sound/oss/trident.h

   1 #ifndef __TRID4DWAVE_H
   2 #define __TRID4DWAVE_H
   3
   4 /*
   5  *  audio@tridentmicro.com
   6  *  Fri Feb 19 15:55:28 MST 1999
   7  *  Definitions for Trident 4DWave DX/NX chips
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  */
  25
  26 /* PCI vendor and device ID */
  27 #ifndef PCI_VENDOR_ID_TRIDENT
  28 #define PCI_VENDOR_ID_TRIDENT           0x1023
  29 #endif
  30
  31 #ifndef PCI_VENDOR_ID_SI
  32 #define PCI_VENDOR_ID_SI                        0x1039
  33 #endif
  34
  35 #ifndef PCI_VENDOR_ID_ALI
  36 #define PCI_VENDOR_ID_ALI                       0x10b9
  37 #endif
  38
  39 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
  40 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
  41 #endif
  42
  43 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
  44 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
  45 #endif
  46
  47 #ifndef PCI_DEVICE_ID_SI_7018
  48 #define PCI_DEVICE_ID_SI_7018           0x7018
  49 #endif
  50
  51 #ifndef PCI_DEVICE_ID_ALI_5451
  52 #define PCI_DEVICE_ID_ALI_5451          0x5451
  53 #endif
  54
  55 #ifndef PCI_DEVICE_ID_ALI_1533
  56 #define PCI_DEVICE_ID_ALI_1533          0x1533
  57 #endif
  58
  59 #ifndef FALSE
  60 #define FALSE           0
  61 #define TRUE            1
  62 #endif
  63
  64 #define CHANNEL_REGS    5
  65 #define CHANNEL_START   0xe0   // The first bytes of the contiguous register space.
  66
  67 #define BANK_A          0
  68 #define BANK_B          1
  69 #define NR_BANKS                2
  70
  71 #define TRIDENT_FMT_STEREO     0x01
  72 #define TRIDENT_FMT_16BIT      0x02
  73 #define TRIDENT_FMT_MASK       0x03
  74
  75 #define DAC_RUNNING     0x01
  76 #define ADC_RUNNING     0x02
  77
  78 /* Register Addresses */
  79
  80 /* operational registers common to DX, NX, 7018 */
  81 enum trident_op_registers {
  82         T4D_GAME_CR     = 0x30, T4D_GAME_LEG    = 0x31,
  83         T4D_GAME_AXD    = 0x34,
  84         T4D_REC_CH      = 0x70,
  85         T4D_START_A     = 0x80, T4D_STOP_A      = 0x84,
  86         T4D_DLY_A       = 0x88, T4D_SIGN_CSO_A  = 0x8c,
  87         T4D_CSPF_A      = 0x90, T4D_CEBC_A      = 0x94,
  88         T4D_AINT_A      = 0x98, T4D_EINT_A      = 0x9c,
  89         T4D_LFO_GC_CIR  = 0xa0, T4D_AINTEN_A    = 0xa4,
  90         T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
  91         T4D_MISCINT     = 0xb0, T4D_START_B     = 0xb4,
  92         T4D_STOP_B      = 0xb8, T4D_CSPF_B      = 0xbc,
  93         T4D_SBBL_SBCL   = 0xc0, T4D_SBCTRL_SBE2R_SBDD    = 0xc4,
  94         T4D_STIMER      = 0xc8, T4D_LFO_B_I2S_DELTA      = 0xcc,
  95         T4D_AINT_B      = 0xd8, T4D_AINTEN_B    = 0xdc,
  96         ALI_MPUR2       = 0x22, ALI_GPIO        = 0x7c,
  97         ALI_EBUF1 = 0xf4,
  98         ALI_EBUF2 = 0xf8
  99 };
 100
 101 enum ali_op_registers {
 102         ALI_SCTRL               = 0x48,
 103         ALI_GLOBAL_CONTROL      = 0xd4,
 104         ALI_STIMER              = 0xc8,
 105         ALI_SPDIF_CS            = 0x70,
 106         ALI_SPDIF_CTRL          = 0x74
 107 };
 108
 109 enum ali_registers_number {
 110         ALI_GLOBAL_REGS         = 56,
 111         ALI_CHANNEL_REGS        = 8,
 112         ALI_MIXER_REGS          = 20
 113 };
 114
 115 enum ali_sctrl_control_bit {
 116         ALI_SPDIF_OUT_ENABLE    = 0x20
 117 };
 118
 119 enum ali_global_control_bit {
 120         ALI_SPDIF_OUT_SEL_PCM   = 0x00000400,
 121         ALI_SPDIF_IN_SUPPORT    = 0x00000800,
 122         ALI_SPDIF_OUT_CH_ENABLE = 0x00008000,
 123         ALI_SPDIF_IN_CH_ENABLE  = 0x00080000,
 124         ALI_PCM_IN_DISABLE      = 0x7fffffff,
 125         ALI_PCM_IN_ENABLE       = 0x80000000,
 126         ALI_SPDIF_IN_CH_DISABLE = 0xfff7ffff,
 127         ALI_SPDIF_OUT_CH_DISABLE = 0xffff7fff,
 128         ALI_SPDIF_OUT_SEL_SPDIF = 0xfffffbff
 129
 130 };
 131
 132 enum ali_spdif_control_bit {
 133         ALI_SPDIF_IN_FUNC_ENABLE        = 0x02,
 134         ALI_SPDIF_IN_CH_STATUS          = 0x40,
 135         ALI_SPDIF_OUT_CH_STATUS         = 0xbf
 136
 137 };
 138
 139 enum ali_control_all {
 140         ALI_DISABLE_ALL_IRQ     = 0,
 141         ALI_CHANNELS            = 32,
 142         ALI_STOP_ALL_CHANNELS   = 0xffffffff,
 143         ALI_MULTI_CHANNELS_START_STOP   = 0x07800000
 144 };
 145
 146 enum ali_EMOD_control_bit {
 147         ALI_EMOD_DEC    = 0x00000000,
 148         ALI_EMOD_INC    = 0x10000000,
 149         ALI_EMOD_Delay  = 0x20000000,
 150         ALI_EMOD_Still  = 0x30000000
 151 };
 152
 153 enum ali_pcm_in_channel_num {
 154         ALI_NORMAL_CHANNEL      = 0,
 155         ALI_SPDIF_OUT_CHANNEL   = 15,
 156         ALI_SPDIF_IN_CHANNEL    = 19,
 157         ALI_LEF_CHANNEL         = 23,
 158         ALI_CENTER_CHANNEL      = 24,
 159         ALI_SURR_RIGHT_CHANNEL  = 25,
 160         ALI_SURR_LEFT_CHANNEL   = 26,
 161         ALI_PCM_IN_CHANNEL      = 31
 162 };
 163
 164 enum ali_pcm_out_channel_num {
 165         ALI_PCM_OUT_CHANNEL_FIRST = 0,
 166         ALI_PCM_OUT_CHANNEL_LAST = 31
 167 };
 168
 169 enum ali_ac97_power_control_bit {
 170         ALI_EAPD_POWER_DOWN     = 0x8000
 171 };
 172
 173 enum ali_update_ptr_flags {
 174         ALI_ADDRESS_INT_UPDATE  = 0x01
 175 };
 176
 177 enum ali_revision {
 178         ALI_5451_V02    = 0x02
 179 };
 180
 181 enum ali_spdif_out_control {
 182         ALI_PCM_TO_SPDIF_OUT            = 0,
 183         ALI_SPDIF_OUT_TO_SPDIF_OUT      = 1,
 184         ALI_SPDIF_OUT_PCM               = 0,
 185         ALI_SPDIF_OUT_NON_PCM           = 2
 186 };
 187
 188 /* S/PDIF Operational Registers for 4D-NX */
 189 enum nx_spdif_registers {
 190         NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
 191         NX_SPESO        = 0x2c, NX_SPCSTATUS = 0x64
 192 };
 193
 194 /* OP registers to access each hardware channel */
 195 enum channel_registers {
 196         CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
 197         CH_DX_FMC_RVOL_CVOL = 0xec,
 198         CH_NX_DELTA_CSO     = 0xe0, CH_NX_DELTA_ESO = 0xe8,
 199         CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
 200         CH_LBA              = 0xe4,
 201         CH_GVSEL_PAN_VOL_CTRL_EC      = 0xf0
 202 };
 203
 204 /* registers to read/write/control AC97 codec */
 205 enum dx_ac97_registers {
 206         DX_ACR0_AC97_W        = 0x40, DX_ACR1_AC97_R = 0x44,
 207         DX_ACR2_AC97_COM_STAT = 0x48
 208 };
 209
 210 enum nx_ac97_registers {
 211         NX_ACR0_AC97_COM_STAT  = 0x40, NX_ACR1_AC97_W           = 0x44,
 212         NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
 213 };
 214
 215 enum si_ac97_registers {
 216         SI_AC97_WRITE       = 0x40, SI_AC97_READ = 0x44,
 217         SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
 218 };
 219
 220 enum ali_ac97_registers {
 221         ALI_AC97_WRITE       = 0x40, ALI_AC97_READ = 0x44
 222 };
 223
 224 /* Bit mask for operational registers */
 225 #define AC97_REG_ADDR      0x000000ff
 226
 227 enum ali_ac97_bits {
 228         ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
 229         ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
 230         ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY  = 0x0080,
 231         ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
 232         ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
 233 };
 234
 235 enum sis7018_ac97_bits {
 236         SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
 237         SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
 238         SI_AC97_SECONDARY  = 0x0080
 239 };
 240
 241 enum trident_dx_ac97_bits {
 242         DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
 243         DX_AC97_READY      = 0x0010, DX_AC97_RECORD    = 0x0008,
 244         DX_AC97_PLAYBACK   = 0x0002
 245 };
 246
 247 enum trident_nx_ac97_bits {
 248         /* ACR1-3 */
 249         NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
 250         NX_AC97_BUSY_DATA  = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
 251         /* ACR0 */
 252         NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
 253         NX_AC97_SURROUND_OUTPUT = 0x0010,
 254         NX_AC97_PRIMARY_READY   = 0x0008, NX_AC97_PRIMARY_RECORD   = 0x0004,
 255         NX_AC97_PCM_OUTPUT      = 0x0002,
 256         NX_AC97_WARM_RESET      = 0x0001
 257 };
 258
 259 enum serial_intf_ctrl_bits {
 260         WARM_REST   = 0x00000001, COLD_RESET  = 0x00000002,
 261         I2S_CLOCK   = 0x00000004, PCM_SEC_AC97= 0x00000008,
 262         AC97_DBL_RATE = 0x00000010, SPDIF_EN  = 0x00000020,
 263         I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
 264         PCMIN       = 0x00000100, LINE1IN     = 0x00000200,
 265         MICIN       = 0x00000400, LINE2IN     = 0x00000800,
 266         HEAD_SET_IN = 0x00001000, GPIOIN      = 0x00002000,
 267         /* 7018 spec says id = 01 but the demo board routed to 10
 268            SECONDARY_ID= 0x00004000, */
 269         SECONDARY_ID= 0x00004000,
 270         PCMOUT      = 0x00010000, SURROUT     = 0x00020000,
 271         CENTEROUT   = 0x00040000, LFEOUT      = 0x00080000,
 272         LINE1OUT    = 0x00100000, LINE2OUT    = 0x00200000,
 273         GPIOOUT     = 0x00400000,
 274         SI_AC97_PRIMARY_READY   = 0x01000000,
 275         SI_AC97_SECONDARY_READY = 0x02000000,
 276 };
 277
 278 enum global_control_bits {
 279         CHANNLE_IDX = 0x0000003f, PB_RESET    = 0x00000100,
 280         PAUSE_ENG   = 0x00000200,
 281         OVERRUN_IE  = 0x00000400, UNDERRUN_IE = 0x00000800,
 282         ENDLP_IE    = 0x00001000, MIDLP_IE    = 0x00002000,
 283         ETOG_IE     = 0x00004000,
 284         EDROP_IE    = 0x00008000, BANK_B_EN   = 0x00010000
 285 };
 286
 287 enum channel_control_bits {
 288         CHANNEL_LOOP   = 0x00001000, CHANNEL_SIGNED = 0x00002000,
 289         CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
 290 };
 291
 292 enum channel_attribute {
 293         /* playback/record select */
 294         CHANNEL_PB     = 0x0000, CHANNEL_SPC_PB = 0x4000,
 295         CHANNEL_REC    = 0x8000, CHANNEL_REC_PB = 0xc000,
 296         /* playback destination/record source select */
 297         MODEM_LINE1    = 0x0000, MODEM_LINE2    = 0x0400,
 298         PCM_LR         = 0x0800, HSET           = 0x0c00,
 299         I2S_LR         = 0x1000, CENTER_LFE     = 0x1400,
 300         SURR_LR        = 0x1800, SPDIF_LR       = 0x1c00,
 301         MIC            = 0x1400,
 302         /* mist stuff */
 303         MONO_LEFT      = 0x0000, MONO_RIGHT     = 0x0100,
 304         MONO_MIX       = 0x0200, SRC_ENABLE     = 0x0080,
 305 };
 306
 307 enum miscint_bits {
 308         PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
 309         SB_IRQ          = 0x00000004, MPU401_IRQ      = 0x00000008,
 310         OPL3_IRQ        = 0x00000010, ADDRESS_IRQ     = 0x00000020,
 311         ENVELOPE_IRQ    = 0x00000040, ST_IRQ          = 0x00000080,
 312         PB_UNDERRUN     = 0x00000100, REC_OVERRUN     = 0x00000200,
 313         MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW  = 0x00000800,
 314         ST_TARGET_REACHED = 0x00008000, PB_24K_MODE   = 0x00010000,
 315         ST_IRQ_EN       = 0x00800000, ACGPIO_IRQ      = 0x01000000
 316 };
 317
 318 #define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
 319
 320 #define         CYBER_PORT_AUDIO                0x3CE
 321 #define         CYBER_IDX_AUDIO_ENABLE          0x7B
 322 #define         CYBER_BMSK_AUDIO_INT_ENABLE     0x09
 323 #define         CYBER_BMSK_AUENZ                0x01
 324 #define         CYBER_BMSK_AUENZ_ENABLE         0x00
 325 #define         CYBER_IDX_IRQ_ENABLE            0x12
 326
 327 #define VALIDATE_MAGIC(FOO,MAG)                         \
 328 ({                                                      \
 329         if (!(FOO) || (FOO)->magic != MAG) {            \
 330                 printk(invalid_magic,__FUNCTION__);     \
 331                 return -ENXIO;                          \
 332         }                                               \
 333 })
 334
 335 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
 336 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
 337
 338 static inline unsigned ld2(unsigned int x)
 339 {
 340         unsigned r = 0;
 341
 342         if (x >= 0x10000) {
 343                 x >>= 16;
 344                 r += 16;
 345         }
 346         if (x >= 0x100) {
 347                 x >>= 8;
 348                 r += 8;
 349         }
 350         if (x >= 0x10) {
 351                 x >>= 4;
 352                 r += 4;
 353         }
 354         if (x >= 4) {
 355                 x >>= 2;
 356                 r += 2;
 357         }
 358         if (x >= 2)
 359                 r++;
 360         return r;
 361 }
 362
 363 #ifdef DEBUG
 364
 365 #define TRDBG(msg, args...) do {          \
 366         printk(KERN_DEBUG msg , ##args ); \
 367 } while (0)
 368
 369 #else /* !defined(DEBUG) */
 370
 371 #define TRDBG(msg, args...) do { } while (0)
 372
 373 #endif /* DEBUG */
 374
 375 #endif /* __TRID4DWAVE_H */