2 * linux/arch/alpha/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
14 * "A Kernel Model for Precision Timekeeping" by Dave Mills
15 * 1997-01-09 Adrian Sun
16 * use interval timer if CONFIG_RTC=y
17 * 1997-10-29 John Bowman (bowman@math.ualberta.ca)
18 * fixed tick loss calculation in timer_interrupt
19 * (round system clock to nearest tick instead of truncating)
20 * fixed algorithm in time_init for getting time from CMOS clock
21 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
22 * fixed algorithm in do_gettimeofday() for calculating the precise time
23 * from processor cycle counter (now taking lost_ticks into account)
24 * 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
25 * Fixed time_init to be aware of epoches != 1900. This prevents
26 * booting up in 2048 for me;) Code is stolen from rtc.c.
28 #include <linux/config.h>
29 #include <linux/errno.h>
30 #include <linux/sched.h>
31 #include <linux/kernel.h>
32 #include <linux/param.h>
33 #include <linux/string.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/irq.h>
38 #include <linux/interrupt.h>
39 #include <linux/init.h>
40 #include <linux/bcd.h>
42 #include <asm/uaccess.h>
44 #include <asm/hwrpb.h>
46 #include <linux/mc146818rtc.h>
47 #include <linux/time.h>
48 #include <linux/timex.h>
53 u64 jiffies_64
= INITIAL_JIFFIES
;
55 extern unsigned long wall_jiffies
; /* kernel/timer.c */
57 static int set_rtc_mmss(unsigned long);
59 spinlock_t rtc_lock
= SPIN_LOCK_UNLOCKED
;
61 #define TICK_SIZE (tick_nsec / 1000)
64 * Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
65 * by 48 gives us 16 bits for HZ while keeping the accuracy good even
66 * for large CPU clock rates.
70 /* lump static variables together for more efficient access: */
72 /* cycle counter last time it got invoked */
74 /* ticks/cycle * 2^48 */
75 unsigned long scaled_ticks_per_cycle
;
76 /* last time the CMOS clock got updated */
77 time_t last_rtc_update
;
78 /* partial unused tick */
79 unsigned long partial_tick
;
82 unsigned long est_cycle_freq
;
85 static inline __u32
rpcc(void)
88 asm volatile ("rpcc %0" : "=r"(result
));
94 * timer_interrupt() needs to keep up the real-time clock,
95 * as well as call the "do_timer()" routine every clocktick
97 irqreturn_t
timer_interrupt(int irq
, void *dev
, struct pt_regs
* regs
)
104 /* Not SMP, do kernel PC profiling here. */
105 if (!user_mode(regs
))
106 alpha_do_profile(regs
->pc
);
109 write_seqlock(&xtime_lock
);
112 * Calculate how many ticks have passed since the last update,
113 * including any previous partial leftover. Save any resulting
114 * fraction for the next pass.
117 delta
= now
- state
.last_time
;
118 state
.last_time
= now
;
119 delta
= delta
* state
.scaled_ticks_per_cycle
+ state
.partial_tick
;
120 state
.partial_tick
= delta
& ((1UL << FIX_SHIFT
) - 1);
121 nticks
= delta
>> FIX_SHIFT
;
129 * If we have an externally synchronized Linux clock, then update
130 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
131 * called as close as possible to 500 ms before the new second starts.
133 if ((time_status
& STA_UNSYNC
) == 0
134 && xtime
.tv_sec
> state
.last_rtc_update
+ 660
135 && xtime
.tv_nsec
>= 500000 - ((unsigned) TICK_SIZE
) / 2
136 && xtime
.tv_nsec
<= 500000 + ((unsigned) TICK_SIZE
) / 2) {
137 int tmp
= set_rtc_mmss(xtime
.tv_sec
);
138 state
.last_rtc_update
= xtime
.tv_sec
- (tmp
? 600 : 0);
141 write_sequnlock(&xtime_lock
);
146 common_init_rtc(void)
150 /* Reset periodic interrupt frequency. */
151 x
= CMOS_READ(RTC_FREQ_SELECT
) & 0x3f;
152 if (x
!= 0x26 && x
!= 0x19 && x
!= 0x06) {
153 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x
);
154 CMOS_WRITE(0x26, RTC_FREQ_SELECT
);
157 /* Turn on periodic interrupts. */
158 x
= CMOS_READ(RTC_CONTROL
);
159 if (!(x
& RTC_PIE
)) {
160 printk("Turning on RTC interrupts.\n");
162 x
&= ~(RTC_AIE
| RTC_UIE
);
163 CMOS_WRITE(x
, RTC_CONTROL
);
165 (void) CMOS_READ(RTC_INTR_FLAGS
);
167 outb(0x36, 0x43); /* pit counter 0: system timer */
171 outb(0xb6, 0x43); /* pit counter 2: speaker */
179 /* Validate a computed cycle counter result against the known bounds for
180 the given processor core. There's too much brokenness in the way of
181 timing hardware for any one method to work everywhere. :-(
183 Return 0 if the result cannot be trusted, otherwise return the argument. */
185 static unsigned long __init
186 validate_cc_value(unsigned long cc
)
188 static struct bounds
{
189 unsigned int min
, max
;
190 } cpu_hz
[] __initdata
= {
191 [EV3_CPU
] = { 50000000, 200000000 }, /* guess */
192 [EV4_CPU
] = { 100000000, 300000000 },
193 [LCA4_CPU
] = { 100000000, 300000000 }, /* guess */
194 [EV45_CPU
] = { 200000000, 300000000 },
195 [EV5_CPU
] = { 250000000, 433000000 },
196 [EV56_CPU
] = { 333000000, 667000000 },
197 [PCA56_CPU
] = { 400000000, 600000000 }, /* guess */
198 [PCA57_CPU
] = { 500000000, 600000000 }, /* guess */
199 [EV6_CPU
] = { 466000000, 600000000 },
200 [EV67_CPU
] = { 600000000, 750000000 },
201 [EV68AL_CPU
] = { 750000000, 940000000 },
202 [EV68CB_CPU
] = { 1000000000, 1333333333 },
203 /* None of the following are shipping as of 2001-11-01. */
204 [EV68CX_CPU
] = { 1000000000, 1700000000 }, /* guess */
205 [EV69_CPU
] = { 1000000000, 1700000000 }, /* guess */
206 [EV7_CPU
] = { 800000000, 1400000000 }, /* guess */
207 [EV79_CPU
] = { 1000000000, 2000000000 }, /* guess */
210 /* Allow for some drift in the crystal. 10MHz is more than enough. */
211 const unsigned int deviation
= 10000000;
213 struct percpu_struct
*cpu
;
216 cpu
= (struct percpu_struct
*)((char*)hwrpb
+ hwrpb
->processor_offset
);
217 index
= cpu
->type
& 0xffffffff;
219 /* If index out of bounds, no way to validate. */
220 if (index
>= sizeof(cpu_hz
)/sizeof(cpu_hz
[0]))
223 /* If index contains no data, no way to validate. */
224 if (cpu_hz
[index
].max
== 0)
227 if (cc
< cpu_hz
[index
].min
- deviation
228 || cc
> cpu_hz
[index
].max
+ deviation
)
236 * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
240 #define CALIBRATE_LATCH (52 * LATCH)
241 #define CALIBRATE_TIME (52 * 1000020 / HZ)
243 static unsigned long __init
244 calibrate_cc_with_pic(void)
248 /* Set the Gate high, disable speaker */
249 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
252 * Now let's take care of CTC channel 2
254 * Set the Gate high, program CTC channel 2 for mode 0,
255 * (interrupt on terminal count mode), binary count,
256 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
258 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
259 outb(CALIBRATE_LATCH
& 0xff, 0x42); /* LSB of count */
260 outb(CALIBRATE_LATCH
>> 8, 0x42); /* MSB of count */
264 count
+=100; /* by 1 takes too long to timeout from 0 */
265 } while ((inb(0x61) & 0x20) == 0 && count
> 0);
268 /* Error: ECTCNEVERSET or ECPUTOOFAST. */
272 /* Error: ECPUTOOSLOW. */
273 if (cc
<= CALIBRATE_TIME
)
276 return (cc
* 1000000UL) / CALIBRATE_TIME
;
279 /* The Linux interpretation of the CMOS clock register contents:
280 When the Update-In-Progress (UIP) flag goes from 1 to 0, the
281 RTC registers show the second which has precisely just started.
282 Let's hope other operating systems interpret the RTC the same way. */
284 static unsigned long __init
285 rpcc_after_update_in_progress(void)
287 do { } while (!(CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
));
288 do { } while (CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
);
296 unsigned int year
, mon
, day
, hour
, min
, sec
, cc1
, cc2
, epoch
;
297 unsigned long cycle_freq
, one_percent
;
300 /* Calibrate CPU clock -- attempt #1. */
302 est_cycle_freq
= validate_cc_value(calibrate_cc_with_pic());
304 cc1
= rpcc_after_update_in_progress();
306 /* Calibrate CPU clock -- attempt #2. */
307 if (!est_cycle_freq
) {
308 cc2
= rpcc_after_update_in_progress();
309 est_cycle_freq
= validate_cc_value(cc2
- cc1
);
313 cycle_freq
= hwrpb
->cycle_freq
;
314 if (est_cycle_freq
) {
315 /* If the given value is within 1% of what we calculated,
316 accept it. Otherwise, use what we found. */
317 one_percent
= cycle_freq
/ 100;
318 diff
= cycle_freq
- est_cycle_freq
;
321 if ((unsigned long)diff
> one_percent
) {
322 cycle_freq
= est_cycle_freq
;
323 printk("HWRPB cycle frequency bogus. "
324 "Estimated %lu Hz\n", cycle_freq
);
328 } else if (! validate_cc_value (cycle_freq
)) {
329 printk("HWRPB cycle frequency bogus, "
330 "and unable to estimate a proper value!\n");
333 /* From John Bowman <bowman@math.ualberta.ca>: allow the values
334 to settle, as the Update-In-Progress bit going low isn't good
335 enough on some hardware. 2ms is our guess; we haven't found
336 bogomips yet, but this is close on a 500Mhz box. */
339 sec
= CMOS_READ(RTC_SECONDS
);
340 min
= CMOS_READ(RTC_MINUTES
);
341 hour
= CMOS_READ(RTC_HOURS
);
342 day
= CMOS_READ(RTC_DAY_OF_MONTH
);
343 mon
= CMOS_READ(RTC_MONTH
);
344 year
= CMOS_READ(RTC_YEAR
);
346 if (!(CMOS_READ(RTC_CONTROL
) & RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
355 /* PC-like is standard; used for year < 20 || year >= 70 */
359 else if (year
>= 20 && year
< 48)
362 else if (year
>= 48 && year
< 70)
363 /* Digital UNIX epoch */
366 printk(KERN_INFO
"Using epoch = %d\n", epoch
);
368 if ((year
+= epoch
) < 1970)
371 xtime
.tv_sec
= mktime(year
, mon
, day
, hour
, min
, sec
);
374 wall_to_monotonic
.tv_sec
-= xtime
.tv_sec
;
375 wall_to_monotonic
.tv_nsec
= 0;
378 extern void __you_loose (void);
382 state
.last_time
= cc1
;
383 state
.scaled_ticks_per_cycle
384 = ((unsigned long) HZ
<< FIX_SHIFT
) / cycle_freq
;
385 state
.last_rtc_update
= 0;
386 state
.partial_tick
= 0L;
388 /* Startup the timer source. */
393 * Use the cycle counter to estimate an displacement from the last time
394 * tick. Unfortunately the Alpha designers made only the low 32-bits of
395 * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
396 * part. So we can't do the "find absolute time in terms of cycles" thing
397 * that the other ports do.
400 do_gettimeofday(struct timeval
*tv
)
403 unsigned long sec
, usec
, lost
, seq
;
404 unsigned long delta_cycles
, delta_usec
, partial_tick
;
407 seq
= read_seqbegin_irqsave(&xtime_lock
, flags
);
409 delta_cycles
= rpcc() - state
.last_time
;
411 usec
= (xtime
.tv_nsec
/ 1000);
412 partial_tick
= state
.partial_tick
;
413 lost
= jiffies
- wall_jiffies
;
415 } while (read_seqretry_irqrestore(&xtime_lock
, seq
, flags
));
418 /* Until and unless we figure out how to get cpu cycle counters
419 in sync and keep them there, we can't use the rpcc tricks. */
420 delta_usec
= lost
* (1000000 / HZ
);
423 * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
424 * = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
425 * = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
427 * which, given a 600MHz cycle and a 1024Hz tick, has a
428 * dynamic range of about 1.7e17, which is less than the
429 * 1.8e19 in an unsigned long, so we are safe from overflow.
431 * Round, but with .5 up always, since .5 to even is harder
432 * with no clear gain.
435 delta_usec
= (delta_cycles
* state
.scaled_ticks_per_cycle
437 + (lost
<< FIX_SHIFT
)) * 15625;
438 delta_usec
= ((delta_usec
/ ((1UL << (FIX_SHIFT
-6-1)) * HZ
)) + 1) / 2;
442 if (usec
>= 1000000) {
452 do_settimeofday(struct timespec
*tv
)
454 time_t wtm_sec
, sec
= tv
->tv_sec
;
455 long wtm_nsec
, nsec
= tv
->tv_nsec
;
456 unsigned long delta_nsec
;
458 if ((unsigned long)tv
->tv_nsec
>= NSEC_PER_SEC
)
461 write_seqlock_irq(&xtime_lock
);
463 /* The offset that is added into time in do_gettimeofday above
464 must be subtracted out here to keep a coherent view of the
465 time. Without this, a full-tick error is possible. */
468 delta_nsec
= (jiffies
- wall_jiffies
) * (NSEC_PER_SEC
/ HZ
);
470 delta_nsec
= rpcc() - state
.last_time
;
471 delta_nsec
= (delta_nsec
* state
.scaled_ticks_per_cycle
473 + ((jiffies
- wall_jiffies
) << FIX_SHIFT
)) * 15625;
474 delta_nsec
= ((delta_nsec
/ ((1UL << (FIX_SHIFT
-6-1)) * HZ
)) + 1) / 2;
480 wtm_sec
= wall_to_monotonic
.tv_sec
+ (xtime
.tv_sec
- sec
);
481 wtm_nsec
= wall_to_monotonic
.tv_nsec
+ (xtime
.tv_nsec
- nsec
);
483 set_normalized_timespec(&xtime
, sec
, nsec
);
484 set_normalized_timespec(&wall_to_monotonic
, wtm_sec
, wtm_nsec
);
486 time_adjust
= 0; /* stop active adjtime() */
487 time_status
|= STA_UNSYNC
;
488 time_maxerror
= NTP_PHASE_LIMIT
;
489 time_esterror
= NTP_PHASE_LIMIT
;
491 write_sequnlock_irq(&xtime_lock
);
497 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
498 * called 500 ms after the second nowtime has started, because when
499 * nowtime is written into the registers of the CMOS clock, it will
500 * jump to the next second precisely 500 ms later. Check the Motorola
501 * MC146818A or Dallas DS12887 data sheet for details.
503 * BUG: This routine does not handle hour overflow properly; it just
504 * sets the minutes. Usually you won't notice until after reboot!
510 set_rtc_mmss(unsigned long nowtime
)
513 int real_seconds
, real_minutes
, cmos_minutes
;
514 unsigned char save_control
, save_freq_select
;
516 /* irq are locally disabled here */
517 spin_lock(&rtc_lock
);
518 /* Tell the clock it's being set */
519 save_control
= CMOS_READ(RTC_CONTROL
);
520 CMOS_WRITE((save_control
|RTC_SET
), RTC_CONTROL
);
522 /* Stop and reset prescaler */
523 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
524 CMOS_WRITE((save_freq_select
|RTC_DIV_RESET2
), RTC_FREQ_SELECT
);
526 cmos_minutes
= CMOS_READ(RTC_MINUTES
);
527 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
528 BCD_TO_BIN(cmos_minutes
);
531 * since we're only adjusting minutes and seconds,
532 * don't interfere with hour overflow. This avoids
533 * messing with unknown time zones but requires your
534 * RTC not to be off by more than 15 minutes
536 real_seconds
= nowtime
% 60;
537 real_minutes
= nowtime
/ 60;
538 if (((abs(real_minutes
- cmos_minutes
) + 15)/30) & 1) {
539 /* correct for half hour time zone */
544 if (abs(real_minutes
- cmos_minutes
) < 30) {
545 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
546 BIN_TO_BCD(real_seconds
);
547 BIN_TO_BCD(real_minutes
);
549 CMOS_WRITE(real_seconds
,RTC_SECONDS
);
550 CMOS_WRITE(real_minutes
,RTC_MINUTES
);
553 "set_rtc_mmss: can't update from %d to %d\n",
554 cmos_minutes
, real_minutes
);
558 /* The following flags have to be released exactly in this order,
559 * otherwise the DS12887 (popular MC146818A clone with integrated
560 * battery and quartz) will not reset the oscillator and will not
561 * update precisely 500 ms later. You won't find this mentioned in
562 * the Dallas Semiconductor data sheets, but who believes data
563 * sheets anyway ... -- Markus Kuhn
565 CMOS_WRITE(save_control
, RTC_CONTROL
);
566 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
567 spin_unlock(&rtc_lock
);