include/asm-cris/sv_addr_ag.h

   1 /*!**************************************************************************
   2 *!
   3 *! MACROS:
   4 *!   IO_MASK(reg,field)
   5 *!   IO_STATE(reg,field,state)
   6 *!   IO_EXTRACT(reg,field,val)
   7 *!   IO_STATE_VALUE(reg,field,state)
   8 *!   IO_BITNR(reg,field)
   9 *!   IO_WIDTH(reg,field)
  10 *!   IO_FIELD(reg,field,val)
  11 *!   IO_RD(reg)
  12 *!   All moderegister addresses and fields of these.
  13 *!
  14 *!**************************************************************************/
  15
  16 #ifndef __sv_addr_ag_h__
  17 #define __sv_addr_ag_h__
  18
  19
  20 #define __test_sv_addr__ 0
  21
  22 /*------------------------------------------------------------
  23 !* General macros to manipulate moderegisters.
  24 !*-----------------------------------------------------------*/
  25
  26 /* IO_MASK returns a mask for a specified bitfield in a register.
  27    Note that this macro doesn't work when field width is 32 bits. */
  28 #define IO_MASK(reg,field) \
  29     ( ( ( 1 << reg##__##field##__WIDTH ) - 1 ) << reg##__##field##__BITNR )
  30
  31 /* IO_STATE returns a constant corresponding to a one of the symbolic
  32    states that the bitfield can have. (Shifted to correct position)  */
  33 #define IO_STATE(reg,field,state) \
  34     ( reg##__##field##__##state << reg##__##field##__BITNR )
  35
  36 /* IO_EXTRACT returns the masked and shifted value corresponding to the
  37    bitfield can have. */
  38 #define IO_EXTRACT(reg,field,val) ( (( ( ( 1 << reg##__##field##__WIDTH ) \
  39      - 1 ) << reg##__##field##__BITNR ) & (val)) >> reg##__##field##__BITNR )
  40
  41 /* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
  42    states that the bitfield can have. (Not shifted)  */
  43 #define IO_STATE_VALUE(reg,field,state) ( reg##__##field##__##state )
  44
  45 /* IO_FIELD shifts the val parameter to be aligned with the bitfield
  46    specified. */
  47 #define IO_FIELD(reg,field,val) ((val) << reg##__##field##__BITNR)
  48
  49 /* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
  50    LSB and the returned bitnumber is LSB of the field. */
  51 #define IO_BITNR(reg,field) (reg##__##field##__BITNR)
  52
  53 /* IO_WIDTH returns the width, in bits, of a bitfield. */
  54 #define IO_WIDTH(reg,field) (reg##__##field##__WIDTH)
  55
  56 /*--- Obsolete. Kept for backw compatibility. ---*/
  57 /* Reads (or writes) a byte/uword/udword from the specified mode
  58    register. */
  59 #define IO_RD(reg) (*(volatile u32*)(reg))
  60 #define IO_RD_B(reg) (*(volatile u8*)(reg))
  61 #define IO_RD_W(reg) (*(volatile u16*)(reg))
  62 #define IO_RD_D(reg) (*(volatile u32*)(reg))
  63
  64 /*------------------------------------------------------------
  65 !* Start addresses of the different memory areas.
  66 !*-----------------------------------------------------------*/
  67
  68 #define MEM_CSE0_START (0x00000000)
  69 #define MEM_CSE1_START (0x04000000)
  70 #define MEM_CSR0_START (0x08000000)
  71 #define MEM_CSR1_START (0x0c000000)
  72 #define MEM_CSP0_START (0x10000000)
  73 #define MEM_CSP1_START (0x14000000)
  74 #define MEM_CSP2_START (0x18000000)
  75 #define MEM_CSP3_START (0x1c000000)
  76 #define MEM_CSP4_START (0x20000000)
  77 #define MEM_CSP5_START (0x24000000)
  78 #define MEM_CSP6_START (0x28000000)
  79 #define MEM_CSP7_START (0x2c000000)
  80 #define MEM_DRAM_START (0x40000000)
  81
  82 #define MEM_NON_CACHEABLE (0x80000000)
  83
  84 /*------------------------------------------------------------
  85 !* Type casts used in mode register macros, making pointer
  86 !* dereferencing possible. Empty in assembler.
  87 !*-----------------------------------------------------------*/
  88
  89 #ifndef __ASSEMBLER__
  90 # define  IO_TYPECAST_UDWORD  (volatile u32*)
  91 # define  IO_TYPECAST_RO_UDWORD  (const volatile u32*)
  92 # define  IO_TYPECAST_UWORD  (volatile u16*)
  93 # define  IO_TYPECAST_RO_UWORD  (const volatile u16*)
  94 # define  IO_TYPECAST_BYTE  (volatile u8*)
  95 # define  IO_TYPECAST_RO_BYTE  (const volatile u8*)
  96 #else
  97 # define  IO_TYPECAST_UDWORD
  98 # define  IO_TYPECAST_RO_UDWORD
  99 # define  IO_TYPECAST_UWORD
 100 # define  IO_TYPECAST_RO_UWORD
 101 # define  IO_TYPECAST_BYTE
 102 # define  IO_TYPECAST_RO_BYTE
 103 #endif
 104
 105 /*------------------------------------------------------------*/
 106
 107 #include "sv_addr.agh"
 108
 109 #if __test_sv_addr__
 110 /* IO_MASK( R_BUS_CONFIG , CE ) */
 111 IO_MASK( R_WAITSTATES , SRAM_WS )
 112 IO_MASK( R_TEST , W32 )
 113
 114 IO_STATE( R_BUS_CONFIG, CE, DISABLE )
 115 IO_STATE( R_BUS_CONFIG, CE, ENABLE )
 116
 117 IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
 118
 119 IO_MASK( R_DRAM_TIMING, REF )
 120
 121 IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
 122
 123 IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S )
 124    == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
 125 #endif
 126
 127
 128 #endif  /* ifndef __sv_addr_ag_h__ */
 129