arch/ppc/platforms/sandpoint_setup.c

   1 /*
   2  * arch/ppc/platforms/sandpoint_setup.c
   3  *
   4  * Board setup routines for the Motorola SPS Sandpoint Test Platform.
   5  *
   6  * Author: Mark A. Greer
   7  *         mgreer@mvista.com
   8  *
   9  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file adds support for the Motorola SPS Sandpoint Test Platform.
  17  * These boards have a PPMC slot for the processor so any combination
  18  * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
  19  * module from Motorola SPS and other closely related cpu/host bridge
  20  * combinations (e.g., 750/755/7400 with MPC107 host bridge).
  21  * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
  22  * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
  23  * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
  24  * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
  25  * but are really 5V).
  26  *
  27  * The firmware on the sandpoint is called DINK (not my acronym :).  This port
  28  * depends on DINK to do some basic initialization (e.g., initialize the memory
  29  * ctlr) and to ensure that the processor is using MAP B (CHRP map).
  30  *
  31  * The switch settings for the Sandpoint board MUST be as follows:
  32  *      S3: down
  33  *      S4: up
  34  *      S5: up
  35  *      S6: down
  36  *
  37  * 'down' is in the direction from the PCI slots towards the PPMC slot;
  38  * 'up' is in the direction from the PPMC slot towards the PCI slots.
  39  * Be careful, the way the sandpoint board is installed in XT chasses will
  40  * make the directions reversed.
  41  *
  42  * Since Motorola listened to our suggestions for improvement, we now have
  43  * the Sandpoint X3 board.  All of the PCI slots are available, it uses
  44  * the serial interrupt interface (just a hardware thing we need to
  45  * configure properly).
  46  *
  47  * Use the default X3 switch settings.  The interrupts are then:
  48  *              EPIC    Source
  49  *                0     SIOINT          (8259, active low)
  50  *                1     PCI #1
  51  *                2     PCI #2
  52  *                3     PCI #3
  53  *                4     PCI #4
  54  *                7     Winbond INTC    (IDE interrupt)
  55  *                8     Winbond INTD    (IDE interrupt)
  56  *
  57  */
  58 #include <linux/config.h>
  59 #include <linux/stddef.h>
  60 #include <linux/kernel.h>
  61 #include <linux/init.h>
  62 #include <linux/errno.h>
  63 #include <linux/reboot.h>
  64 #include <linux/pci.h>
  65 #include <linux/kdev_t.h>
  66 #include <linux/major.h>
  67 #include <linux/initrd.h>
  68 #include <linux/console.h>
  69 #include <linux/delay.h>
  70 #include <linux/irq.h>
  71 #include <linux/ide.h>
  72 #include <linux/seq_file.h>
  73 #include <linux/root_dev.h>
  74
  75 #include <asm/system.h>
  76 #include <asm/pgtable.h>
  77 #include <asm/page.h>
  78 #include <asm/time.h>
  79 #include <asm/dma.h>
  80 #include <asm/io.h>
  81 #include <asm/machdep.h>
  82 #include <asm/prom.h>
  83 #include <asm/smp.h>
  84 #include <asm/vga.h>
  85 #include <asm/open_pic.h>
  86 #include <asm/i8259.h>
  87 #include <asm/todc.h>
  88 #include <asm/bootinfo.h>
  89 #include <asm/mpc10x.h>
  90 #include <asm/pci-bridge.h>
  91
  92 #include "sandpoint.h"
  93
  94 extern u_int openpic_irq(void);
  95 extern void openpic_eoi(void);
  96
  97 static void     sandpoint_halt(void);
  98
  99
 100 /*
 101  * *** IMPORTANT ***
 102  *
 103  * The first 16 entries of 'sandpoint_openpic_initsenses[]' are there and
 104  * initialized to 0 on purpose.  DO NOT REMOVE THEM as the 'offset' parameter
 105  * of 'openpic_init()' does not work for the sandpoint because the 8259
 106  * interrupt is NOT routed to the EPIC's IRQ 0 AND the EPIC's IRQ 0's offset is
 107  * the same as a normal openpic's IRQ 16 offset.
 108  */
 109 static u_char sandpoint_openpic_initsenses[] __initdata = {
 110         0,      /* 0-15 not used by EPCI but by 8259 (std PC-type IRQs) */
 111         0,      /* 1 */
 112         0,      /* 2 */
 113         0,      /* 3 */
 114         0,      /* 4 */
 115         0,      /* 5 */
 116         0,      /* 6 */
 117         0,      /* 7 */
 118         0,      /* 8 */
 119         0,      /* 9 */
 120         0,      /* 10 */
 121         0,      /* 11 */
 122         0,      /* 12 */
 123         0,      /* 13 */
 124         0,      /* 14 */
 125         0,      /* 15 */
 126 #ifdef CONFIG_SANDPOINT_X3
 127         1,      /* 16: EPIC IRQ 0: Active Low -- SIOINT (8259) */
 128  0, /* AACK!  Shouldn't need this.....see sandpoint_pci.c for more info */
 129         1,      /* 17: EPIC IRQ 1: Active Low -- PCI Slot 1 */
 130         1,      /* 18: EPIC IRQ 2: Active Low -- PCI Slot 2 */
 131         1,      /* 19: EPIC IRQ 3: Active Low -- PCI Slot 3 */
 132         1,      /* 20: EPIC IRQ 4: Active Low -- PCI Slot 4 */
 133         0,      /* 21 -- Unused */
 134         0,      /* 22 -- Unused */
 135         1,      /* 23 -- IDE (Winbond INT C)  */
 136         1,      /* 24 -- IDE (Winbond INT D)  */
 137                 /* 35 - 31 (EPIC 9 - 15) Unused */
 138 #else
 139         1,      /* 16: EPIC IRQ 0: Active Low -- PCI intrs */
 140         1,      /* 17: EPIC IRQ 1: Active Low -- PCI (possibly 8259) intrs */
 141         1,      /* 18: EPIC IRQ 2: Active Low -- PCI (possibly 8259) intrs  */
 142         1       /* 19: EPIC IRQ 3: Active Low -- PCI intrs */
 143                 /* 20: EPIC IRQ 4: Not used */
 144 #endif
 145 };
 146
 147 static void __init
 148 sandpoint_setup_arch(void)
 149 {
 150         loops_per_jiffy = 100000000 / HZ;
 151
 152 #ifdef CONFIG_BLK_DEV_INITRD
 153         if (initrd_start)
 154                 ROOT_DEV = Root_RAM0;
 155         else
 156 #endif
 157 #ifdef  CONFIG_ROOT_NFS
 158                 ROOT_DEV = Root_NFS;
 159 #else
 160                 ROOT_DEV = Root_HDA1;
 161 #endif
 162
 163         /* Lookup PCI host bridges */
 164         sandpoint_find_bridges();
 165
 166 #ifdef CONFIG_DUMMY_CONSOLE
 167         conswitchp = &dummy_con;
 168 #endif
 169
 170         printk("Motorola SPS Sandpoint Test Platform\n");
 171         printk("Sandpoint port (MontaVista Software, Inc. (source@mvista.com))\n");
 172
 173         /* The Sandpoint rom doesn't enable any caches.  Do that now.
 174          * The 7450 portion will also set up the L3s once I get enough
 175          * information do do so.  If the processor running doesn't have
 176          * and L2, the _set_L2CR is a no-op.
 177          */
 178         if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450) {
 179                 /* Just enable L2, the bits are different from others.
 180                 */
 181                 _set_L2CR(L2CR_L2E);
 182         }
 183         else {
 184                 /* The magic number for Sandpoint/74xx PrPMCs.
 185                 */
 186                 _set_L2CR(0xbd014000);
 187         }
 188 }
 189
 190 #define SANDPOINT_87308_CFG_ADDR                0x15c
 191 #define SANDPOINT_87308_CFG_DATA                0x15d
 192
 193 #define SANDPOINT_87308_CFG_INB(addr, byte) {                           \
 194         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 195         (byte) = inb(SANDPOINT_87308_CFG_DATA);                         \
 196 }
 197
 198 #define SANDPOINT_87308_CFG_OUTB(addr, byte) {                          \
 199         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 200         outb((byte), SANDPOINT_87308_CFG_DATA);                         \
 201 }
 202
 203 #define SANDPOINT_87308_SELECT_DEV(dev_num) {                           \
 204         SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));                      \
 205 }
 206
 207 #define SANDPOINT_87308_DEV_ENABLE(dev_num) {                           \
 208         SANDPOINT_87308_SELECT_DEV(dev_num);                            \
 209         SANDPOINT_87308_CFG_OUTB(0x30, 0x01);                           \
 210 }
 211
 212 /*
 213  * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
 214  */
 215 static void __init
 216 sandpoint_setup_natl_87308(void)
 217 {
 218         u_char  reg;
 219
 220         /*
 221          * Enable all the devices on the Super I/O chip.
 222          */
 223         SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
 224         SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
 225         SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
 226         SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
 227         SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
 228         SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
 229         SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
 230         SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
 231         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 232         SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
 233         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 234
 235         /* Set up floppy in PS/2 mode */
 236         outb(0x09, SIO_CONFIG_RA);
 237         reg = inb(SIO_CONFIG_RD);
 238         reg = (reg & 0x3F) | 0x40;
 239         outb(reg, SIO_CONFIG_RD);
 240         outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
 241
 242         return;
 243 }
 244
 245 /*
 246  * Fix IDE interrupts.
 247  */
 248 static void __init
 249 sandpoint_fix_winbond_83553(void)
 250 {
 251         /* Make all 8259 interrupt level sensitive */
 252         outb(0xf8, 0x4d0);
 253         outb(0xde, 0x4d1);
 254
 255         return;
 256 }
 257
 258 static void __init
 259 sandpoint_init2(void)
 260 {
 261         /* Do Sandpoint board specific initialization.  */
 262         sandpoint_fix_winbond_83553();
 263         sandpoint_setup_natl_87308();
 264
 265         request_region(0x00,0x20,"dma1");
 266         request_region(0x20,0x20,"pic1");
 267         request_region(0x40,0x20,"timer");
 268         request_region(0x80,0x10,"dma page reg");
 269         request_region(0xa0,0x20,"pic2");
 270         request_region(0xc0,0x20,"dma2");
 271
 272         return;
 273 }
 274
 275 /*
 276  * Interrupt setup and service.  Interrrupts on the Sandpoint come
 277  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
 278  * These interrupts are sent to one of four IRQs on the EPIC.
 279  * The SIO shares its interrupt with either slot 2 or slot 3 (INTA#).
 280  * Slot numbering is confusing.  Sometimes in the documentation they
 281  * use 0,1,2,3 and others 1,2,3,4.  We will use slots 1,2,3,4 and
 282  * map this to IRQ 16, 17, 18, 19.
 283  * For Sandpoint X3, this has been better designed.  The 8259 is
 284  * cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, IDE is on
 285  * EPIC 7 and 8.
 286  */
 287 static void __init
 288 sandpoint_init_IRQ(void)
 289 {
 290         int i;
 291
 292         /*
 293          * 3 things cause us to jump through some hoops:
 294          *   1) the EPIC on the 8240 & 107 are not full-blown openpic pic's
 295          *   2) the 8259 is NOT cascaded on the openpic IRQ 0
 296          *   3) the 8259 shares its interrupt line with some PCI interrupts.
 297          *
 298          * What we'll do is set up the 8259 to be level sensitive, active low
 299          * just like a PCI device.  Then, when an interrupt on the IRQ that is
 300          * shared with the 8259 comes in, we'll take a peek at the 8259 to see
 301          * it its generating an interrupt.  If it is, we'll handle the 8259
 302          * interrupt.  Otherwise, we'll handle it just like a normal PCI
 303          * interrupt.  This does give the 8259 interrupts a higher priority
 304          * than the EPIC ones--hopefully, not a problem.
 305          */
 306         OpenPIC_InitSenses = sandpoint_openpic_initsenses;
 307         OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
 308
 309         openpic_init(1, 0, NULL, -1);
 310
 311         /*
 312          * openpic_init() has set up irq_desc[0-23] to be openpic
 313          * interrupts.  We need to set irq_desc[0-15] to be 8259 interrupts.
 314          * We then need to request and enable the 8259 irq.
 315          */
 316         for(i=0; i < NUM_8259_INTERRUPTS; i++)
 317                 irq_desc[i].handler = &i8259_pic;
 318
 319         if (request_irq(SANDPOINT_SIO_IRQ, no_action, SA_INTERRUPT,
 320                         "8259 cascade to EPIC", NULL)) {
 321
 322                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 323                         SANDPOINT_SIO_IRQ);
 324         }
 325
 326         i8259_init(NULL);
 327 }
 328
 329 static int
 330 sandpoint_get_irq(struct pt_regs *regs)
 331 {
 332         int     irq, cascade_irq;
 333
 334         irq = openpic_irq();
 335
 336         if (irq == SANDPOINT_SIO_IRQ) {
 337                 cascade_irq = i8259_irq(regs);
 338
 339                 if (cascade_irq != -1) {
 340                         irq = cascade_irq;
 341                         openpic_eoi();
 342                 }
 343         }
 344         else if (irq == OPENPIC_VEC_SPURIOUS) {
 345                 irq = -1;
 346         }
 347
 348         return irq;
 349 }
 350
 351 static u32
 352 sandpoint_irq_canonicalize(u32 irq)
 353 {
 354         if (irq == 2)
 355         {
 356                 return 9;
 357         }
 358         else
 359         {
 360                 return irq;
 361         }
 362 }
 363
 364 static ulong __init
 365 sandpoint_find_end_of_memory(void)
 366 {
 367         ulong   size = 0;
 368
 369 #if 0   /* Leave out until DINK sets mem ctlr correctly */
 370         size = mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 371 #else
 372         size = 32*1024*1024;
 373 #endif
 374
 375         return size;
 376 }
 377
 378 static void __init
 379 sandpoint_map_io(void)
 380 {
 381         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 382 }
 383
 384 /*
 385  * Due to Sandpoint X2 errata, the Port 92 will not work.
 386  */
 387 static void
 388 sandpoint_restart(char *cmd)
 389 {
 390         local_irq_disable();
 391
 392         /* Set exception prefix high - to the firmware */
 393         _nmask_and_or_msr(0, MSR_IP);
 394
 395         /* Reset system via Port 92 */
 396         outb(0x00, 0x92);
 397         outb(0x01, 0x92);
 398         for(;;);        /* Spin until reset happens */
 399 }
 400
 401 static void
 402 sandpoint_power_off(void)
 403 {
 404         local_irq_disable();
 405         for(;;);  /* No way to shut power off with software */
 406         /* NOTREACHED */
 407 }
 408
 409 static void
 410 sandpoint_halt(void)
 411 {
 412         sandpoint_power_off();
 413         /* NOTREACHED */
 414 }
 415
 416 static int
 417 sandpoint_show_cpuinfo(struct seq_file *m)
 418 {
 419         uint pvid;
 420
 421         pvid = mfspr(PVR);
 422
 423         seq_printf(m, "vendor\t\t: Motorola SPS\n");
 424         seq_printf(m, "machine\t\t: Sandpoint\n");
 425         seq_printf(m, "processor\t: PVID: 0x%x, vendor: %s\n",
 426                         pvid, (pvid & (1<<15) ? "IBM" : "Motorola"));
 427
 428         return 0;
 429 }
 430
 431 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 432 /*
 433  * IDE support.
 434  */
 435 static int              sandpoint_ide_ports_known = 0;
 436 static unsigned long    sandpoint_ide_regbase[MAX_HWIFS];
 437 static unsigned long    sandpoint_ide_ctl_regbase[MAX_HWIFS];
 438 static unsigned long    sandpoint_idedma_regbase;
 439
 440 static void
 441 sandpoint_ide_probe(void)
 442 {
 443         struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
 444                                                PCI_DEVICE_ID_WINBOND_82C105,
 445                                                NULL);
 446
 447         if(pdev) {
 448                 sandpoint_ide_regbase[0]=pdev->resource[0].start;
 449                 sandpoint_ide_regbase[1]=pdev->resource[2].start;
 450                 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
 451                 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
 452                 sandpoint_idedma_regbase=pdev->resource[4].start;
 453         }
 454
 455         sandpoint_ide_ports_known = 1;
 456         return;
 457 }
 458
 459 static int
 460 sandpoint_ide_default_irq(unsigned long base)
 461 {
 462         if (sandpoint_ide_ports_known == 0)
 463                 sandpoint_ide_probe();
 464
 465         if (base == sandpoint_ide_regbase[0])
 466                 return SANDPOINT_IDE_INT0;
 467         else if (base == sandpoint_ide_regbase[1])
 468                 return SANDPOINT_IDE_INT1;
 469         else
 470                 return 0;
 471 }
 472
 473 static unsigned long
 474 sandpoint_ide_default_io_base(int index)
 475 {
 476         if (sandpoint_ide_ports_known == 0)
 477                 sandpoint_ide_probe();
 478
 479         return sandpoint_ide_regbase[index];
 480 }
 481
 482 static void __init
 483 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
 484                               unsigned long ctrl_port, int *irq)
 485 {
 486         unsigned long reg = data_port;
 487         uint    alt_status_base;
 488         int     i;
 489
 490         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 491                 hw->io_ports[i] = reg++;
 492         }
 493
 494         if (data_port == sandpoint_ide_regbase[0]) {
 495                 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
 496                 hw->irq = 14;
 497         }
 498         else if (data_port == sandpoint_ide_regbase[1]) {
 499                 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
 500                 hw->irq = 15;
 501         }
 502         else {
 503                 alt_status_base = 0;
 504                 hw->irq = 0;
 505         }
 506
 507         if (ctrl_port) {
 508                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 509         } else {
 510                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 511         }
 512
 513         if (irq != NULL) {
 514                 *irq = hw->irq;
 515         }
 516
 517         return;
 518 }
 519 #endif
 520
 521 /*
 522  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 523  */
 524 static __inline__ void
 525 sandpoint_set_bat(void)
 526 {
 527         unsigned long   bat3u, bat3l;
 528         static int      mapping_set = 0;
 529
 530         if (!mapping_set) {
 531
 532                 __asm__ __volatile__(
 533                 " lis %0,0xf800\n \
 534                   ori %1,%0,0x002a\n \
 535                   ori %0,%0,0x0ffe\n \
 536                   mtspr 0x21e,%0\n \
 537                   mtspr 0x21f,%1\n \
 538                   isync\n \
 539                   sync "
 540                   : "=r" (bat3u), "=r" (bat3l));
 541
 542                 mapping_set = 1;
 543         }
 544
 545         return;
 546 }
 547
 548 #ifdef  CONFIG_SERIAL_TEXT_DEBUG
 549 #include <linux/serialP.h>
 550 #include <linux/serial_reg.h>
 551 #include <asm/serial.h>
 552
 553 static struct serial_state rs_table[RS_TABLE_SIZE] = {
 554         SERIAL_PORT_DFNS        /* Defined in <asm/serial.h> */
 555 };
 556
 557 static void
 558 sandpoint_progress(char *s, unsigned short hex)
 559 {
 560         volatile char c;
 561         volatile unsigned long com_port;
 562         u16 shift;
 563
 564         com_port = rs_table[0].port;
 565         shift = rs_table[0].iomem_reg_shift;
 566
 567         while ((c = *s++) != 0) {
 568                 while ((*((volatile unsigned char *)com_port +
 569                                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
 570                                 ;
 571                 *(volatile unsigned char *)com_port = c;
 572
 573                 if (c == '\n') {
 574                         while ((*((volatile unsigned char *)com_port +
 575                                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
 576                                         ;
 577                         *(volatile unsigned char *)com_port = '\r';
 578                 }
 579         }
 580 }
 581 #endif  /* CONFIG_SERIAL_TEXT_DEBUG */
 582
 583 __init void sandpoint_setup_pci_ptrs(void);
 584
 585 TODC_ALLOC();
 586
 587 void __init
 588 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 589               unsigned long r6, unsigned long r7)
 590 {
 591         parse_bootinfo(find_bootinfo());
 592
 593         /* Map in board regs, etc. */
 594         sandpoint_set_bat();
 595
 596         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 597         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 598         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 599         ISA_DMA_THRESHOLD = 0x00ffffff;
 600         DMA_MODE_READ = 0x44;
 601         DMA_MODE_WRITE = 0x48;
 602
 603         ppc_md.setup_arch = sandpoint_setup_arch;
 604         ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
 605         ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
 606         ppc_md.init_IRQ = sandpoint_init_IRQ;
 607         ppc_md.get_irq = sandpoint_get_irq;
 608         ppc_md.init = sandpoint_init2;
 609
 610         ppc_md.restart = sandpoint_restart;
 611         ppc_md.power_off = sandpoint_power_off;
 612         ppc_md.halt = sandpoint_halt;
 613
 614         ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
 615         ppc_md.setup_io_mappings = sandpoint_map_io;
 616
 617         TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
 618         ppc_md.time_init = todc_time_init;
 619         ppc_md.set_rtc_time = todc_set_rtc_time;
 620         ppc_md.get_rtc_time = todc_get_rtc_time;
 621         ppc_md.calibrate_decr = todc_calibrate_decr;
 622
 623         ppc_md.nvram_read_val = todc_mc146818_read_val;
 624         ppc_md.nvram_write_val = todc_mc146818_write_val;
 625
 626         ppc_md.heartbeat = NULL;
 627         ppc_md.heartbeat_reset = 0;
 628         ppc_md.heartbeat_count = 0;
 629
 630 #ifdef  CONFIG_SERIAL_TEXT_DEBUG
 631         ppc_md.progress = sandpoint_progress;
 632 #else   /* !CONFIG_SERIAL_TEXT_DEBUG */
 633         ppc_md.progress = NULL;
 634 #endif  /* CONFIG_SERIAL_TEXT_DEBUG */
 635
 636 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 637         ppc_ide_md.default_irq = sandpoint_ide_default_irq;
 638         ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
 639         ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
 640 #endif
 641
 642         return;
 643 }