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Print more informations on bus error.
[linux-2.6/linux-mips.git] / arch / cris / drivers / sync_serial.c
blob59d62e01c731262470eb7c179c809ed45a10fdc2
1 /*
2 * Simple synchronous serial port driver for ETRAX 100LX.
3 *
4 * Synchronous serial ports are used for continous streamed data like audio.
5 * The default setting for this driver is compatible with the STA 013 MP3
6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders
7 * and SPI
8 *
9 * Copyright (c) 2001 Axis Communications AB
10 *
11 * Author: Mikael Starvik
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/major.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <asm/irq.h>
26 #include <asm/io.h>
27 #include <asm/svinto.h>
28 #include <asm/uaccess.h>
29 #include <asm/system.h>
30 #include <asm/sync_serial.h>
31
32 /* The receiver is a bit tricky beacuse of the continous stream of data. */
33 /* */
34 /* Two DMA descriptors are linked together. Each DMA descriptor is */
35 /* responsible for one half of a common buffer. */
36 /* */
37 /* ------------------------------ */
38 /* | ---------- ---------- | */
39 /* --> | Descr1 |-->| Descr2 |--- */
40 /* ---------- ---------- */
41 /* | | */
42 /* v v */
43 /* ----------------------------- */
44 /* | BUFFER | */
45 /* ----------------------------- */
46 /* | | */
47 /* readp writep */
48 /* */
49 /* If the application keeps up the pace readp will be right after writep.*/
50 /* If the application can't keep the pace we have to throw away data. */
51 /* The idea is that readp should be ready with the data pointed out by */
52 /* Descr1 when the DMA has filled in Descr2. Otherwise we will discard */
53 /* the rest of the data pointed out by Descr1 and set readp to the start */
54 /* of Descr2 */
55
56 #define SYNC_SERIAL_MAJOR 125
57
58 /* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
59 /* words can be handled */
60
61 #define IN_BUFFER_SIZE 12288
62 #define OUT_BUFFER_SIZE 4096
63
64 #define DEFAULT_FRAME_RATE 0
65 #define DEFAULT_WORD_RATE 7
66
67 #define DEBUG(x)
68
69 /* Define some macros to access ETRAX 100 registers */
70 #define SETF(var, reg, field, val) var = (var & ~IO_MASK(##reg##, field)) | \
71 IO_FIELD(##reg##, field, val)
72 #define SETS(var, reg, field, val) var = (var & ~IO_MASK(##reg##, field)) | \
73 IO_STATE(##reg##, field, val)
74
75 typedef struct sync_port
76 {
77 /* Etrax registers and bits*/
78 volatile unsigned * const status;
79 volatile unsigned * const ctrl_data;
80 volatile unsigned * const output_dma_first;
81 volatile unsigned char * const output_dma_cmd;
82 volatile unsigned char * const output_dma_clr_irq;
83 volatile unsigned * const input_dma_first;
84 volatile unsigned char * const input_dma_cmd;
85 volatile unsigned char * const input_dma_clr_irq;
86 volatile unsigned * const data_out;
87 volatile unsigned * const data_in;
88 char data_avail_bit; /* In R_IRQ_MASK1_RD */
89 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD */
90 char ready_irq_bit; /* In R_IRQ_MASK1_SET and R_IRQ_MASK1_CLR */
91 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
92 char output_dma_bit; /* In R_IRQ_MASK2_RD */
93
94 int enabled; /* 1 if port is enabled */
95 int use_dma; /* 1 if port uses dma */
96 int port_nbr; /* Port 0 or 1 */
97 unsigned ctrl_data_shadow; /* Register shadow */
98 char busy; /* 1 if port is busy */
99 wait_queue_head_t out_wait_q;
100 wait_queue_head_t in_wait_q;
101 struct etrax_dma_descr out_descr;
102 struct etrax_dma_descr in_descr1;
103 struct etrax_dma_descr in_descr2;
104 char out_buffer[OUT_BUFFER_SIZE];
105 int out_count; /* Remaining bytes for current transfer */
106 char* outp; /* Current position in out_buffer */
107 char in_buffer[IN_BUFFER_SIZE];
108 volatile char* readp; /* Next byte to be read by application */
109 volatile char* writep; /* Next byte to be written by etrax */
110 int odd_output; /* 1 if writing odd nible in 12 bit mode */
111 int odd_input; /* 1 if reading odd nible in 12 bit mode */
112 } sync_port;
113
114
115 static int etrax_sync_serial_init(void);
116 static void initialize_port(int portnbr);
117 static int sync_serial_open(struct inode *, struct file*);
118 static int sync_serial_release(struct inode*, struct file*);
119 static int sync_serial_ioctl(struct inode*, struct file*,
120 unsigned int cmd, unsigned long arg);
121 static ssize_t sync_serial_write(struct file * file, const char * buf,
122 size_t count, loff_t *ppos);
123 static ssize_t sync_serial_manual_write(struct file * file, const char * buf,
124 size_t count, loff_t *ppos);
125 static ssize_t sync_serial_read(struct file *file, char *buf,
126 size_t count, loff_t *ppos);
127 static void send_word(sync_port* port);
128 static void start_dma(struct sync_port *port, const char* data, int count);
129 static void start_dma_in(sync_port* port);
130 static void tr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
131 static void rx_interrupt(int irq, void *dev_id, struct pt_regs * regs);
132 static void manual_interrupt(int irq, void *dev_id, struct pt_regs * regs);
133
134 /* The ports */
135 static struct sync_port ports[]=
136 {
137 {
138 R_SYNC_SERIAL1_STATUS, /* status */
139 R_SYNC_SERIAL1_CTRL, /* ctrl_data */
140 R_DMA_CH8_FIRST, /* output_dma_first */
141 R_DMA_CH8_CMD, /* output_dma_cmd */
142 R_DMA_CH8_CLR_INTR, /* output_dma_clr_irq */
143 R_DMA_CH9_FIRST, /* input_dma_first */
144 R_DMA_CH9_CMD, /* input_dma_cmd */
145 R_DMA_CH9_CLR_INTR, /* input_dma_clr_irq */
146 R_SYNC_SERIAL1_TR_DATA, /* data_out */
147 R_SYNC_SERIAL1_REC_DATA,/* data in */
148 IO_BITNR(R_IRQ_MASK1_RD, ser1_data), /* data_avail_bit */
149 IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), /* transmitter_ready_bit */
150 IO_BITNR(R_IRQ_MASK1_SET, ser1_ready), /* ready_irq_bit */
151 IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), /* input_dma_descr_bit */
152 IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), /* output_dma_bit */
153 },
154 {
155 R_SYNC_SERIAL3_STATUS, /* status */
156 R_SYNC_SERIAL3_CTRL, /* ctrl_data */
157 R_DMA_CH4_FIRST, /* output_dma_first */
158 R_DMA_CH4_CMD, /* output_dma_cmd */
159 R_DMA_CH4_CLR_INTR, /* output_dma_clr_irq */
160 R_DMA_CH5_FIRST, /* input_dma_first */
161 R_DMA_CH5_CMD, /* input_dma_cmd */
162 R_DMA_CH5_CLR_INTR, /* input_dma_clr_irq */
163 R_SYNC_SERIAL3_TR_DATA, /* data_out */
164 R_SYNC_SERIAL3_REC_DATA,/* data in */
165 IO_BITNR(R_IRQ_MASK1_RD, ser3_data), /* data_avail_bit */
166 IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), /* transmitter_ready_bit */
167 IO_BITNR(R_IRQ_MASK1_SET, ser3_ready), /* ready_irq_bit */
168 IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), /* input_dma_descr_bit */
169 IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), /* output_dma_bit */
170 }
171 };
172
173 /* Register shadows */
174 static unsigned sync_serial_prescale_shadow = 0;
175 static unsigned gen_config_ii_shadow = 0;
176
177 #define NUMBER_OF_PORTS (sizeof(ports)/sizeof(sync_port))
178
179 static struct file_operations sync_serial_fops = {
180 .owner = THIS_MODULE,
181 .write = sync_serial_write,
182 .read = sync_serial_read,
183 .ioctl = sync_serial_ioctl,
184 .open = sync_serial_open,
185 .release = sync_serial_release
186 };
187
188 static int __init etrax_sync_serial_init(void)
189 {
190 ports[0].enabled = 0;
191 ports[1].enabled = 0;
192
193 if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 )
194 {
195 printk("unable to get major for synchronous serial port\n");
196 return -EBUSY;
197 }
198
199 /* Deselect synchronous serial ports */
200 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
201 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
202 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, ser3, select);
203 *R_GEN_CONFIG_II = gen_config_ii_shadow;
204
205 /* Initialize Ports */
206 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
207 ports[0].enabled = 1;
208 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
209 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
210 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
211 ports[0].use_dma = 1;
212 initialize_port(0);
213 if(request_irq(24, tr_interrupt, 0, "synchronous serial 1 dma tr", &ports[0]))
214 panic("Can't allocate sync serial port 1 IRQ");
215 if(request_irq(25, rx_interrupt, 0, "synchronous serial 1 dma rx", &ports[0]))
216 panic("Can't allocate sync serial port 1 IRQ");
217 RESET_DMA(8); WAIT_DMA(8);
218 RESET_DMA(9); WAIT_DMA(9);
219 *R_DMA_CH8_CLR_INTR = IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
220 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
221 *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do) |
222 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, do);
223 *R_IRQ_MASK2_SET =
224 IO_STATE(R_IRQ_MASK2_SET, dma8_eop, set) |
225 IO_STATE(R_IRQ_MASK2_SET, dma8_descr, set) |
226 IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set);
227 start_dma_in(&ports[0]);
228 #else
229 ports[0].use_dma = 0;
230 initialize_port(0);
231 if (request_irq(8, manual_interrupt, SA_SHIRQ, "synchronous serial manual irq", &ports[0]))
232 panic("Can't allocate sync serial manual irq");
233 *R_IRQ_MASK1_SET = IO_STATE(R_IRQ_MASK1_SET, ser1_data, set);
234 #endif
235 #endif
236
237 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
238 ports[1].enabled = 1;
239 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
240 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
241 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
242 ports[1].use_dma = 1;
243 initialize_port(1);
244 if(request_irq(20, tr_interrupt, 0, "synchronous serial 3 dma tr", &ports[1]))
245 panic("Can't allocate sync serial port 1 IRQ");
246 if(request_irq(21, rx_interrupt, 0, "synchronous serial 3 dma rx", &ports[1]))
247 panic("Can't allocate sync serial port 1 IRQ");
248 RESET_DMA(4); WAIT_DMA(4);
249 RESET_DMA(5); WAIT_DMA(5);
250 *R_DMA_CH4_CLR_INTR = IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
251 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
252 *R_DMA_CH5_CLR_INTR = IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, do) |
253 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, do);
254 *R_IRQ_MASK2_SET =
255 IO_STATE(R_IRQ_MASK2_SET, dma4_eop, set) |
256 IO_STATE(R_IRQ_MASK2_SET, dma4_descr, set) |
257 IO_STATE(R_IRQ_MASK2_SET, dma5_descr, set);
258 start_dma_in(&ports[1]);
259 #else
260 ports[1].use_dma = 0;
261 initialize_port(1);
262 if (port[0].use_dma) /* Port 0 uses dma, we must manual allocate IRQ */
263 {
264 if (request_irq(8, manual_interrupt, SA_SHIRQ, "synchronous serial manual irq", &ports[1]))
265 panic("Can't allocate sync serial manual irq");
266 }
267 *R_IRQ_MASK1_SET = IO_STATE(R_IRQ_MASK1_SET, ser3_data, set);
268 #endif
269 #endif
270
271 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
272
273 /* Set up timing */
274 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
275 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
276 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
277 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
278 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
279 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
280 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, DEFAULT_FRAME_RATE) |
281 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
282 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
283
284 /* Select synchronous ports */
285 *R_GEN_CONFIG_II = gen_config_ii_shadow;
286
287 printk("ETRAX 100LX synchronous serial port driver\n");
288 return 0;
289 }
290
291 static void initialize_port(int portnbr)
292 {
293 struct sync_port* port = &ports[portnbr];
294
295 DEBUG(printk("Init sync serial port %d\n", portnbr));
296
297 port->port_nbr = portnbr;
298 port->busy = 0;
299 port->readp = port->in_buffer;
300 port->writep = port->in_buffer + IN_BUFFER_SIZE/2;
301 port->odd_input = 0;
302
303 init_waitqueue_head(&port->out_wait_q);
304 init_waitqueue_head(&port->in_wait_q);
305
306 port->ctrl_data_shadow =
307 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
308 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
309 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
310 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
311 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
312 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
313 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
314 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
315 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
316 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
317 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
318 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
319 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
320 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
321 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
322 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
323 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
324 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
325 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
326 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
327 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
328 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
329
330 if (port->use_dma)
331 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, dma_enable, on);
332 else
333 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, dma_enable, off);
334
335 *port->ctrl_data = port->ctrl_data_shadow;
336 }
337
338 static int sync_serial_open(struct inode *inode, struct file *file)
339 {
340 int dev = MINOR(inode->i_rdev);
341 DEBUG(printk("Open sync serial port %d\n", dev));
342
343 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
344 {
345 DEBUG(printk("Invalid minor %d\n", dev));
346 return -ENODEV;
347 }
348 if (ports[dev].busy)
349 {
350 DEBUG(printk("Device is busy.. \n"));
351 return -EBUSY;
352 }
353 ports[dev].busy = 1;
354 return 0;
355 }
356
357 static int sync_serial_release(struct inode *inode, struct file *file)
358 {
359 int dev = MINOR(inode->i_rdev);
360 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
361 {
362 DEBUG(printk("Invalid minor %d\n", dev));
363 return -ENODEV;
364 }
365 ports[dev].busy = 0;
366 return 0;
367 }
368
369 static int sync_serial_ioctl(struct inode *inode, struct file *file,
370 unsigned int cmd, unsigned long arg)
371 {
372 int return_val = 0;
373 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
374 sync_port* port;
375
376 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
377 {
378 DEBUG(printk("Invalid minor %d\n", dev));
379 return -1;
380 }
381 port = &ports[dev];
382
383 /* Disable port while changing config */
384 if (dev)
385 {
386 RESET_DMA(4); WAIT_DMA(4);
387 *R_DMA_CH4_CLR_INTR = IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
388 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
389 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
390 }
391 else
392 {
393 RESET_DMA(8); WAIT_DMA(8);
394 *R_DMA_CH8_CLR_INTR = IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
395 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
396 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
397 }
398 *R_GEN_CONFIG_II = gen_config_ii_shadow;
399
400 switch(cmd)
401 {
402 case SSP_SPEED:
403 if (GET_SPEED(arg) == CODEC)
404 {
405 if (dev)
406 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec);
407 else
408 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec);
409
410 SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, prescaler, GET_FREQ(arg));
411 SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, frame_rate, GET_FRAME_RATE(arg));
412 SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, word_rate, GET_WORD_RATE(arg));
413 }
414 else
415 {
416 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_baud, GET_SPEED(arg));
417 if (dev)
418 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u3, baudrate);
419 else
420 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u1, baudrate);
421 }
422 break;
423 case SSP_MODE:
424 if (arg > 5)
425 return -EINVAL;
426 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
427 break;
428 case SSP_FRAME_SYNC:
429 if (arg & NORMAL_SYNC)
430 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, normal);
431 else if (arg & EARLY_SYNC)
432 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, early);
433
434 if (arg & BIT_SYNC)
435 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, bit);
436 else if (arg & WORD_SYNC)
437 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, word);
438 else if (arg & EXTENDED_SYNC)
439 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, extended);
440
441 if (arg & SYNC_ON)
442 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
443 else if (arg & SYNC_OFF)
444 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, off);
445
446 if (arg & WORD_SIZE_8)
447 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size8bit);
448 else if (arg & WORD_SIZE_12)
449 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size12bit);
450 else if (arg & WORD_SIZE_16)
451 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size16bit);
452 else if (arg & WORD_SIZE_24)
453 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size24bit);
454 else if (arg & WORD_SIZE_32)
455 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size32bit);
456
457 if (arg & BIT_ORDER_MSB)
458 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, msb);
459 else if (arg & BIT_ORDER_LSB)
460 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, lsb);
461
462 if (arg & FLOW_CONTROL_ENABLE)
463 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled);
464 else if (arg & FLOW_CONTROL_DISABLE)
465 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, disabled);
466
467 if (arg & CLOCK_NOT_GATED)
468 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_mode, normal);
469 else if (arg & CLOCK_GATED)
470 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_mode, gated);
471
472 break;
473 case SSP_IPOLARITY:
474 if (arg & CLOCK_NORMAL)
475 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, neg);
476 else if (arg & CLOCK_INVERT)
477 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, pos);
478
479 if (arg & FRAME_NORMAL)
480 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, normal);
481 else if (arg & FRAME_INVERT)
482 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, inverted);
483
484 if (arg & STATUS_NORMAL)
485 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_polarity, normal);
486 else if (arg & STATUS_INVERT)
487 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_polarity, inverted);
488 break;
489 case SSP_OPOLARITY:
490 if (arg & CLOCK_NORMAL)
491 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, normal);
492 else if (arg & CLOCK_INVERT)
493 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, inverted);
494
495 if (arg & FRAME_NORMAL)
496 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, normal);
497 else if (arg & FRAME_INVERT)
498 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, inverted);
499
500 if (arg & STATUS_NORMAL)
501 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_driver, normal);
502 else if (arg & STATUS_INVERT)
503 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_driver, inverted);
504 break;
505 case SSP_SPI:
506 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, disabled);
507 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, msb);
508 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size8bit);
509 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
510 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, word);
511 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, normal);
512 if (arg & SPI_SLAVE)
513 {
514 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, inverted);
515 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, neg);
516 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, SLAVE_INPUT);
517 }
518 else
519 {
520 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, inverted);
521 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, inverted);
522 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, MASTER_OUTPUT);
523 }
524 break;
525 default:
526 return_val = -1;
527 }
528 /* Set config and enable port */
529 *port->ctrl_data = port->ctrl_data_shadow;
530 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
531 if (dev)
532 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
533 else
534 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
535
536 *R_GEN_CONFIG_II = gen_config_ii_shadow;
537 return return_val;
538 }
539
540 static ssize_t sync_serial_manual_write(struct file * file, const char * buf,
541 size_t count, loff_t *ppos)
542 {
543 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
544 DECLARE_WAITQUEUE(wait, current);
545 sync_port* port;
546
547 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
548 {
549 DEBUG(printk("Invalid minor %d\n", dev));
550 return -ENODEV;
551 }
552
553 port = &ports[dev];
554 if (copy_from_user(port->out_buffer, buf, count))
555 return -EFAULT;
556 port->outp = port->out_buffer;
557 port->out_count = count;
558 port->odd_output = 1;
559 add_wait_queue(&port->out_wait_q, &wait);
560 set_current_state(TASK_INTERRUPTIBLE);
561 *R_IRQ_MASK1_SET = 1 << port->ready_irq_bit; /* transmitter ready IRQ on */
562 send_word(port); /* Start sender by sending first word */
563 schedule();
564 set_current_state(TASK_RUNNING);
565 remove_wait_queue(&port->out_wait_q, &wait);
566 if (signal_pending(current))
567 {
568 return -EINTR;
569 }
570 return count;
571 }
572
573 static ssize_t sync_serial_write(struct file * file, const char * buf,
574 size_t count, loff_t *ppos)
575 {
576 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
577 DECLARE_WAITQUEUE(wait, current);
578 sync_port *port;
579
580 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
581 {
582 DEBUG(printk("Invalid minor %d\n", dev));
583 return -ENODEV;
584 }
585 port = &ports[dev];
586
587 DEBUG(printk("Write dev %d count %d\n", port->port_nbr, count));
588
589 count = count > OUT_BUFFER_SIZE ? OUT_BUFFER_SIZE : count;
590
591 /* Make sure transmitter is running */
592 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, running);
593 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, enable);
594 *port->ctrl_data = port->ctrl_data_shadow;
595
596 if (!port->use_dma)
597 {
598 return sync_serial_manual_write(file, buf, count, ppos);
599 }
600
601 if (copy_from_user(port->out_buffer, buf, count))
602 return -EFAULT;
603 add_wait_queue(&port->out_wait_q, &wait);
604 set_current_state(TASK_INTERRUPTIBLE);
605 start_dma(port, buf, count);
606 schedule();
607 set_current_state(TASK_RUNNING);
608 remove_wait_queue(&port->out_wait_q, &wait);
609 if (signal_pending(current))
610 {
611 return -EINTR;
612 }
613 return count;
614 }
615
616 static ssize_t sync_serial_read(struct file * file, char * buf,
617 size_t count, loff_t *ppos)
618 {
619 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
620 int avail;
621 sync_port *port;
622 char* start;
623 char* end;
624 unsigned long flags;
625
626 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
627 {
628 DEBUG(printk("Invalid minor %d\n", dev));
629 return -ENODEV;
630 }
631 port = &ports[dev];
632
633 DEBUG(printk("Read dev %d count %d\n", dev, count));
634
635 /* Make sure receiver is running */
636 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, running);
637 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, enable);
638 *port->ctrl_data = port->ctrl_data_shadow;
639
640 /* Calculate number of available bytes */
641 while (port->readp == port->writep) /* No data */
642 {
643 if (file->f_flags & O_NONBLOCK)
644 return -EAGAIN;
645 interruptible_sleep_on(&port->in_wait_q);
646 if (signal_pending(current))
647 {
648 return -EINTR;
649 }
650 }
651
652 /* Save pointers to avoid that they are modified by interrupt */
653 start = port->readp;
654 end = port->writep;
655
656 /* Lazy read, never return wrapped data. */
657 if (end > start)
658 avail = end - start;
659 else
660 avail = port->in_buffer + IN_BUFFER_SIZE - start;
661
662 count = count > avail ? avail : count;
663 if (copy_to_user(buf, start, count))
664 return -EFAULT;
665
666 /* Disable interrupts while updating readp */
667 save_flags(flags);
668 cli();
669 port->readp += count;
670 if (port->readp == port->in_buffer + IN_BUFFER_SIZE) /* Wrap? */
671 port->readp = port->in_buffer;
672 restore_flags(flags);
673
674 DEBUG(printk("%d bytes read\n", count));
675 return count;
676 }
677
678 static void send_word(sync_port* port)
679 {
680 switch(port->ctrl_data_shadow & IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize))
681 {
682 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
683 port->out_count--;
684 *port->data_out = *port->outp++;
685 break;
686 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
687 port->out_count--;
688 if (port->odd_output)
689 *port->data_out = ((*port->outp) << 16) | (*(unsigned short *)(port->outp + 1));
690 else
691 *port->data_out = ((*(unsigned short *)port->outp) << 8) | (*(port->outp + 1));
692 port->odd_output = !port->odd_output;
693 port->outp++;
694 break;
695 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
696 port->out_count-=2;
697 *port->data_out = *(unsigned short *)port->outp;
698 port->outp+=2;
699 break;
700 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
701 port->out_count-=3;
702 *port->data_out = *(unsigned int *)port->outp;
703 port->outp+=3;
704 break;
705 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
706 port->out_count-=4;
707 *port->data_out = *(unsigned int *)port->outp;
708 port->outp+=4;
709 break;
710 }
711 }
712
713 static void start_dma(struct sync_port* port, const char* data, int count)
714 {
715 port->out_descr.hw_len = 0;
716 port->out_descr.next = 0;
717 port->out_descr.ctrl = d_int | d_eol | d_eop | d_wait;
718 port->out_descr.sw_len = count;
719 port->out_descr.buf = virt_to_phys(port->out_buffer);
720 port->out_descr.status = 0;
721
722 *port->output_dma_first = virt_to_phys(&port->out_descr);
723 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
724 }
725
726 static void start_dma_in(sync_port* port)
727 {
728 if (port->writep > port->in_buffer + IN_BUFFER_SIZE)
729 {
730 panic("Offset too large in sync serial driver\n");
731 return;
732 }
733 port->in_descr1.hw_len = 0;
734 port->in_descr1.ctrl = d_int;
735 port->in_descr1.status = 0;
736 port->in_descr1.next = virt_to_phys(&port->in_descr2);
737 port->in_descr2.hw_len = 0;
738 port->in_descr2.next = virt_to_phys(&port->in_descr1);
739 port->in_descr2.ctrl = d_int;
740 port->in_descr2.status = 0;
741
742 /* Find out which descriptor to start */
743 if (port->writep >= port->in_buffer + IN_BUFFER_SIZE/2)
744 {
745 /* Start descriptor 2 */
746 port->in_descr1.sw_len = IN_BUFFER_SIZE/2; /* All data available in 1 */
747 port->in_descr1.buf = virt_to_phys(port->in_buffer);
748 port->in_descr2.sw_len = port->in_buffer + IN_BUFFER_SIZE - port->writep;
749 port->in_descr2.buf = virt_to_phys(port->writep);
750 *port->input_dma_first = virt_to_phys(&port->in_descr2);
751 }
752 else
753 {
754 /* Start descriptor 1 */
755 port->in_descr1.sw_len = port->in_buffer + IN_BUFFER_SIZE/2 - port->writep;
756 port->in_descr1.buf = virt_to_phys(port->writep);
757 port->in_descr2.sw_len = IN_BUFFER_SIZE/2;
758 port->in_descr2.buf = virt_to_phys(port->in_buffer + IN_BUFFER_SIZE / 2);
759 *port->input_dma_first = virt_to_phys(&port->in_descr1);
760 }
761 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
762 }
763
764 static void tr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
765 {
766 unsigned long ireg = *R_IRQ_MASK2_RD;
767 int i;
768
769 for (i = 0; i < NUMBER_OF_PORTS; i++)
770 {
771 sync_port *port = &ports[i];
772 if (ireg & (1 << port->output_dma_bit)) /* IRQ active for the port? */
773 {
774 /* Clear IRQ */
775 *port->output_dma_clr_irq =
776 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
777 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
778 wake_up_interruptible(&port->out_wait_q); /* wake up the waiting process */
779 }
780 }
781 }
782
783 static void rx_interrupt(int irq, void *dev_id, struct pt_regs * regs)
784 {
785 unsigned long ireg = *R_IRQ_MASK2_RD;
786 int i;
787
788 for (i = 0; i < NUMBER_OF_PORTS; i++)
789 {
790 int update = 0;
791 sync_port *port = &ports[i];
792
793 if (!port->enabled)
794 {
795 continue;
796 }
797
798 if (ireg & (1 << port->input_dma_descr_bit)) /* Descriptor interrupt */
799 {
800 /* DMA has reached end of descriptor */
801 *port->input_dma_clr_irq =
802 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
803 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
804
805 /* Find out which descriptor that is ready */
806 if (port->writep >= port->in_buffer + IN_BUFFER_SIZE/2)
807 {
808 /* Descr 2 was ready. Restart DMA at descriptor 1 */
809 port->writep = port->in_buffer;
810
811 /* Throw away data? */
812 if (port->readp < port->in_buffer + IN_BUFFER_SIZE/2)
813 port->readp = port->in_buffer + IN_BUFFER_SIZE/2;
814 }
815 else
816 {
817 /* Descr 1 was ready. Restart DMA at descriptor 2 */
818 port->writep = port->in_buffer + IN_BUFFER_SIZE/2;
819
820 /* Throw away data? */
821 if (port->readp >= port->in_buffer + IN_BUFFER_SIZE/2)
822 port->readp = port->in_buffer;
823 }
824 start_dma_in(port);
825 wake_up_interruptible(&port->in_wait_q); /* wake up the waiting process */
826 }
827 }
828 }
829
830 static void manual_interrupt(int irq, void *dev_id, struct pt_regs * regs)
831 {
832 int i;
833
834 for (i = 0; i < NUMBER_OF_PORTS; i++)
835 {
836 sync_port* port = &ports[i];
837
838 if (!port->enabled)
839 {
840 continue;
841 }
842
843 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) /* Data received? */
844 {
845 /* Read data */
846 switch(port->ctrl_data_shadow & IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize))
847 {
848 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
849 *port->writep++ = *(volatile char *)port->data_in;
850 break;
851 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
852 {
853 int data = *(unsigned short *)port->data_in;
854 if (port->odd_input)
855 {
856 *port->writep |= (data & 0x0f00) >> 8;
857 *(port->writep + 1) = data & 0xff;
858 }
859 else
860 {
861 *port->writep = (data & 0x0ff0) >> 4;
862 *(port->writep + 1) = (data & 0x0f) << 4;
863 }
864 port->odd_input = !port->odd_input;
865 port->writep+=1;
866 }
867 break;
868 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
869 *(unsigned short*)port->writep = *(volatile unsigned short *)port->data_in;
870 port->writep+=2;
871 break;
872 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
873 *(unsigned int*)port->writep = *port->data_in;
874 port->writep+=3;
875 break;
876 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
877 *(unsigned int*)port->writep = *port->data_in;
878 port->writep+=4;
879 break;
880 }
881
882 if (port->writep > port->in_buffer + IN_BUFFER_SIZE) /* Wrap? */
883 port->writep = port->in_buffer;
884 wake_up_interruptible(&port->in_wait_q); /* Wake up application */
885 }
886
887 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) /* Transmitter ready? */
888 {
889 if (port->out_count) /* More data to send */
890 send_word(port);
891 else /* transmission finished */
892 {
893 *R_IRQ_MASK1_CLR = 1 << port->ready_irq_bit; /* Turn off IRQ */
894 wake_up_interruptible(&port->out_wait_q); /* Wake up application */
895 }
896 }
897 }
898 }
899
900 module_init(etrax_sync_serial_init);
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