2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
20 * 2004/03/24 LH7A404 support (Durgesh Pattamatta & Marc Singer)
21 * 2004/02/04 use generic dma_* functions instead of pci_* (dsaxena@plexity.net)
22 * 2003/02/24 show registers in sysfs (Kevin Brosius)
24 * 2002/09/03 get rid of ed hashtables, rework periodic scheduling and
25 * bandwidth accounting; if debugging, show schedules in driverfs
26 * 2002/07/19 fixes to management of ED and schedule state.
27 * 2002/06/09 SA-1111 support (Christopher Hoover)
28 * 2002/06/01 remember frame when HC won't see EDs any more; use that info
29 * to fix urb unlink races caused by interrupt latency assumptions;
30 * minor ED field and function naming updates
31 * 2002/01/18 package as a patch for 2.5.3; this should match the
32 * 2.4.17 kernel modulo some bugs being fixed.
34 * 2001/10/18 merge pmac cleanup (Benjamin Herrenschmidt) and bugfixes
35 * from post-2.4.5 patches.
36 * 2001/09/20 URB_ZERO_PACKET support; hcca_dma portability, OPTi warning
37 * 2001/09/07 match PCI PM changes, errnos from Linus' tree
38 * 2001/05/05 fork 2.4.5 version into "hcd" framework, cleanup, simplify;
39 * pbook pci quirks gone (please fix pbook pci sw!) (db)
41 * 2001/04/08 Identify version on module load (gb)
42 * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam);
44 * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db)
45 * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam)
47 * 2000/09/26 fixed races in removing the private portion of the urb
48 * 2000/09/07 disable bulk and control lists when unlinking the last
49 * endpoint descriptor in order to avoid unrecoverable errors on
50 * the Lucent chips. (rwc@sgi)
51 * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some
52 * urb unlink probs, indentation fixes
53 * 2000/08/11 various oops fixes mostly affecting iso and cleanup from
55 * 2000/06/28 use PCI hotplug framework, for better power management
56 * and for Cardbus support (David Brownell)
57 * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling
58 * when the controller loses power; handle UE; cleanup; ...
60 * v5.2 1999/12/07 URB 3rd preview,
61 * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi)
62 * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume
63 * i386: HUB, Keyboard, Mouse, Printer
65 * v4.3 1999/10/27 multiple HCs, bulk_request
66 * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes
67 * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl.
70 * v2.1 1999/05/09 code clean up
72 * v1.0 1999/04/27 initial release
74 * This file is licenced under the GPL.
77 #include <linux/module.h>
78 #include <linux/moduleparam.h>
79 #include <linux/pci.h>
80 #include <linux/kernel.h>
81 #include <linux/delay.h>
82 #include <linux/ioport.h>
83 #include <linux/sched.h>
84 #include <linux/slab.h>
85 #include <linux/smp_lock.h>
86 #include <linux/errno.h>
87 #include <linux/init.h>
88 #include <linux/timer.h>
89 #include <linux/list.h>
90 #include <linux/usb.h>
91 #include <linux/usb/otg.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/dmapool.h>
94 #include <linux/reboot.h>
98 #include <asm/system.h>
99 #include <asm/unaligned.h>
100 #include <asm/byteorder.h>
102 #include "../core/hcd.h"
104 #define DRIVER_VERSION "2006 August 04"
105 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
106 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
108 /*-------------------------------------------------------------------------*/
110 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
112 /* For initializing controller (mask in an HCFS mode too) */
113 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
114 #define OHCI_INTR_INIT \
115 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
116 | OHCI_INTR_RD | OHCI_INTR_WDH)
119 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
123 #ifdef CONFIG_ARCH_OMAP
124 /* OMAP doesn't support IR (no SMM; not needed) */
128 /*-------------------------------------------------------------------------*/
130 static const char hcd_name
[] = "ohci_hcd";
132 #define STATECHANGE_DELAY msecs_to_jiffies(300)
136 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
137 static int ohci_init (struct ohci_hcd
*ohci
);
138 static void ohci_stop (struct usb_hcd
*hcd
);
140 #include "ohci-hub.c"
141 #include "ohci-dbg.c"
142 #include "ohci-mem.c"
147 * On architectures with edge-triggered interrupts we must never return
150 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
151 #define IRQ_NOTMINE IRQ_HANDLED
153 #define IRQ_NOTMINE IRQ_NONE
157 /* Some boards misreport power switching/overcurrent */
158 static int distrust_firmware
= 1;
159 module_param (distrust_firmware
, bool, 0);
160 MODULE_PARM_DESC (distrust_firmware
,
161 "true to distrust firmware power/overcurrent setup");
163 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
164 static int no_handshake
= 0;
165 module_param (no_handshake
, bool, 0);
166 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
168 /*-------------------------------------------------------------------------*/
171 * queue up an urb for anything except the root hub
173 static int ohci_urb_enqueue (
175 struct usb_host_endpoint
*ep
,
179 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
181 urb_priv_t
*urb_priv
;
182 unsigned int pipe
= urb
->pipe
;
187 #ifdef OHCI_VERBOSE_DEBUG
188 urb_print (urb
, "SUB", usb_pipein (pipe
));
191 /* every endpoint has a ed, locate and maybe (re)initialize it */
192 if (! (ed
= ed_get (ohci
, ep
, urb
->dev
, pipe
, urb
->interval
)))
195 /* for the private part of the URB we need the number of TDs (size) */
198 /* td_submit_urb() doesn't yet handle these */
199 if (urb
->transfer_buffer_length
> 4096)
202 /* 1 TD for setup, 1 for ACK, plus ... */
205 // case PIPE_INTERRUPT:
208 /* one TD for every 4096 Bytes (can be upto 8K) */
209 size
+= urb
->transfer_buffer_length
/ 4096;
210 /* ... and for any remaining bytes ... */
211 if ((urb
->transfer_buffer_length
% 4096) != 0)
213 /* ... and maybe a zero length packet to wrap it up */
216 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
217 && (urb
->transfer_buffer_length
218 % usb_maxpacket (urb
->dev
, pipe
,
219 usb_pipeout (pipe
))) == 0)
222 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
223 size
= urb
->number_of_packets
;
227 /* allocate the private part of the URB */
228 urb_priv
= kmalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
232 memset (urb_priv
, 0, sizeof (urb_priv_t
) + size
* sizeof (struct td
*));
233 INIT_LIST_HEAD (&urb_priv
->pending
);
234 urb_priv
->length
= size
;
237 /* allocate the TDs (deferring hash chain updates) */
238 for (i
= 0; i
< size
; i
++) {
239 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
240 if (!urb_priv
->td
[i
]) {
241 urb_priv
->length
= i
;
242 urb_free_priv (ohci
, urb_priv
);
247 spin_lock_irqsave (&ohci
->lock
, flags
);
249 /* don't submit to a dead HC */
250 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
)) {
254 if (!HC_IS_RUNNING(hcd
->state
)) {
259 /* in case of unlink-during-submit */
260 spin_lock (&urb
->lock
);
261 if (urb
->status
!= -EINPROGRESS
) {
262 spin_unlock (&urb
->lock
);
263 urb
->hcpriv
= urb_priv
;
264 finish_urb (ohci
, urb
);
269 /* schedule the ed if needed */
270 if (ed
->state
== ED_IDLE
) {
271 retval
= ed_schedule (ohci
, ed
);
274 if (ed
->type
== PIPE_ISOCHRONOUS
) {
275 u16 frame
= ohci_frame_no(ohci
);
277 /* delay a few frames before the first TD */
278 frame
+= max_t (u16
, 8, ed
->interval
);
279 frame
&= ~(ed
->interval
- 1);
281 urb
->start_frame
= frame
;
283 /* yes, only URB_ISO_ASAP is supported, and
284 * urb->start_frame is never used as input.
287 } else if (ed
->type
== PIPE_ISOCHRONOUS
)
288 urb
->start_frame
= ed
->last_iso
+ ed
->interval
;
290 /* fill the TDs and link them to the ed; and
291 * enable that part of the schedule, if needed
292 * and update count of queued periodic urbs
294 urb
->hcpriv
= urb_priv
;
295 td_submit_urb (ohci
, urb
);
298 spin_unlock (&urb
->lock
);
301 urb_free_priv (ohci
, urb_priv
);
302 spin_unlock_irqrestore (&ohci
->lock
, flags
);
307 * decouple the URB from the HC queues (TDs, urb_priv); it's
308 * already marked using urb->status. reporting is always done
309 * asynchronously, and we might be dealing with an urb that's
310 * partially transferred, or an ED with other urbs being unlinked.
312 static int ohci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
314 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
317 #ifdef OHCI_VERBOSE_DEBUG
318 urb_print (urb
, "UNLINK", 1);
321 spin_lock_irqsave (&ohci
->lock
, flags
);
322 if (HC_IS_RUNNING(hcd
->state
)) {
323 urb_priv_t
*urb_priv
;
325 /* Unless an IRQ completed the unlink while it was being
326 * handed to us, flag it for unlink and giveback, and force
327 * some upcoming INTR_SF to call finish_unlinks()
329 urb_priv
= urb
->hcpriv
;
331 if (urb_priv
->ed
->state
== ED_OPER
)
332 start_ed_unlink (ohci
, urb_priv
->ed
);
336 * with HC dead, we won't respect hc queue pointers
337 * any more ... just clean up every urb's memory.
340 finish_urb (ohci
, urb
);
342 spin_unlock_irqrestore (&ohci
->lock
, flags
);
346 /*-------------------------------------------------------------------------*/
348 /* frees config/altsetting state for endpoints,
349 * including ED memory, dummy TD, and bulk/intr data toggle
353 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
355 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
357 struct ed
*ed
= ep
->hcpriv
;
358 unsigned limit
= 1000;
360 /* ASSERT: any requests/urbs are being unlinked */
361 /* ASSERT: nobody can be submitting urbs for this any more */
367 spin_lock_irqsave (&ohci
->lock
, flags
);
369 if (!HC_IS_RUNNING (hcd
->state
)) {
372 finish_unlinks (ohci
, 0);
376 case ED_UNLINK
: /* wait for hw to finish? */
377 /* major IRQ delivery trouble loses INTR_SF too... */
379 ohci_warn (ohci
, "IRQ INTR_SF lossage\n");
382 spin_unlock_irqrestore (&ohci
->lock
, flags
);
383 schedule_timeout_uninterruptible(1);
385 case ED_IDLE
: /* fully unlinked */
386 if (list_empty (&ed
->td_list
)) {
387 td_free (ohci
, ed
->dummy
);
391 /* else FALL THROUGH */
393 /* caller was supposed to have unlinked any requests;
394 * that's not our job. can't recover; must leak ed.
396 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
397 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
398 list_empty (&ed
->td_list
) ? "" : " (has tds)");
399 td_free (ohci
, ed
->dummy
);
403 spin_unlock_irqrestore (&ohci
->lock
, flags
);
407 static int ohci_get_frame (struct usb_hcd
*hcd
)
409 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
411 return ohci_frame_no(ohci
);
414 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
416 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
417 ohci
->hc_control
&= OHCI_CTRL_RWC
;
418 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
421 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
422 * other cases where the next software may expect clean state from the
423 * "firmware". this is bus-neutral, unlike shutdown() methods.
426 ohci_shutdown (struct usb_hcd
*hcd
)
428 struct ohci_hcd
*ohci
;
430 ohci
= hcd_to_ohci (hcd
);
431 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
432 ohci_usb_reset (ohci
);
433 /* flush the writes */
434 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
437 /*-------------------------------------------------------------------------*
439 *-------------------------------------------------------------------------*/
441 /* init memory, and kick BIOS/SMM off */
443 static int ohci_init (struct ohci_hcd
*ohci
)
446 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
449 ohci
->regs
= hcd
->regs
;
451 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
452 * was never needed for most non-PCI systems ... remove the code?
456 /* SMM owns the HC? not for long! */
457 if (!no_handshake
&& ohci_readl (ohci
,
458 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
461 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
463 /* this timeout is arbitrary. we make it long, so systems
464 * depending on usb keyboards may be usable even if the
465 * BIOS/SMM code seems pretty broken.
467 temp
= 500; /* arbitrary: five seconds */
469 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
470 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
471 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
474 ohci_err (ohci
, "USB HC takeover failed!"
475 " (BIOS/SMM bug)\n");
479 ohci_usb_reset (ohci
);
483 /* Disable HC interrupts */
484 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
486 /* flush the writes, and save key bits like RWC */
487 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
488 ohci
->hc_control
|= OHCI_CTRL_RWC
;
490 /* Read the number of ports unless overridden */
491 if (ohci
->num_ports
== 0)
492 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
497 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
498 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
502 if ((ret
= ohci_mem_init (ohci
)) < 0)
505 create_debug_files (ohci
);
511 /*-------------------------------------------------------------------------*/
513 /* Start an OHCI controller, set the BUS operational
514 * resets USB and controller
517 static int ohci_run (struct ohci_hcd
*ohci
)
520 int first
= ohci
->fminterval
== 0;
521 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
525 /* boot firmware should have set this up (5.1.1.3.1) */
528 temp
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
529 ohci
->fminterval
= temp
& 0x3fff;
530 if (ohci
->fminterval
!= FI
)
531 ohci_dbg (ohci
, "fminterval delta %d\n",
532 ohci
->fminterval
- FI
);
533 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
534 /* also: power/overcurrent flags in roothub.a */
537 /* Reset USB nearly "by the book". RemoteWakeupConnected was
538 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
539 * or if bus glue did the same (e.g. for PCI add-in cards with
542 ohci_dbg (ohci
, "resetting from state '%s', control = 0x%x\n",
543 hcfs2string (ohci
->hc_control
& OHCI_CTRL_HCFS
),
544 ohci_readl (ohci
, &ohci
->regs
->control
));
545 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0
546 && !device_may_wakeup(hcd
->self
.controller
))
547 device_init_wakeup(hcd
->self
.controller
, 1);
549 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
553 case OHCI_USB_SUSPEND
:
554 case OHCI_USB_RESUME
:
555 ohci
->hc_control
&= OHCI_CTRL_RWC
;
556 ohci
->hc_control
|= OHCI_USB_RESUME
;
557 temp
= 10 /* msec wait */;
559 // case OHCI_USB_RESET:
561 ohci
->hc_control
&= OHCI_CTRL_RWC
;
562 ohci
->hc_control
|= OHCI_USB_RESET
;
563 temp
= 50 /* msec wait */;
566 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
568 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
570 temp
= roothub_a (ohci
);
571 if (!(temp
& RH_A_NPS
)) {
572 /* power down each port */
573 for (temp
= 0; temp
< ohci
->num_ports
; temp
++)
574 ohci_writel (ohci
, RH_PS_LSDA
,
575 &ohci
->regs
->roothub
.portstatus
[temp
]);
577 // flush those writes
578 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
579 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
581 /* 2msec timelimit here means no irqs/preempt */
582 spin_lock_irq (&ohci
->lock
);
585 /* HC Reset requires max 10 us delay */
586 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
587 temp
= 30; /* ... allow extra time */
588 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
590 spin_unlock_irq (&ohci
->lock
);
591 ohci_err (ohci
, "USB HC reset timed out!\n");
597 /* now we're in the SUSPEND state ... must go OPERATIONAL
598 * within 2msec else HC enters RESUME
600 * ... but some hardware won't init fmInterval "by the book"
601 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
602 * this if we write fmInterval after we're OPERATIONAL.
603 * Unclear about ALi, ServerWorks, and others ... this could
604 * easily be a longstanding bug in chip init on Linux.
606 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
607 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
608 // flush those writes
609 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
612 /* Tell the controller where the control and bulk lists are
613 * The lists are empty now. */
614 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
615 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
617 /* a reset clears this */
618 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
620 periodic_reinit (ohci
);
622 /* some OHCI implementations are finicky about how they init.
623 * bogus values here mean not even enumeration could work.
625 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
626 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
627 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
628 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
629 ohci_dbg (ohci
, "enabling initreset quirk\n");
632 spin_unlock_irq (&ohci
->lock
);
633 ohci_err (ohci
, "init err (%08x %04x)\n",
634 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
635 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
639 /* use rhsc irqs after khubd is fully initialized */
641 hcd
->uses_new_polling
= 1;
643 /* start controller operations */
644 ohci
->hc_control
&= OHCI_CTRL_RWC
;
645 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
646 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
647 hcd
->state
= HC_STATE_RUNNING
;
649 /* wake on ConnectStatusChange, matching external hubs */
650 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
652 /* Choose the interrupts we care about now, others later on demand */
653 mask
= OHCI_INTR_INIT
;
654 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
655 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
657 /* handle root hub init quirks ... */
658 temp
= roothub_a (ohci
);
659 temp
&= ~(RH_A_PSM
| RH_A_OCPM
);
660 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
661 /* NSC 87560 and maybe others */
663 temp
&= ~(RH_A_POTPGT
| RH_A_NPS
);
664 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
665 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) || distrust_firmware
) {
666 /* hub power always on; required for AMD-756 and some
667 * Mac platforms. ganged overcurrent reporting, if any.
670 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
672 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
673 ohci_writel (ohci
, (temp
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
674 &ohci
->regs
->roothub
.b
);
675 // flush those writes
676 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
678 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
679 spin_unlock_irq (&ohci
->lock
);
681 // POTPGT delay is bits 24-31, in 2 ms units.
682 mdelay ((temp
>> 23) & 0x1fe);
683 hcd
->state
= HC_STATE_RUNNING
;
690 /*-------------------------------------------------------------------------*/
692 /* an interrupt happens */
694 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
696 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
697 struct ohci_regs __iomem
*regs
= ohci
->regs
;
700 /* we can eliminate a (slow) ohci_readl()
701 if _only_ WDH caused this irq */
702 if ((ohci
->hcca
->done_head
!= 0)
703 && ! (hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
)
705 ints
= OHCI_INTR_WDH
;
707 /* cardbus/... hardware gone before remove() */
708 } else if ((ints
= ohci_readl (ohci
, ®s
->intrstatus
)) == ~(u32
)0) {
710 ohci_dbg (ohci
, "device removed!\n");
713 /* interrupt for some other device? */
714 } else if ((ints
&= ohci_readl (ohci
, ®s
->intrenable
)) == 0) {
718 if (ints
& OHCI_INTR_UE
) {
720 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
721 // e.g. due to PCI Master/Target Abort
724 ohci_usb_reset (ohci
);
727 if (ints
& OHCI_INTR_RHSC
) {
728 ohci_vdbg(ohci
, "rhsc\n");
729 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
730 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
733 /* NOTE: Vendors didn't always make the same implementation
734 * choices for RHSC. Many followed the spec; RHSC triggers
735 * on an edge, like setting and maybe clearing a port status
736 * change bit. With others it's level-triggered, active
737 * until khubd clears all the port status change bits. We'll
738 * always disable it here and rely on polling until khubd
741 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
742 usb_hcd_poll_rh_status(hcd
);
745 /* For connect and disconnect events, we expect the controller
746 * to turn on RHSC along with RD. But for remote wakeup events
747 * this might not happen.
749 else if (ints
& OHCI_INTR_RD
) {
750 ohci_vdbg(ohci
, "resume detect\n");
751 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
753 if (ohci
->autostop
) {
754 spin_lock (&ohci
->lock
);
755 ohci_rh_resume (ohci
);
756 spin_unlock (&ohci
->lock
);
758 usb_hcd_resume_root_hub(hcd
);
761 if (ints
& OHCI_INTR_WDH
) {
762 if (HC_IS_RUNNING(hcd
->state
))
763 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrdisable
);
764 spin_lock (&ohci
->lock
);
766 spin_unlock (&ohci
->lock
);
767 if (HC_IS_RUNNING(hcd
->state
))
768 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrenable
);
771 /* could track INTR_SO to reduce available PCI/... bandwidth */
773 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
774 * when there's still unlinking to be done (next frame).
776 spin_lock (&ohci
->lock
);
777 if (ohci
->ed_rm_list
)
778 finish_unlinks (ohci
, ohci_frame_no(ohci
));
779 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
780 && HC_IS_RUNNING(hcd
->state
))
781 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
782 spin_unlock (&ohci
->lock
);
784 if (HC_IS_RUNNING(hcd
->state
)) {
785 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
786 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
787 // flush those writes
788 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
794 /*-------------------------------------------------------------------------*/
796 static void ohci_stop (struct usb_hcd
*hcd
)
798 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
800 ohci_dbg (ohci
, "stop %s controller (state 0x%02x)\n",
801 hcfs2string (ohci
->hc_control
& OHCI_CTRL_HCFS
),
805 flush_scheduled_work();
807 ohci_usb_reset (ohci
);
808 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
809 free_irq(hcd
->irq
, hcd
);
812 remove_debug_files (ohci
);
813 ohci_mem_cleanup (ohci
);
815 dma_free_coherent (hcd
->self
.controller
,
817 ohci
->hcca
, ohci
->hcca_dma
);
823 /*-------------------------------------------------------------------------*/
825 /* must not be called from interrupt context */
829 static int ohci_restart (struct ohci_hcd
*ohci
)
833 struct urb_priv
*priv
;
835 /* mark any devices gone, so they do nothing till khubd disconnects.
836 * recycle any "live" eds/tds (and urbs) right away.
837 * later, khubd disconnect processing will recycle the other state,
838 * (either as disconnect/reconnect, or maybe someday as a reset).
840 spin_lock_irq(&ohci
->lock
);
842 usb_root_hub_lost_power(ohci_to_hcd(ohci
)->self
.root_hub
);
843 if (!list_empty (&ohci
->pending
))
844 ohci_dbg(ohci
, "abort schedule...\n");
845 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
846 struct urb
*urb
= priv
->td
[0]->urb
;
847 struct ed
*ed
= priv
->ed
;
851 ed
->state
= ED_UNLINK
;
852 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
853 ed_deschedule (ohci
, ed
);
855 ed
->ed_next
= ohci
->ed_rm_list
;
857 ohci
->ed_rm_list
= ed
;
862 ohci_dbg(ohci
, "bogus ed %p state %d\n",
866 spin_lock (&urb
->lock
);
867 urb
->status
= -ESHUTDOWN
;
868 spin_unlock (&urb
->lock
);
870 finish_unlinks (ohci
, 0);
871 spin_unlock_irq(&ohci
->lock
);
873 /* paranoia, in case that didn't work: */
875 /* empty the interrupt branches */
876 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
877 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
879 /* no EDs to remove */
880 ohci
->ed_rm_list
= NULL
;
882 /* empty control and bulk lists */
883 ohci
->ed_controltail
= NULL
;
884 ohci
->ed_bulktail
= NULL
;
886 if ((temp
= ohci_run (ohci
)) < 0) {
887 ohci_err (ohci
, "can't restart, %d\n", temp
);
890 /* here we "know" root ports should always stay powered,
891 * and that if we try to turn them back on the root hub
892 * will respond to CSC processing.
896 ohci_writel (ohci
, RH_PS_PSS
,
897 &ohci
->regs
->roothub
.portstatus
[i
]);
898 ohci_dbg (ohci
, "restart complete\n");
904 /*-------------------------------------------------------------------------*/
906 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
908 MODULE_AUTHOR (DRIVER_AUTHOR
);
909 MODULE_DESCRIPTION (DRIVER_INFO
);
910 MODULE_LICENSE ("GPL");
913 #include "ohci-pci.c"
917 #include "ohci-sa1111.c"
920 #ifdef CONFIG_ARCH_S3C2410
921 #include "ohci-s3c2410.c"
924 #ifdef CONFIG_ARCH_OMAP
925 #include "ohci-omap.c"
928 #ifdef CONFIG_ARCH_LH7A404
929 #include "ohci-lh7a404.c"
933 #include "ohci-pxa27x.c"
936 #ifdef CONFIG_ARCH_EP93XX
937 #include "ohci-ep93xx.c"
940 #ifdef CONFIG_SOC_AU1X00
941 #include "ohci-au1xxx.c"
944 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
945 #include "ohci-ppc-soc.c"
948 #if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
949 #include "ohci-at91.c"
952 #ifdef CONFIG_ARCH_PNX4008
953 #include "ohci-pnx4008.c"
956 #if !(defined(CONFIG_PCI) \
957 || defined(CONFIG_SA1111) \
958 || defined(CONFIG_ARCH_S3C2410) \
959 || defined(CONFIG_ARCH_OMAP) \
960 || defined (CONFIG_ARCH_LH7A404) \
961 || defined (CONFIG_PXA27x) \
962 || defined (CONFIG_ARCH_EP93XX) \
963 || defined (CONFIG_SOC_AU1X00) \
964 || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
965 || defined (CONFIG_ARCH_AT91RM9200) \
966 || defined (CONFIG_ARCH_AT91SAM9261) \
967 || defined (CONFIG_ARCH_PNX4008) \
969 #error "missing bus glue for ohci-hcd"