include/asm-ppc/system.h

   1 /*
   2  * $Id: system.h,v 1.49 1999/09/11 18:37:54 cort Exp $
   3  *
   4  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   5  */
   6 #ifndef __PPC_SYSTEM_H
   7 #define __PPC_SYSTEM_H
   8
   9 #include <linux/config.h>
  10 #include <linux/kdev_t.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/atomic.h>
  14 #include <asm/hw_irq.h>
  15
  16 /*
  17  * Memory barrier.
  18  * The sync instruction guarantees that all memory accesses initiated
  19  * by this processor have been performed (with respect to all other
  20  * mechanisms that access memory).  The eieio instruction is a barrier
  21  * providing an ordering (separately) for (a) cacheable stores and (b)
  22  * loads and stores to non-cacheable memory (e.g. I/O devices).
  23  *
  24  * mb() prevents loads and stores being reordered across this point.
  25  * rmb() prevents loads being reordered across this point.
  26  * wmb() prevents stores being reordered across this point.
  27  *
  28  * We can use the eieio instruction for wmb, but since it doesn't
  29  * give any ordering guarantees about loads, we have to use the
  30  * stronger but slower sync instruction for mb and rmb.
  31  */
  32 #define mb()  __asm__ __volatile__ ("sync" : : : "memory")
  33 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  34 #define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
  35
  36 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  37 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
  38
  39 extern void xmon_irq(int, void *, struct pt_regs *);
  40 extern void xmon(struct pt_regs *excp);
  41
  42
  43 /* Data cache block flush - write out the cache line containing the
  44    specified address and then invalidate it in the cache. */
  45 extern __inline__ void dcbf(void *line)
  46 {
  47         asm("dcbf %0,%1; sync" : : "r" (line), "r" (0));
  48 }
  49
  50 extern void print_backtrace(unsigned long *);
  51 extern void show_regs(struct pt_regs * regs);
  52 extern void flush_instruction_cache(void);
  53 extern void hard_reset_now(void);
  54 extern void poweroff_now(void);
  55 extern int _get_PVR(void);
  56 extern long _get_L2CR(void);
  57 extern void _set_L2CR(unsigned long);
  58 extern void via_cuda_init(void);
  59 extern void pmac_nvram_init(void);
  60 extern void read_rtc_time(void);
  61 extern void pmac_find_display(void);
  62 extern void giveup_fpu(struct task_struct *);
  63 extern void enable_kernel_fp(void);
  64 extern void giveup_altivec(struct task_struct *);
  65 extern void load_up_altivec(struct task_struct *);
  66 extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
  67 extern void cvt_df(double *from, float *to, unsigned long *fpscr);
  68 extern int call_rtas(const char *, int, int, unsigned long *, ...);
  69 extern int abs(int);
  70
  71 struct device_node;
  72 extern void note_scsi_host(struct device_node *, void *);
  73
  74 struct task_struct;
  75 #define prepare_to_switch()     do { } while(0)
  76 #define switch_to(prev,next,last) _switch_to((prev),(next),&(last))
  77 extern void _switch_to(struct task_struct *, struct task_struct *,
  78                        struct task_struct **);
  79
  80 struct thread_struct;
  81 extern struct task_struct *_switch(struct thread_struct *prev,
  82                                    struct thread_struct *next);
  83
  84 extern unsigned int rtas_data;
  85
  86 struct pt_regs;
  87 extern void dump_regs(struct pt_regs *);
  88
  89 #ifndef CONFIG_SMP
  90
  91 #define cli()   __cli()
  92 #define sti()   __sti()
  93 #define save_flags(flags)       __save_flags(flags)
  94 #define restore_flags(flags)    __restore_flags(flags)
  95 #define save_and_cli(flags)     __save_and_cli(flags)
  96
  97 #else /* CONFIG_SMP */
  98
  99 extern void __global_cli(void);
 100 extern void __global_sti(void);
 101 extern unsigned long __global_save_flags(void);
 102 extern void __global_restore_flags(unsigned long);
 103 #define cli() __global_cli()
 104 #define sti() __global_sti()
 105 #define save_flags(x) ((x)=__global_save_flags())
 106 #define restore_flags(x) __global_restore_flags(x)
 107
 108 #endif /* !CONFIG_SMP */
 109
 110 #define local_irq_disable()             __cli()
 111 #define local_irq_enable()              __sti()
 112 #define local_irq_save(flags)           __save_and_cli(flags)
 113 #define local_irq_restore(flags)        __restore_flags(flags)
 114
 115 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 116
 117 extern unsigned long xchg_u64(void *ptr, unsigned long val);
 118 extern unsigned long xchg_u32(void *ptr, unsigned long val);
 119
 120 /*
 121  * This function doesn't exist, so you'll get a linker error
 122  * if something tries to do an invalid xchg().
 123  *
 124  * This only works if the compiler isn't horribly bad at optimizing.
 125  * gcc-2.5.8 reportedly can't handle this, but as that doesn't work
 126  * too well on the alpha anyway..
 127  */
 128 extern void __xchg_called_with_bad_pointer(void);
 129
 130 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 131 #define tas(ptr) (xchg((ptr),1))
 132
 133 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 134 {
 135         switch (size) {
 136         case 4:
 137                 return (unsigned long )xchg_u32(ptr, x);
 138         case 8:
 139                 return (unsigned long )xchg_u64(ptr, x);
 140         }
 141         __xchg_called_with_bad_pointer();
 142         return x;
 143
 144
 145 }
 146
 147 extern inline void * xchg_ptr(void * m, void * val)
 148 {
 149         return (void *) xchg_u32(m, (unsigned long) val);
 150 }
 151
 152 #endif