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cxgb3 - Fix potential MAC hang
[linux-2.6/linux-loongson.git] / drivers / net / sky2.c
blobab0ab92583fe427a0568cbb87c5571b918909998
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
42
43 #include <asm/irq.h>
44
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
47 #endif
48
49 #include "sky2.h"
50
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.13"
53 #define PFX DRV_NAME " "
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
101
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
133 { 0 }
134 };
135
136 MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
141 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
142
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
150 };
151
152 /* Access to external PHY */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
163 return 0;
164 udelay(1);
165 }
166
167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
168 return -ETIMEDOUT;
169 }
170
171 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
172 {
173 int i;
174
175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177
178 for (i = 0; i < PHY_RETRIES; i++) {
179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
181 return 0;
182 }
183
184 udelay(1);
185 }
186
187 return -ETIMEDOUT;
188 }
189
190 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191 {
192 u16 v;
193
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 return v;
197 }
198
199
200 static void sky2_power_on(struct sky2_hw *hw)
201 {
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
205
206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
208
209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 else
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
217
218 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
219 u32 reg1;
220
221 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 &= P_ASPM_CONTROL_MSK;
224 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
225 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
226 }
227 }
228
229 static void sky2_power_aux(struct sky2_hw *hw)
230 {
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 else
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239
240 /* switch power to VAUX */
241 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
242 sky2_write8(hw, B0_POWER_CTRL,
243 (PC_VAUX_ENA | PC_VCC_ENA |
244 PC_VAUX_ON | PC_VCC_OFF));
245 }
246
247 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
248 {
249 u16 reg;
250
251 /* disable all GMAC IRQ's */
252 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
253 /* disable PHY IRQs */
254 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
255
256 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
257 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
258 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
260
261 reg = gma_read16(hw, port, GM_RX_CTRL);
262 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
263 gma_write16(hw, port, GM_RX_CTRL, reg);
264 }
265
266 /* flow control to advertise bits */
267 static const u16 copper_fc_adv[] = {
268 [FC_NONE] = 0,
269 [FC_TX] = PHY_M_AN_ASP,
270 [FC_RX] = PHY_M_AN_PC,
271 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
272 };
273
274 /* flow control to advertise bits when using 1000BaseX */
275 static const u16 fiber_fc_adv[] = {
276 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
277 [FC_TX] = PHY_M_P_ASYM_MD_X,
278 [FC_RX] = PHY_M_P_SYM_MD_X,
279 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
280 };
281
282 /* flow control to GMA disable bits */
283 static const u16 gm_fc_disable[] = {
284 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
285 [FC_TX] = GM_GPCR_FC_RX_DIS,
286 [FC_RX] = GM_GPCR_FC_TX_DIS,
287 [FC_BOTH] = 0,
288 };
289
290
291 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
292 {
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
295
296 if (sky2->autoneg == AUTONEG_ENABLE
297 && !(hw->chip_id == CHIP_ID_YUKON_XL
298 || hw->chip_id == CHIP_ID_YUKON_EC_U
299 || hw->chip_id == CHIP_ID_YUKON_EX)) {
300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
303 PHY_M_EC_MAC_S_MSK);
304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (sky2_is_copper(hw)) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 if (sky2->autoneg == AUTONEG_ENABLE
327 && (hw->chip_id == CHIP_ID_YUKON_XL
328 || hw->chip_id == CHIP_ID_YUKON_EC_U
329 || hw->chip_id == CHIP_ID_YUKON_EX)) {
330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
334 } else {
335 /* workaround for deviation #4.88 (CRC errors) */
336 /* disable Automatic Crossover */
337
338 ctrl &= ~PHY_M_PC_MDIX_MSK;
339 }
340
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342
343 /* special setup for PHY 88E1112 Fiber */
344 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
345 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
346
347 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 ctrl &= ~PHY_M_MAC_MD_MSK;
351 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
353
354 if (hw->pmd_type == 'P') {
355 /* select page 1 to access Fiber registers */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
357
358 /* for SFP-module set SIGDET polarity to low */
359 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
360 ctrl |= PHY_M_FIB_SIGD_POL;
361 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
362 }
363
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
365 }
366
367 ctrl = PHY_CT_RESET;
368 ct1000 = 0;
369 adv = PHY_AN_CSMA;
370 reg = 0;
371
372 if (sky2->autoneg == AUTONEG_ENABLE) {
373 if (sky2_is_copper(hw)) {
374 if (sky2->advertising & ADVERTISED_1000baseT_Full)
375 ct1000 |= PHY_M_1000C_AFD;
376 if (sky2->advertising & ADVERTISED_1000baseT_Half)
377 ct1000 |= PHY_M_1000C_AHD;
378 if (sky2->advertising & ADVERTISED_100baseT_Full)
379 adv |= PHY_M_AN_100_FD;
380 if (sky2->advertising & ADVERTISED_100baseT_Half)
381 adv |= PHY_M_AN_100_HD;
382 if (sky2->advertising & ADVERTISED_10baseT_Full)
383 adv |= PHY_M_AN_10_FD;
384 if (sky2->advertising & ADVERTISED_10baseT_Half)
385 adv |= PHY_M_AN_10_HD;
386
387 adv |= copper_fc_adv[sky2->flow_mode];
388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
393
394 adv |= fiber_fc_adv[sky2->flow_mode];
395 }
396
397 /* Restart Auto-negotiation */
398 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
399 } else {
400 /* forced speed/duplex settings */
401 ct1000 = PHY_M_1000C_MSE;
402
403 /* Disable auto update for duplex flow control and speed */
404 reg |= GM_GPCR_AU_ALL_DIS;
405
406 switch (sky2->speed) {
407 case SPEED_1000:
408 ctrl |= PHY_CT_SP1000;
409 reg |= GM_GPCR_SPEED_1000;
410 break;
411 case SPEED_100:
412 ctrl |= PHY_CT_SP100;
413 reg |= GM_GPCR_SPEED_100;
414 break;
415 }
416
417 if (sky2->duplex == DUPLEX_FULL) {
418 reg |= GM_GPCR_DUP_FULL;
419 ctrl |= PHY_CT_DUP_MD;
420 } else if (sky2->speed < SPEED_1000)
421 sky2->flow_mode = FC_NONE;
422
423
424 reg |= gm_fc_disable[sky2->flow_mode];
425
426 /* Forward pause packets to GMAC? */
427 if (sky2->flow_mode & FC_RX)
428 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
429 else
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
431 }
432
433 gma_write16(hw, port, GM_GP_CTRL, reg);
434
435 if (hw->chip_id != CHIP_ID_YUKON_FE)
436 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
437
438 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
439 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
440
441 /* Setup Phy LED's */
442 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
443 ledover = 0;
444
445 switch (hw->chip_id) {
446 case CHIP_ID_YUKON_FE:
447 /* on 88E3082 these bits are at 11..9 (shifted left) */
448 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
449
450 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
451
452 /* delete ACT LED control bits */
453 ctrl &= ~PHY_M_FELP_LED1_MSK;
454 /* change ACT LED control to blink mode */
455 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
456 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
457 break;
458
459 case CHIP_ID_YUKON_XL:
460 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
461
462 /* select page 3 to access LED control register */
463 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
464
465 /* set LED Function Control register */
466 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
467 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
468 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
469 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
470 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
471
472 /* set Polarity Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
474 (PHY_M_POLC_LS1_P_MIX(4) |
475 PHY_M_POLC_IS0_P_MIX(4) |
476 PHY_M_POLC_LOS_CTRL(2) |
477 PHY_M_POLC_INIT_CTRL(2) |
478 PHY_M_POLC_STA1_CTRL(2) |
479 PHY_M_POLC_STA0_CTRL(2)));
480
481 /* restore page register */
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
483 break;
484
485 case CHIP_ID_YUKON_EC_U:
486 case CHIP_ID_YUKON_EX:
487 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
488
489 /* select page 3 to access LED control register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
491
492 /* set LED Function Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
494 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
495 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
496 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
497 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
498
499 /* set Blink Rate in LED Timer Control Register */
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
501 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
502 /* restore page register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
504 break;
505
506 default:
507 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
509 /* turn off the Rx LED (LED_RX) */
510 ledover &= ~PHY_M_LED_MO_RX;
511 }
512
513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
514 /* apply fixes in PHY AFE */
515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
517
518 /* increase differential signal amplitude in 10BASE-T */
519 gm_phy_write(hw, port, 0x18, 0xaa99);
520 gm_phy_write(hw, port, 0x17, 0x2011);
521
522 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
523 gm_phy_write(hw, port, 0x18, 0xa204);
524 gm_phy_write(hw, port, 0x17, 0x2002);
525
526 /* set page register to 0 */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
530
531 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
532 /* turn on 100 Mbps LED (LED_LINK100) */
533 ledover |= PHY_M_LED_MO_100;
534 }
535
536 if (ledover)
537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
538
539 }
540
541 /* Enable phy interrupt on auto-negotiation complete (or link up) */
542 if (sky2->autoneg == AUTONEG_ENABLE)
543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
544 else
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
546 }
547
548 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
549 {
550 u32 reg1;
551 static const u32 phy_power[]
552 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
553
554 /* looks like this XL is back asswards .. */
555 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
556 onoff = !onoff;
557
558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
559 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
560 if (onoff)
561 /* Turn off phy power saving */
562 reg1 &= ~phy_power[port];
563 else
564 reg1 |= phy_power[port];
565
566 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
567 sky2_pci_read32(hw, PCI_DEV_REG1);
568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
569 udelay(100);
570 }
571
572 /* Force a renegotiation */
573 static void sky2_phy_reinit(struct sky2_port *sky2)
574 {
575 spin_lock_bh(&sky2->phy_lock);
576 sky2_phy_init(sky2->hw, sky2->port);
577 spin_unlock_bh(&sky2->phy_lock);
578 }
579
580 /* Put device in state to listen for Wake On Lan */
581 static void sky2_wol_init(struct sky2_port *sky2)
582 {
583 struct sky2_hw *hw = sky2->hw;
584 unsigned port = sky2->port;
585 enum flow_control save_mode;
586 u16 ctrl;
587 u32 reg1;
588
589 /* Bring hardware out of reset */
590 sky2_write16(hw, B0_CTST, CS_RST_CLR);
591 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
592
593 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
595
596 /* Force to 10/100
597 * sky2_reset will re-enable on resume
598 */
599 save_mode = sky2->flow_mode;
600 ctrl = sky2->advertising;
601
602 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
603 sky2->flow_mode = FC_NONE;
604 sky2_phy_power(hw, port, 1);
605 sky2_phy_reinit(sky2);
606
607 sky2->flow_mode = save_mode;
608 sky2->advertising = ctrl;
609
610 /* Set GMAC to no flow control and auto update for speed/duplex */
611 gma_write16(hw, port, GM_GP_CTRL,
612 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
613 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
614
615 /* Set WOL address */
616 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
617 sky2->netdev->dev_addr, ETH_ALEN);
618
619 /* Turn on appropriate WOL control bits */
620 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
621 ctrl = 0;
622 if (sky2->wol & WAKE_PHY)
623 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
624 else
625 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
626
627 if (sky2->wol & WAKE_MAGIC)
628 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
629 else
630 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
631
632 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
633 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
634
635 /* Turn on legacy PCI-Express PME mode */
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638 reg1 |= PCI_Y2_PME_LEGACY;
639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641
642 /* block receiver */
643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
644
645 }
646
647 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
648 {
649 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
650 u16 reg;
651 int i;
652 const u8 *addr = hw->dev[port]->dev_addr;
653
654 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
656
657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
658
659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
660 /* WA DEV_472 -- looks like crossed wires on port 2 */
661 /* clear GMAC 1 Control reset */
662 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
663 do {
664 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
666 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
667 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
668 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
669 }
670
671 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
672
673 /* Enable Transmit FIFO Underrun */
674 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
675
676 spin_lock_bh(&sky2->phy_lock);
677 sky2_phy_init(hw, port);
678 spin_unlock_bh(&sky2->phy_lock);
679
680 /* MIB clear */
681 reg = gma_read16(hw, port, GM_PHY_ADDR);
682 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
683
684 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
685 gma_read16(hw, port, i);
686 gma_write16(hw, port, GM_PHY_ADDR, reg);
687
688 /* transmit control */
689 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
690
691 /* receive control reg: unicast + multicast + no FCS */
692 gma_write16(hw, port, GM_RX_CTRL,
693 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
694
695 /* transmit flow control */
696 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
697
698 /* transmit parameter */
699 gma_write16(hw, port, GM_TX_PARAM,
700 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
701 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
702 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
703 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
704
705 /* serial mode register */
706 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
707 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
708
709 if (hw->dev[port]->mtu > ETH_DATA_LEN)
710 reg |= GM_SMOD_JUMBO_ENA;
711
712 gma_write16(hw, port, GM_SERIAL_MODE, reg);
713
714 /* virtual address for data */
715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
716
717 /* physical address: used for pause frames */
718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
719
720 /* ignore counter overflows */
721 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
722 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
724
725 /* Configure Rx MAC FIFO */
726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
727 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
728 GMF_OPER_ON | GMF_RX_F_FL_ON);
729
730 /* Flush Rx MAC FIFO on any flow control or error */
731 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
732
733 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
735
736 /* Configure Tx MAC FIFO */
737 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
738 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
739
740 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
741 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
742 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
743 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
744 /* set Tx GMAC FIFO Almost Empty Threshold */
745 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
746 /* Disable Store & Forward mode for TX */
747 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
748 }
749 }
750
751 }
752
753 /* Assign Ram Buffer allocation to queue */
754 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
755 {
756 u32 end;
757
758 /* convert from K bytes to qwords used for hw register */
759 start *= 1024/8;
760 space *= 1024/8;
761 end = start + space - 1;
762
763 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
764 sky2_write32(hw, RB_ADDR(q, RB_START), start);
765 sky2_write32(hw, RB_ADDR(q, RB_END), end);
766 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
767 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
768
769 if (q == Q_R1 || q == Q_R2) {
770 u32 tp = space - space/4;
771
772 /* On receive queue's set the thresholds
773 * give receiver priority when > 3/4 full
774 * send pause when down to 2K
775 */
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
778
779 tp = space - 2048/8;
780 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
781 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
782 } else {
783 /* Enable store & forward on Tx queue's because
784 * Tx FIFO is only 1K on Yukon
785 */
786 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
787 }
788
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
790 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
791 }
792
793 /* Setup Bus Memory Interface */
794 static void sky2_qset(struct sky2_hw *hw, u16 q)
795 {
796 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
797 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
798 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
799 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
800 }
801
802 /* Setup prefetch unit registers. This is the interface between
803 * hardware and driver list elements
804 */
805 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
806 u64 addr, u32 last)
807 {
808 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
810 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
812 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
814
815 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
816 }
817
818 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
819 {
820 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
821
822 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
823 le->ctrl = 0;
824 return le;
825 }
826
827 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
828 struct sky2_tx_le *le)
829 {
830 return sky2->tx_ring + (le - sky2->tx_le);
831 }
832
833 /* Update chip's next pointer */
834 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
835 {
836 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
837 wmb();
838 sky2_write16(hw, q, idx);
839 sky2_read16(hw, q);
840 }
841
842
843 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
844 {
845 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
846 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
847 le->ctrl = 0;
848 return le;
849 }
850
851 /* Return high part of DMA address (could be 32 or 64 bit) */
852 static inline u32 high32(dma_addr_t a)
853 {
854 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
855 }
856
857 /* Build description to hardware for one receive segment */
858 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
859 dma_addr_t map, unsigned len)
860 {
861 struct sky2_rx_le *le;
862 u32 hi = high32(map);
863
864 if (sky2->rx_addr64 != hi) {
865 le = sky2_next_rx(sky2);
866 le->addr = cpu_to_le32(hi);
867 le->opcode = OP_ADDR64 | HW_OWNER;
868 sky2->rx_addr64 = high32(map + len);
869 }
870
871 le = sky2_next_rx(sky2);
872 le->addr = cpu_to_le32((u32) map);
873 le->length = cpu_to_le16(len);
874 le->opcode = op | HW_OWNER;
875 }
876
877 /* Build description to hardware for one possibly fragmented skb */
878 static void sky2_rx_submit(struct sky2_port *sky2,
879 const struct rx_ring_info *re)
880 {
881 int i;
882
883 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
884
885 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
886 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
887 }
888
889
890 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
891 unsigned size)
892 {
893 struct sk_buff *skb = re->skb;
894 int i;
895
896 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
897 pci_unmap_len_set(re, data_size, size);
898
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
900 re->frag_addr[i] = pci_map_page(pdev,
901 skb_shinfo(skb)->frags[i].page,
902 skb_shinfo(skb)->frags[i].page_offset,
903 skb_shinfo(skb)->frags[i].size,
904 PCI_DMA_FROMDEVICE);
905 }
906
907 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
908 {
909 struct sk_buff *skb = re->skb;
910 int i;
911
912 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
913 PCI_DMA_FROMDEVICE);
914
915 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
916 pci_unmap_page(pdev, re->frag_addr[i],
917 skb_shinfo(skb)->frags[i].size,
918 PCI_DMA_FROMDEVICE);
919 }
920
921 /* Tell chip where to start receive checksum.
922 * Actually has two checksums, but set both same to avoid possible byte
923 * order problems.
924 */
925 static void rx_set_checksum(struct sky2_port *sky2)
926 {
927 struct sky2_rx_le *le;
928
929 le = sky2_next_rx(sky2);
930 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
931 le->ctrl = 0;
932 le->opcode = OP_TCPSTART | HW_OWNER;
933
934 sky2_write32(sky2->hw,
935 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
936 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
937
938 }
939
940 /*
941 * The RX Stop command will not work for Yukon-2 if the BMU does not
942 * reach the end of packet and since we can't make sure that we have
943 * incoming data, we must reset the BMU while it is not doing a DMA
944 * transfer. Since it is possible that the RX path is still active,
945 * the RX RAM buffer will be stopped first, so any possible incoming
946 * data will not trigger a DMA. After the RAM buffer is stopped, the
947 * BMU is polled until any DMA in progress is ended and only then it
948 * will be reset.
949 */
950 static void sky2_rx_stop(struct sky2_port *sky2)
951 {
952 struct sky2_hw *hw = sky2->hw;
953 unsigned rxq = rxqaddr[sky2->port];
954 int i;
955
956 /* disable the RAM Buffer receive queue */
957 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
958
959 for (i = 0; i < 0xffff; i++)
960 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
961 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
962 goto stopped;
963
964 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
965 sky2->netdev->name);
966 stopped:
967 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
968
969 /* reset the Rx prefetch unit */
970 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
971 }
972
973 /* Clean out receive buffer area, assumes receiver hardware stopped */
974 static void sky2_rx_clean(struct sky2_port *sky2)
975 {
976 unsigned i;
977
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
979 for (i = 0; i < sky2->rx_pending; i++) {
980 struct rx_ring_info *re = sky2->rx_ring + i;
981
982 if (re->skb) {
983 sky2_rx_unmap_skb(sky2->hw->pdev, re);
984 kfree_skb(re->skb);
985 re->skb = NULL;
986 }
987 }
988 }
989
990 /* Basic MII support */
991 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
992 {
993 struct mii_ioctl_data *data = if_mii(ifr);
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 int err = -EOPNOTSUPP;
997
998 if (!netif_running(dev))
999 return -ENODEV; /* Phy still in reset */
1000
1001 switch (cmd) {
1002 case SIOCGMIIPHY:
1003 data->phy_id = PHY_ADDR_MARV;
1004
1005 /* fallthru */
1006 case SIOCGMIIREG: {
1007 u16 val = 0;
1008
1009 spin_lock_bh(&sky2->phy_lock);
1010 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1011 spin_unlock_bh(&sky2->phy_lock);
1012
1013 data->val_out = val;
1014 break;
1015 }
1016
1017 case SIOCSMIIREG:
1018 if (!capable(CAP_NET_ADMIN))
1019 return -EPERM;
1020
1021 spin_lock_bh(&sky2->phy_lock);
1022 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1023 data->val_in);
1024 spin_unlock_bh(&sky2->phy_lock);
1025 break;
1026 }
1027 return err;
1028 }
1029
1030 #ifdef SKY2_VLAN_TAG_USED
1031 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1032 {
1033 struct sky2_port *sky2 = netdev_priv(dev);
1034 struct sky2_hw *hw = sky2->hw;
1035 u16 port = sky2->port;
1036
1037 netif_tx_lock_bh(dev);
1038
1039 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1040 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1041 sky2->vlgrp = grp;
1042
1043 netif_tx_unlock_bh(dev);
1044 }
1045
1046 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1047 {
1048 struct sky2_port *sky2 = netdev_priv(dev);
1049 struct sky2_hw *hw = sky2->hw;
1050 u16 port = sky2->port;
1051
1052 netif_tx_lock_bh(dev);
1053
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1055 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1056 vlan_group_set_device(sky2->vlgrp, vid, NULL);
1057
1058 netif_tx_unlock_bh(dev);
1059 }
1060 #endif
1061
1062 /*
1063 * Allocate an skb for receiving. If the MTU is large enough
1064 * make the skb non-linear with a fragment list of pages.
1065 *
1066 * It appears the hardware has a bug in the FIFO logic that
1067 * cause it to hang if the FIFO gets overrun and the receive buffer
1068 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1069 * aligned except if slab debugging is enabled.
1070 */
1071 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1072 {
1073 struct sk_buff *skb;
1074 unsigned long p;
1075 int i;
1076
1077 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1078 if (!skb)
1079 goto nomem;
1080
1081 p = (unsigned long) skb->data;
1082 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1083
1084 for (i = 0; i < sky2->rx_nfrags; i++) {
1085 struct page *page = alloc_page(GFP_ATOMIC);
1086
1087 if (!page)
1088 goto free_partial;
1089 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1090 }
1091
1092 return skb;
1093 free_partial:
1094 kfree_skb(skb);
1095 nomem:
1096 return NULL;
1097 }
1098
1099 /*
1100 * Allocate and setup receiver buffer pool.
1101 * Normal case this ends up creating one list element for skb
1102 * in the receive ring. Worst case if using large MTU and each
1103 * allocation falls on a different 64 bit region, that results
1104 * in 6 list elements per ring entry.
1105 * One element is used for checksum enable/disable, and one
1106 * extra to avoid wrap.
1107 */
1108 static int sky2_rx_start(struct sky2_port *sky2)
1109 {
1110 struct sky2_hw *hw = sky2->hw;
1111 struct rx_ring_info *re;
1112 unsigned rxq = rxqaddr[sky2->port];
1113 unsigned i, size, space, thresh;
1114
1115 sky2->rx_put = sky2->rx_next = 0;
1116 sky2_qset(hw, rxq);
1117
1118 /* On PCI express lowering the watermark gives better performance */
1119 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1120 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1121
1122 /* These chips have no ram buffer?
1123 * MAC Rx RAM Read is controlled by hardware */
1124 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1125 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1126 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1127 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1128
1129 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1130
1131 rx_set_checksum(sky2);
1132
1133 /* Space needed for frame data + headers rounded up */
1134 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1135 + 8;
1136
1137 /* Stopping point for hardware truncation */
1138 thresh = (size - 8) / sizeof(u32);
1139
1140 /* Account for overhead of skb - to avoid order > 0 allocation */
1141 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1142 + sizeof(struct skb_shared_info);
1143
1144 sky2->rx_nfrags = space >> PAGE_SHIFT;
1145 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1146
1147 if (sky2->rx_nfrags != 0) {
1148 /* Compute residue after pages */
1149 space = sky2->rx_nfrags << PAGE_SHIFT;
1150
1151 if (space < size)
1152 size -= space;
1153 else
1154 size = 0;
1155
1156 /* Optimize to handle small packets and headers */
1157 if (size < copybreak)
1158 size = copybreak;
1159 if (size < ETH_HLEN)
1160 size = ETH_HLEN;
1161 }
1162 sky2->rx_data_size = size;
1163
1164 /* Fill Rx ring */
1165 for (i = 0; i < sky2->rx_pending; i++) {
1166 re = sky2->rx_ring + i;
1167
1168 re->skb = sky2_rx_alloc(sky2);
1169 if (!re->skb)
1170 goto nomem;
1171
1172 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1173 sky2_rx_submit(sky2, re);
1174 }
1175
1176 /*
1177 * The receiver hangs if it receives frames larger than the
1178 * packet buffer. As a workaround, truncate oversize frames, but
1179 * the register is limited to 9 bits, so if you do frames > 2052
1180 * you better get the MTU right!
1181 */
1182 if (thresh > 0x1ff)
1183 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1184 else {
1185 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1186 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1187 }
1188
1189 /* Tell chip about available buffers */
1190 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1191 return 0;
1192 nomem:
1193 sky2_rx_clean(sky2);
1194 return -ENOMEM;
1195 }
1196
1197 /* Bring up network interface. */
1198 static int sky2_up(struct net_device *dev)
1199 {
1200 struct sky2_port *sky2 = netdev_priv(dev);
1201 struct sky2_hw *hw = sky2->hw;
1202 unsigned port = sky2->port;
1203 u32 ramsize, imask;
1204 int cap, err = -ENOMEM;
1205 struct net_device *otherdev = hw->dev[sky2->port^1];
1206
1207 /*
1208 * On dual port PCI-X card, there is an problem where status
1209 * can be received out of order due to split transactions
1210 */
1211 if (otherdev && netif_running(otherdev) &&
1212 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1213 struct sky2_port *osky2 = netdev_priv(otherdev);
1214 u16 cmd;
1215
1216 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1217 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1218 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1219
1220 sky2->rx_csum = 0;
1221 osky2->rx_csum = 0;
1222 }
1223
1224 if (netif_msg_ifup(sky2))
1225 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1226
1227 /* must be power of 2 */
1228 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1229 TX_RING_SIZE *
1230 sizeof(struct sky2_tx_le),
1231 &sky2->tx_le_map);
1232 if (!sky2->tx_le)
1233 goto err_out;
1234
1235 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1236 GFP_KERNEL);
1237 if (!sky2->tx_ring)
1238 goto err_out;
1239 sky2->tx_prod = sky2->tx_cons = 0;
1240
1241 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1242 &sky2->rx_le_map);
1243 if (!sky2->rx_le)
1244 goto err_out;
1245 memset(sky2->rx_le, 0, RX_LE_BYTES);
1246
1247 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1248 GFP_KERNEL);
1249 if (!sky2->rx_ring)
1250 goto err_out;
1251
1252 sky2_phy_power(hw, port, 1);
1253
1254 sky2_mac_init(hw, port);
1255
1256 /* Register is number of 4K blocks on internal RAM buffer. */
1257 ramsize = sky2_read8(hw, B2_E_0) * 4;
1258 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1259
1260 if (ramsize > 0) {
1261 u32 rxspace;
1262
1263 if (ramsize < 16)
1264 rxspace = ramsize / 2;
1265 else
1266 rxspace = 8 + (2*(ramsize - 16))/3;
1267
1268 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1269 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1270
1271 /* Make sure SyncQ is disabled */
1272 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1273 RB_RST_SET);
1274 }
1275
1276 sky2_qset(hw, txqaddr[port]);
1277
1278 /* Set almost empty threshold */
1279 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1280 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1281 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1282
1283 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1284 TX_RING_SIZE - 1);
1285
1286 err = sky2_rx_start(sky2);
1287 if (err)
1288 goto err_out;
1289
1290 /* Enable interrupts from phy/mac for port */
1291 imask = sky2_read32(hw, B0_IMSK);
1292 imask |= portirq_msk[port];
1293 sky2_write32(hw, B0_IMSK, imask);
1294
1295 return 0;
1296
1297 err_out:
1298 if (sky2->rx_le) {
1299 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1300 sky2->rx_le, sky2->rx_le_map);
1301 sky2->rx_le = NULL;
1302 }
1303 if (sky2->tx_le) {
1304 pci_free_consistent(hw->pdev,
1305 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1306 sky2->tx_le, sky2->tx_le_map);
1307 sky2->tx_le = NULL;
1308 }
1309 kfree(sky2->tx_ring);
1310 kfree(sky2->rx_ring);
1311
1312 sky2->tx_ring = NULL;
1313 sky2->rx_ring = NULL;
1314 return err;
1315 }
1316
1317 /* Modular subtraction in ring */
1318 static inline int tx_dist(unsigned tail, unsigned head)
1319 {
1320 return (head - tail) & (TX_RING_SIZE - 1);
1321 }
1322
1323 /* Number of list elements available for next tx */
1324 static inline int tx_avail(const struct sky2_port *sky2)
1325 {
1326 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1327 }
1328
1329 /* Estimate of number of transmit list elements required */
1330 static unsigned tx_le_req(const struct sk_buff *skb)
1331 {
1332 unsigned count;
1333
1334 count = sizeof(dma_addr_t) / sizeof(u32);
1335 count += skb_shinfo(skb)->nr_frags * count;
1336
1337 if (skb_is_gso(skb))
1338 ++count;
1339
1340 if (skb->ip_summed == CHECKSUM_PARTIAL)
1341 ++count;
1342
1343 return count;
1344 }
1345
1346 /*
1347 * Put one packet in ring for transmit.
1348 * A single packet can generate multiple list elements, and
1349 * the number of ring elements will probably be less than the number
1350 * of list elements used.
1351 */
1352 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1353 {
1354 struct sky2_port *sky2 = netdev_priv(dev);
1355 struct sky2_hw *hw = sky2->hw;
1356 struct sky2_tx_le *le = NULL;
1357 struct tx_ring_info *re;
1358 unsigned i, len;
1359 dma_addr_t mapping;
1360 u32 addr64;
1361 u16 mss;
1362 u8 ctrl;
1363
1364 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1365 return NETDEV_TX_BUSY;
1366
1367 if (unlikely(netif_msg_tx_queued(sky2)))
1368 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1369 dev->name, sky2->tx_prod, skb->len);
1370
1371 len = skb_headlen(skb);
1372 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1373 addr64 = high32(mapping);
1374
1375 /* Send high bits if changed or crosses boundary */
1376 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1377 le = get_tx_le(sky2);
1378 le->addr = cpu_to_le32(addr64);
1379 le->opcode = OP_ADDR64 | HW_OWNER;
1380 sky2->tx_addr64 = high32(mapping + len);
1381 }
1382
1383 /* Check for TCP Segmentation Offload */
1384 mss = skb_shinfo(skb)->gso_size;
1385 if (mss != 0) {
1386 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1387 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1388 mss += ETH_HLEN;
1389
1390 if (mss != sky2->tx_last_mss) {
1391 le = get_tx_le(sky2);
1392 le->addr = cpu_to_le32(mss);
1393 le->opcode = OP_LRGLEN | HW_OWNER;
1394 sky2->tx_last_mss = mss;
1395 }
1396 }
1397
1398 ctrl = 0;
1399 #ifdef SKY2_VLAN_TAG_USED
1400 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1401 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1402 if (!le) {
1403 le = get_tx_le(sky2);
1404 le->addr = 0;
1405 le->opcode = OP_VLAN|HW_OWNER;
1406 } else
1407 le->opcode |= OP_VLAN;
1408 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1409 ctrl |= INS_VLAN;
1410 }
1411 #endif
1412
1413 /* Handle TCP checksum offload */
1414 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1415 unsigned offset = skb->h.raw - skb->data;
1416 u32 tcpsum;
1417
1418 tcpsum = offset << 16; /* sum start */
1419 tcpsum |= offset + skb->csum_offset; /* sum write */
1420
1421 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1422 if (skb->nh.iph->protocol == IPPROTO_UDP)
1423 ctrl |= UDPTCP;
1424
1425 if (tcpsum != sky2->tx_tcpsum) {
1426 sky2->tx_tcpsum = tcpsum;
1427
1428 le = get_tx_le(sky2);
1429 le->addr = cpu_to_le32(tcpsum);
1430 le->length = 0; /* initial checksum value */
1431 le->ctrl = 1; /* one packet */
1432 le->opcode = OP_TCPLISW | HW_OWNER;
1433 }
1434 }
1435
1436 le = get_tx_le(sky2);
1437 le->addr = cpu_to_le32((u32) mapping);
1438 le->length = cpu_to_le16(len);
1439 le->ctrl = ctrl;
1440 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1441
1442 re = tx_le_re(sky2, le);
1443 re->skb = skb;
1444 pci_unmap_addr_set(re, mapaddr, mapping);
1445 pci_unmap_len_set(re, maplen, len);
1446
1447 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1448 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1449
1450 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1451 frag->size, PCI_DMA_TODEVICE);
1452 addr64 = high32(mapping);
1453 if (addr64 != sky2->tx_addr64) {
1454 le = get_tx_le(sky2);
1455 le->addr = cpu_to_le32(addr64);
1456 le->ctrl = 0;
1457 le->opcode = OP_ADDR64 | HW_OWNER;
1458 sky2->tx_addr64 = addr64;
1459 }
1460
1461 le = get_tx_le(sky2);
1462 le->addr = cpu_to_le32((u32) mapping);
1463 le->length = cpu_to_le16(frag->size);
1464 le->ctrl = ctrl;
1465 le->opcode = OP_BUFFER | HW_OWNER;
1466
1467 re = tx_le_re(sky2, le);
1468 re->skb = skb;
1469 pci_unmap_addr_set(re, mapaddr, mapping);
1470 pci_unmap_len_set(re, maplen, frag->size);
1471 }
1472
1473 le->ctrl |= EOP;
1474
1475 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1476 netif_stop_queue(dev);
1477
1478 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1479
1480 dev->trans_start = jiffies;
1481 return NETDEV_TX_OK;
1482 }
1483
1484 /*
1485 * Free ring elements from starting at tx_cons until "done"
1486 *
1487 * NB: the hardware will tell us about partial completion of multi-part
1488 * buffers so make sure not to free skb to early.
1489 */
1490 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1491 {
1492 struct net_device *dev = sky2->netdev;
1493 struct pci_dev *pdev = sky2->hw->pdev;
1494 unsigned idx;
1495
1496 BUG_ON(done >= TX_RING_SIZE);
1497
1498 for (idx = sky2->tx_cons; idx != done;
1499 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1500 struct sky2_tx_le *le = sky2->tx_le + idx;
1501 struct tx_ring_info *re = sky2->tx_ring + idx;
1502
1503 switch(le->opcode & ~HW_OWNER) {
1504 case OP_LARGESEND:
1505 case OP_PACKET:
1506 pci_unmap_single(pdev,
1507 pci_unmap_addr(re, mapaddr),
1508 pci_unmap_len(re, maplen),
1509 PCI_DMA_TODEVICE);
1510 break;
1511 case OP_BUFFER:
1512 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1513 pci_unmap_len(re, maplen),
1514 PCI_DMA_TODEVICE);
1515 break;
1516 }
1517
1518 if (le->ctrl & EOP) {
1519 if (unlikely(netif_msg_tx_done(sky2)))
1520 printk(KERN_DEBUG "%s: tx done %u\n",
1521 dev->name, idx);
1522 sky2->net_stats.tx_packets++;
1523 sky2->net_stats.tx_bytes += re->skb->len;
1524
1525 dev_kfree_skb_any(re->skb);
1526 }
1527
1528 le->opcode = 0; /* paranoia */
1529 }
1530
1531 sky2->tx_cons = idx;
1532 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1533 netif_wake_queue(dev);
1534 }
1535
1536 /* Cleanup all untransmitted buffers, assume transmitter not running */
1537 static void sky2_tx_clean(struct net_device *dev)
1538 {
1539 struct sky2_port *sky2 = netdev_priv(dev);
1540
1541 netif_tx_lock_bh(dev);
1542 sky2_tx_complete(sky2, sky2->tx_prod);
1543 netif_tx_unlock_bh(dev);
1544 }
1545
1546 /* Network shutdown */
1547 static int sky2_down(struct net_device *dev)
1548 {
1549 struct sky2_port *sky2 = netdev_priv(dev);
1550 struct sky2_hw *hw = sky2->hw;
1551 unsigned port = sky2->port;
1552 u16 ctrl;
1553 u32 imask;
1554
1555 /* Never really got started! */
1556 if (!sky2->tx_le)
1557 return 0;
1558
1559 if (netif_msg_ifdown(sky2))
1560 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1561
1562 /* Stop more packets from being queued */
1563 netif_stop_queue(dev);
1564
1565 /* Disable port IRQ */
1566 imask = sky2_read32(hw, B0_IMSK);
1567 imask &= ~portirq_msk[port];
1568 sky2_write32(hw, B0_IMSK, imask);
1569
1570 /*
1571 * Both ports share the NAPI poll on port 0, so if necessary undo the
1572 * the disable that is done in dev_close.
1573 */
1574 if (sky2->port == 0 && hw->ports > 1)
1575 netif_poll_enable(dev);
1576
1577 sky2_gmac_reset(hw, port);
1578
1579 /* Stop transmitter */
1580 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1581 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1582
1583 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1584 RB_RST_SET | RB_DIS_OP_MD);
1585
1586 /* WA for dev. #4.209 */
1587 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1588 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1589 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1590 sky2->speed != SPEED_1000 ?
1591 TX_STFW_ENA : TX_STFW_DIS);
1592
1593 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1594 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1595 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1596
1597 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1598
1599 /* Workaround shared GMAC reset */
1600 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1601 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1603
1604 /* Disable Force Sync bit and Enable Alloc bit */
1605 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1606 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1607
1608 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1609 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1610 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1611
1612 /* Reset the PCI FIFO of the async Tx queue */
1613 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1614 BMU_RST_SET | BMU_FIFO_RST);
1615
1616 /* Reset the Tx prefetch units */
1617 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1618 PREF_UNIT_RST_SET);
1619
1620 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1621
1622 sky2_rx_stop(sky2);
1623
1624 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1625 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1626
1627 sky2_phy_power(hw, port, 0);
1628
1629 /* turn off LED's */
1630 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1631
1632 synchronize_irq(hw->pdev->irq);
1633
1634 sky2_tx_clean(dev);
1635 sky2_rx_clean(sky2);
1636
1637 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1638 sky2->rx_le, sky2->rx_le_map);
1639 kfree(sky2->rx_ring);
1640
1641 pci_free_consistent(hw->pdev,
1642 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1643 sky2->tx_le, sky2->tx_le_map);
1644 kfree(sky2->tx_ring);
1645
1646 sky2->tx_le = NULL;
1647 sky2->rx_le = NULL;
1648
1649 sky2->rx_ring = NULL;
1650 sky2->tx_ring = NULL;
1651
1652 return 0;
1653 }
1654
1655 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1656 {
1657 if (!sky2_is_copper(hw))
1658 return SPEED_1000;
1659
1660 if (hw->chip_id == CHIP_ID_YUKON_FE)
1661 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1662
1663 switch (aux & PHY_M_PS_SPEED_MSK) {
1664 case PHY_M_PS_SPEED_1000:
1665 return SPEED_1000;
1666 case PHY_M_PS_SPEED_100:
1667 return SPEED_100;
1668 default:
1669 return SPEED_10;
1670 }
1671 }
1672
1673 static void sky2_link_up(struct sky2_port *sky2)
1674 {
1675 struct sky2_hw *hw = sky2->hw;
1676 unsigned port = sky2->port;
1677 u16 reg;
1678 static const char *fc_name[] = {
1679 [FC_NONE] = "none",
1680 [FC_TX] = "tx",
1681 [FC_RX] = "rx",
1682 [FC_BOTH] = "both",
1683 };
1684
1685 /* enable Rx/Tx */
1686 reg = gma_read16(hw, port, GM_GP_CTRL);
1687 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1688 gma_write16(hw, port, GM_GP_CTRL, reg);
1689
1690 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1691
1692 netif_carrier_on(sky2->netdev);
1693 netif_wake_queue(sky2->netdev);
1694
1695 /* Turn on link LED */
1696 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1697 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1698
1699 if (hw->chip_id == CHIP_ID_YUKON_XL
1700 || hw->chip_id == CHIP_ID_YUKON_EC_U
1701 || hw->chip_id == CHIP_ID_YUKON_EX) {
1702 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1703 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1704
1705 switch(sky2->speed) {
1706 case SPEED_10:
1707 led |= PHY_M_LEDC_INIT_CTRL(7);
1708 break;
1709
1710 case SPEED_100:
1711 led |= PHY_M_LEDC_STA1_CTRL(7);
1712 break;
1713
1714 case SPEED_1000:
1715 led |= PHY_M_LEDC_STA0_CTRL(7);
1716 break;
1717 }
1718
1719 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1720 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1721 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1722 }
1723
1724 if (netif_msg_link(sky2))
1725 printk(KERN_INFO PFX
1726 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1727 sky2->netdev->name, sky2->speed,
1728 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1729 fc_name[sky2->flow_status]);
1730 }
1731
1732 static void sky2_link_down(struct sky2_port *sky2)
1733 {
1734 struct sky2_hw *hw = sky2->hw;
1735 unsigned port = sky2->port;
1736 u16 reg;
1737
1738 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1739
1740 reg = gma_read16(hw, port, GM_GP_CTRL);
1741 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1742 gma_write16(hw, port, GM_GP_CTRL, reg);
1743
1744 netif_carrier_off(sky2->netdev);
1745 netif_stop_queue(sky2->netdev);
1746
1747 /* Turn on link LED */
1748 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1749
1750 if (netif_msg_link(sky2))
1751 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1752
1753 sky2_phy_init(hw, port);
1754 }
1755
1756 static enum flow_control sky2_flow(int rx, int tx)
1757 {
1758 if (rx)
1759 return tx ? FC_BOTH : FC_RX;
1760 else
1761 return tx ? FC_TX : FC_NONE;
1762 }
1763
1764 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1765 {
1766 struct sky2_hw *hw = sky2->hw;
1767 unsigned port = sky2->port;
1768 u16 advert, lpa;
1769
1770 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1771 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1772 if (lpa & PHY_M_AN_RF) {
1773 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1774 return -1;
1775 }
1776
1777 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1778 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1779 sky2->netdev->name);
1780 return -1;
1781 }
1782
1783 sky2->speed = sky2_phy_speed(hw, aux);
1784 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1785
1786 /* Since the pause result bits seem to in different positions on
1787 * different chips. look at registers.
1788 */
1789 if (!sky2_is_copper(hw)) {
1790 /* Shift for bits in fiber PHY */
1791 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1792 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1793
1794 if (advert & ADVERTISE_1000XPAUSE)
1795 advert |= ADVERTISE_PAUSE_CAP;
1796 if (advert & ADVERTISE_1000XPSE_ASYM)
1797 advert |= ADVERTISE_PAUSE_ASYM;
1798 if (lpa & LPA_1000XPAUSE)
1799 lpa |= LPA_PAUSE_CAP;
1800 if (lpa & LPA_1000XPAUSE_ASYM)
1801 lpa |= LPA_PAUSE_ASYM;
1802 }
1803
1804 sky2->flow_status = FC_NONE;
1805 if (advert & ADVERTISE_PAUSE_CAP) {
1806 if (lpa & LPA_PAUSE_CAP)
1807 sky2->flow_status = FC_BOTH;
1808 else if (advert & ADVERTISE_PAUSE_ASYM)
1809 sky2->flow_status = FC_RX;
1810 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1811 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1812 sky2->flow_status = FC_TX;
1813 }
1814
1815 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1816 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1817 sky2->flow_status = FC_NONE;
1818
1819 if (sky2->flow_status & FC_TX)
1820 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1821 else
1822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1823
1824 return 0;
1825 }
1826
1827 /* Interrupt from PHY */
1828 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1829 {
1830 struct net_device *dev = hw->dev[port];
1831 struct sky2_port *sky2 = netdev_priv(dev);
1832 u16 istatus, phystat;
1833
1834 if (!netif_running(dev))
1835 return;
1836
1837 spin_lock(&sky2->phy_lock);
1838 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1839 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1840
1841 if (netif_msg_intr(sky2))
1842 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1843 sky2->netdev->name, istatus, phystat);
1844
1845 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1846 if (sky2_autoneg_done(sky2, phystat) == 0)
1847 sky2_link_up(sky2);
1848 goto out;
1849 }
1850
1851 if (istatus & PHY_M_IS_LSP_CHANGE)
1852 sky2->speed = sky2_phy_speed(hw, phystat);
1853
1854 if (istatus & PHY_M_IS_DUP_CHANGE)
1855 sky2->duplex =
1856 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1857
1858 if (istatus & PHY_M_IS_LST_CHANGE) {
1859 if (phystat & PHY_M_PS_LINK_UP)
1860 sky2_link_up(sky2);
1861 else
1862 sky2_link_down(sky2);
1863 }
1864 out:
1865 spin_unlock(&sky2->phy_lock);
1866 }
1867
1868 /* Transmit timeout is only called if we are running, carrier is up
1869 * and tx queue is full (stopped).
1870 */
1871 static void sky2_tx_timeout(struct net_device *dev)
1872 {
1873 struct sky2_port *sky2 = netdev_priv(dev);
1874 struct sky2_hw *hw = sky2->hw;
1875
1876 if (netif_msg_timer(sky2))
1877 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1878
1879 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1880 dev->name, sky2->tx_cons, sky2->tx_prod,
1881 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1882 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1883
1884 /* can't restart safely under softirq */
1885 schedule_work(&hw->restart_work);
1886 }
1887
1888 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1889 {
1890 struct sky2_port *sky2 = netdev_priv(dev);
1891 struct sky2_hw *hw = sky2->hw;
1892 int err;
1893 u16 ctl, mode;
1894 u32 imask;
1895
1896 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1897 return -EINVAL;
1898
1899 /* TSO on Yukon Ultra and MTU > 1500 not supported */
1900 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1901 dev->features &= ~NETIF_F_TSO;
1902
1903 if (!netif_running(dev)) {
1904 dev->mtu = new_mtu;
1905 return 0;
1906 }
1907
1908 imask = sky2_read32(hw, B0_IMSK);
1909 sky2_write32(hw, B0_IMSK, 0);
1910
1911 dev->trans_start = jiffies; /* prevent tx timeout */
1912 netif_stop_queue(dev);
1913 netif_poll_disable(hw->dev[0]);
1914
1915 synchronize_irq(hw->pdev->irq);
1916
1917 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1918 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1919 sky2_rx_stop(sky2);
1920 sky2_rx_clean(sky2);
1921
1922 dev->mtu = new_mtu;
1923
1924 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1925 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1926
1927 if (dev->mtu > ETH_DATA_LEN)
1928 mode |= GM_SMOD_JUMBO_ENA;
1929
1930 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1931
1932 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1933
1934 err = sky2_rx_start(sky2);
1935 sky2_write32(hw, B0_IMSK, imask);
1936
1937 if (err)
1938 dev_close(dev);
1939 else {
1940 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1941
1942 netif_poll_enable(hw->dev[0]);
1943 netif_wake_queue(dev);
1944 }
1945
1946 return err;
1947 }
1948
1949 /* For small just reuse existing skb for next receive */
1950 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1951 const struct rx_ring_info *re,
1952 unsigned length)
1953 {
1954 struct sk_buff *skb;
1955
1956 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1957 if (likely(skb)) {
1958 skb_reserve(skb, 2);
1959 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1960 length, PCI_DMA_FROMDEVICE);
1961 memcpy(skb->data, re->skb->data, length);
1962 skb->ip_summed = re->skb->ip_summed;
1963 skb->csum = re->skb->csum;
1964 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1965 length, PCI_DMA_FROMDEVICE);
1966 re->skb->ip_summed = CHECKSUM_NONE;
1967 skb_put(skb, length);
1968 }
1969 return skb;
1970 }
1971
1972 /* Adjust length of skb with fragments to match received data */
1973 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1974 unsigned int length)
1975 {
1976 int i, num_frags;
1977 unsigned int size;
1978
1979 /* put header into skb */
1980 size = min(length, hdr_space);
1981 skb->tail += size;
1982 skb->len += size;
1983 length -= size;
1984
1985 num_frags = skb_shinfo(skb)->nr_frags;
1986 for (i = 0; i < num_frags; i++) {
1987 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1988
1989 if (length == 0) {
1990 /* don't need this page */
1991 __free_page(frag->page);
1992 --skb_shinfo(skb)->nr_frags;
1993 } else {
1994 size = min(length, (unsigned) PAGE_SIZE);
1995
1996 frag->size = size;
1997 skb->data_len += size;
1998 skb->truesize += size;
1999 skb->len += size;
2000 length -= size;
2001 }
2002 }
2003 }
2004
2005 /* Normal packet - take skb from ring element and put in a new one */
2006 static struct sk_buff *receive_new(struct sky2_port *sky2,
2007 struct rx_ring_info *re,
2008 unsigned int length)
2009 {
2010 struct sk_buff *skb, *nskb;
2011 unsigned hdr_space = sky2->rx_data_size;
2012
2013 pr_debug(PFX "receive new length=%d\n", length);
2014
2015 /* Don't be tricky about reusing pages (yet) */
2016 nskb = sky2_rx_alloc(sky2);
2017 if (unlikely(!nskb))
2018 return NULL;
2019
2020 skb = re->skb;
2021 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2022
2023 prefetch(skb->data);
2024 re->skb = nskb;
2025 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2026
2027 if (skb_shinfo(skb)->nr_frags)
2028 skb_put_frags(skb, hdr_space, length);
2029 else
2030 skb_put(skb, length);
2031 return skb;
2032 }
2033
2034 /*
2035 * Receive one packet.
2036 * For larger packets, get new buffer.
2037 */
2038 static struct sk_buff *sky2_receive(struct net_device *dev,
2039 u16 length, u32 status)
2040 {
2041 struct sky2_port *sky2 = netdev_priv(dev);
2042 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2043 struct sk_buff *skb = NULL;
2044
2045 if (unlikely(netif_msg_rx_status(sky2)))
2046 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2047 dev->name, sky2->rx_next, status, length);
2048
2049 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2050 prefetch(sky2->rx_ring + sky2->rx_next);
2051
2052 if (status & GMR_FS_ANY_ERR)
2053 goto error;
2054
2055 if (!(status & GMR_FS_RX_OK))
2056 goto resubmit;
2057
2058 if (length < copybreak)
2059 skb = receive_copy(sky2, re, length);
2060 else
2061 skb = receive_new(sky2, re, length);
2062 resubmit:
2063 sky2_rx_submit(sky2, re);
2064
2065 return skb;
2066
2067 error:
2068 ++sky2->net_stats.rx_errors;
2069 if (status & GMR_FS_RX_FF_OV) {
2070 sky2->net_stats.rx_over_errors++;
2071 goto resubmit;
2072 }
2073
2074 if (netif_msg_rx_err(sky2) && net_ratelimit())
2075 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2076 dev->name, status, length);
2077
2078 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2079 sky2->net_stats.rx_length_errors++;
2080 if (status & GMR_FS_FRAGMENT)
2081 sky2->net_stats.rx_frame_errors++;
2082 if (status & GMR_FS_CRC_ERR)
2083 sky2->net_stats.rx_crc_errors++;
2084
2085 goto resubmit;
2086 }
2087
2088 /* Transmit complete */
2089 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2090 {
2091 struct sky2_port *sky2 = netdev_priv(dev);
2092
2093 if (netif_running(dev)) {
2094 netif_tx_lock(dev);
2095 sky2_tx_complete(sky2, last);
2096 netif_tx_unlock(dev);
2097 }
2098 }
2099
2100 /* Process status response ring */
2101 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2102 {
2103 struct sky2_port *sky2;
2104 int work_done = 0;
2105 unsigned buf_write[2] = { 0, 0 };
2106 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2107
2108 rmb();
2109
2110 while (hw->st_idx != hwidx) {
2111 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2112 struct net_device *dev;
2113 struct sk_buff *skb;
2114 u32 status;
2115 u16 length;
2116
2117 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2118
2119 BUG_ON(le->link >= 2);
2120 dev = hw->dev[le->link];
2121
2122 sky2 = netdev_priv(dev);
2123 length = le16_to_cpu(le->length);
2124 status = le32_to_cpu(le->status);
2125
2126 switch (le->opcode & ~HW_OWNER) {
2127 case OP_RXSTAT:
2128 skb = sky2_receive(dev, length, status);
2129 if (!skb)
2130 goto force_update;
2131
2132 skb->protocol = eth_type_trans(skb, dev);
2133 sky2->net_stats.rx_packets++;
2134 sky2->net_stats.rx_bytes += skb->len;
2135 dev->last_rx = jiffies;
2136
2137 #ifdef SKY2_VLAN_TAG_USED
2138 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2139 vlan_hwaccel_receive_skb(skb,
2140 sky2->vlgrp,
2141 be16_to_cpu(sky2->rx_tag));
2142 } else
2143 #endif
2144 netif_receive_skb(skb);
2145
2146 /* Update receiver after 16 frames */
2147 if (++buf_write[le->link] == RX_BUF_WRITE) {
2148 force_update:
2149 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2150 buf_write[le->link] = 0;
2151 }
2152
2153 /* Stop after net poll weight */
2154 if (++work_done >= to_do)
2155 goto exit_loop;
2156 break;
2157
2158 #ifdef SKY2_VLAN_TAG_USED
2159 case OP_RXVLAN:
2160 sky2->rx_tag = length;
2161 break;
2162
2163 case OP_RXCHKSVLAN:
2164 sky2->rx_tag = length;
2165 /* fall through */
2166 #endif
2167 case OP_RXCHKS:
2168 if (!sky2->rx_csum)
2169 break;
2170
2171 /* Both checksum counters are programmed to start at
2172 * the same offset, so unless there is a problem they
2173 * should match. This failure is an early indication that
2174 * hardware receive checksumming won't work.
2175 */
2176 if (likely(status >> 16 == (status & 0xffff))) {
2177 skb = sky2->rx_ring[sky2->rx_next].skb;
2178 skb->ip_summed = CHECKSUM_COMPLETE;
2179 skb->csum = status & 0xffff;
2180 } else {
2181 printk(KERN_NOTICE PFX "%s: hardware receive "
2182 "checksum problem (status = %#x)\n",
2183 dev->name, status);
2184 sky2->rx_csum = 0;
2185 sky2_write32(sky2->hw,
2186 Q_ADDR(rxqaddr[le->link], Q_CSR),
2187 BMU_DIS_RX_CHKSUM);
2188 }
2189 break;
2190
2191 case OP_TXINDEXLE:
2192 /* TX index reports status for both ports */
2193 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2194 sky2_tx_done(hw->dev[0], status & 0xfff);
2195 if (hw->dev[1])
2196 sky2_tx_done(hw->dev[1],
2197 ((status >> 24) & 0xff)
2198 | (u16)(length & 0xf) << 8);
2199 break;
2200
2201 default:
2202 if (net_ratelimit())
2203 printk(KERN_WARNING PFX
2204 "unknown status opcode 0x%x\n", le->opcode);
2205 goto exit_loop;
2206 }
2207 }
2208
2209 /* Fully processed status ring so clear irq */
2210 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2211
2212 exit_loop:
2213 if (buf_write[0]) {
2214 sky2 = netdev_priv(hw->dev[0]);
2215 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2216 }
2217
2218 if (buf_write[1]) {
2219 sky2 = netdev_priv(hw->dev[1]);
2220 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2221 }
2222
2223 return work_done;
2224 }
2225
2226 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2227 {
2228 struct net_device *dev = hw->dev[port];
2229
2230 if (net_ratelimit())
2231 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2232 dev->name, status);
2233
2234 if (status & Y2_IS_PAR_RD1) {
2235 if (net_ratelimit())
2236 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2237 dev->name);
2238 /* Clear IRQ */
2239 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2240 }
2241
2242 if (status & Y2_IS_PAR_WR1) {
2243 if (net_ratelimit())
2244 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2245 dev->name);
2246
2247 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2248 }
2249
2250 if (status & Y2_IS_PAR_MAC1) {
2251 if (net_ratelimit())
2252 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2253 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2254 }
2255
2256 if (status & Y2_IS_PAR_RX1) {
2257 if (net_ratelimit())
2258 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2259 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2260 }
2261
2262 if (status & Y2_IS_TCP_TXA1) {
2263 if (net_ratelimit())
2264 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2265 dev->name);
2266 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2267 }
2268 }
2269
2270 static void sky2_hw_intr(struct sky2_hw *hw)
2271 {
2272 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2273
2274 if (status & Y2_IS_TIST_OV)
2275 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2276
2277 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2278 u16 pci_err;
2279
2280 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2281 if (net_ratelimit())
2282 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2283 pci_err);
2284
2285 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2286 sky2_pci_write16(hw, PCI_STATUS,
2287 pci_err | PCI_STATUS_ERROR_BITS);
2288 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2289 }
2290
2291 if (status & Y2_IS_PCI_EXP) {
2292 /* PCI-Express uncorrectable Error occurred */
2293 u32 pex_err;
2294
2295 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2296
2297 if (net_ratelimit())
2298 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2299 pex_err);
2300
2301 /* clear the interrupt */
2302 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2303 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2304 0xffffffffUL);
2305 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2306
2307 if (pex_err & PEX_FATAL_ERRORS) {
2308 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2309 hwmsk &= ~Y2_IS_PCI_EXP;
2310 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2311 }
2312 }
2313
2314 if (status & Y2_HWE_L1_MASK)
2315 sky2_hw_error(hw, 0, status);
2316 status >>= 8;
2317 if (status & Y2_HWE_L1_MASK)
2318 sky2_hw_error(hw, 1, status);
2319 }
2320
2321 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2322 {
2323 struct net_device *dev = hw->dev[port];
2324 struct sky2_port *sky2 = netdev_priv(dev);
2325 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2326
2327 if (netif_msg_intr(sky2))
2328 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2329 dev->name, status);
2330
2331 if (status & GM_IS_RX_FF_OR) {
2332 ++sky2->net_stats.rx_fifo_errors;
2333 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2334 }
2335
2336 if (status & GM_IS_TX_FF_UR) {
2337 ++sky2->net_stats.tx_fifo_errors;
2338 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2339 }
2340 }
2341
2342 /* This should never happen it is a fatal situation */
2343 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2344 const char *rxtx, u32 mask)
2345 {
2346 struct net_device *dev = hw->dev[port];
2347 struct sky2_port *sky2 = netdev_priv(dev);
2348 u32 imask;
2349
2350 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2351 dev ? dev->name : "<not registered>", rxtx);
2352
2353 imask = sky2_read32(hw, B0_IMSK);
2354 imask &= ~mask;
2355 sky2_write32(hw, B0_IMSK, imask);
2356
2357 if (dev) {
2358 spin_lock(&sky2->phy_lock);
2359 sky2_link_down(sky2);
2360 spin_unlock(&sky2->phy_lock);
2361 }
2362 }
2363
2364 /* If idle then force a fake soft NAPI poll once a second
2365 * to work around cases where sharing an edge triggered interrupt.
2366 */
2367 static inline void sky2_idle_start(struct sky2_hw *hw)
2368 {
2369 if (idle_timeout > 0)
2370 mod_timer(&hw->idle_timer,
2371 jiffies + msecs_to_jiffies(idle_timeout));
2372 }
2373
2374 static void sky2_idle(unsigned long arg)
2375 {
2376 struct sky2_hw *hw = (struct sky2_hw *) arg;
2377 struct net_device *dev = hw->dev[0];
2378
2379 if (__netif_rx_schedule_prep(dev))
2380 __netif_rx_schedule(dev);
2381
2382 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2383 }
2384
2385
2386 static int sky2_poll(struct net_device *dev0, int *budget)
2387 {
2388 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2389 int work_limit = min(dev0->quota, *budget);
2390 int work_done = 0;
2391 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2392
2393 if (status & Y2_IS_HW_ERR)
2394 sky2_hw_intr(hw);
2395
2396 if (status & Y2_IS_IRQ_PHY1)
2397 sky2_phy_intr(hw, 0);
2398
2399 if (status & Y2_IS_IRQ_PHY2)
2400 sky2_phy_intr(hw, 1);
2401
2402 if (status & Y2_IS_IRQ_MAC1)
2403 sky2_mac_intr(hw, 0);
2404
2405 if (status & Y2_IS_IRQ_MAC2)
2406 sky2_mac_intr(hw, 1);
2407
2408 if (status & Y2_IS_CHK_RX1)
2409 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2410
2411 if (status & Y2_IS_CHK_RX2)
2412 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2413
2414 if (status & Y2_IS_CHK_TXA1)
2415 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2416
2417 if (status & Y2_IS_CHK_TXA2)
2418 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2419
2420 work_done = sky2_status_intr(hw, work_limit);
2421 if (work_done < work_limit) {
2422 netif_rx_complete(dev0);
2423
2424 sky2_read32(hw, B0_Y2_SP_LISR);
2425 return 0;
2426 } else {
2427 *budget -= work_done;
2428 dev0->quota -= work_done;
2429 return 1;
2430 }
2431 }
2432
2433 static irqreturn_t sky2_intr(int irq, void *dev_id)
2434 {
2435 struct sky2_hw *hw = dev_id;
2436 struct net_device *dev0 = hw->dev[0];
2437 u32 status;
2438
2439 /* Reading this mask interrupts as side effect */
2440 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2441 if (status == 0 || status == ~0)
2442 return IRQ_NONE;
2443
2444 prefetch(&hw->st_le[hw->st_idx]);
2445 if (likely(__netif_rx_schedule_prep(dev0)))
2446 __netif_rx_schedule(dev0);
2447
2448 return IRQ_HANDLED;
2449 }
2450
2451 #ifdef CONFIG_NET_POLL_CONTROLLER
2452 static void sky2_netpoll(struct net_device *dev)
2453 {
2454 struct sky2_port *sky2 = netdev_priv(dev);
2455 struct net_device *dev0 = sky2->hw->dev[0];
2456
2457 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2458 __netif_rx_schedule(dev0);
2459 }
2460 #endif
2461
2462 /* Chip internal frequency for clock calculations */
2463 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2464 {
2465 switch (hw->chip_id) {
2466 case CHIP_ID_YUKON_EC:
2467 case CHIP_ID_YUKON_EC_U:
2468 case CHIP_ID_YUKON_EX:
2469 return 125; /* 125 Mhz */
2470 case CHIP_ID_YUKON_FE:
2471 return 100; /* 100 Mhz */
2472 default: /* YUKON_XL */
2473 return 156; /* 156 Mhz */
2474 }
2475 }
2476
2477 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2478 {
2479 return sky2_mhz(hw) * us;
2480 }
2481
2482 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2483 {
2484 return clk / sky2_mhz(hw);
2485 }
2486
2487
2488 static int __devinit sky2_init(struct sky2_hw *hw)
2489 {
2490 u8 t8;
2491
2492 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2493
2494 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2495 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2496 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2497 hw->chip_id);
2498 return -EOPNOTSUPP;
2499 }
2500
2501 if (hw->chip_id == CHIP_ID_YUKON_EX)
2502 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2503 "Please report success or failure to <netdev@vger.kernel.org>\n");
2504
2505 /* Make sure and enable all clocks */
2506 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2507 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2508
2509 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2510
2511 /* This rev is really old, and requires untested workarounds */
2512 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2513 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2514 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2515 hw->chip_id, hw->chip_rev);
2516 return -EOPNOTSUPP;
2517 }
2518
2519 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2520 hw->ports = 1;
2521 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2522 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2523 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2524 ++hw->ports;
2525 }
2526
2527 return 0;
2528 }
2529
2530 static void sky2_reset(struct sky2_hw *hw)
2531 {
2532 u16 status;
2533 int i;
2534
2535 /* disable ASF */
2536 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2537 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2538 status = sky2_read16(hw, HCU_CCSR);
2539 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2540 HCU_CCSR_UC_STATE_MSK);
2541 sky2_write16(hw, HCU_CCSR, status);
2542 } else
2543 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2544 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2545 }
2546
2547 /* do a SW reset */
2548 sky2_write8(hw, B0_CTST, CS_RST_SET);
2549 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2550
2551 /* clear PCI errors, if any */
2552 status = sky2_pci_read16(hw, PCI_STATUS);
2553
2554 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2555 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2556
2557
2558 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2559
2560 /* clear any PEX errors */
2561 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2562 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2563
2564
2565 sky2_power_on(hw);
2566
2567 for (i = 0; i < hw->ports; i++) {
2568 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2569 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2570 }
2571
2572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2573
2574 /* Clear I2C IRQ noise */
2575 sky2_write32(hw, B2_I2C_IRQ, 1);
2576
2577 /* turn off hardware timer (unused) */
2578 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2579 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2580
2581 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2582
2583 /* Turn off descriptor polling */
2584 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2585
2586 /* Turn off receive timestamp */
2587 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2588 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2589
2590 /* enable the Tx Arbiters */
2591 for (i = 0; i < hw->ports; i++)
2592 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2593
2594 /* Initialize ram interface */
2595 for (i = 0; i < hw->ports; i++) {
2596 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2597
2598 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2599 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2600 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2601 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2602 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2603 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2604 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2605 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2607 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2610 }
2611
2612 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2613
2614 for (i = 0; i < hw->ports; i++)
2615 sky2_gmac_reset(hw, i);
2616
2617 memset(hw->st_le, 0, STATUS_LE_BYTES);
2618 hw->st_idx = 0;
2619
2620 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2621 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2622
2623 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2624 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2625
2626 /* Set the list last index */
2627 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2628
2629 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2630 sky2_write8(hw, STAT_FIFO_WM, 16);
2631
2632 /* set Status-FIFO ISR watermark */
2633 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2634 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2635 else
2636 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2637
2638 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2639 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2640 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2641
2642 /* enable status unit */
2643 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2644
2645 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2646 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2647 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2648 }
2649
2650 static void sky2_restart(struct work_struct *work)
2651 {
2652 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2653 struct net_device *dev;
2654 int i, err;
2655
2656 dev_dbg(&hw->pdev->dev, "restarting\n");
2657
2658 del_timer_sync(&hw->idle_timer);
2659
2660 rtnl_lock();
2661 sky2_write32(hw, B0_IMSK, 0);
2662 sky2_read32(hw, B0_IMSK);
2663
2664 netif_poll_disable(hw->dev[0]);
2665
2666 for (i = 0; i < hw->ports; i++) {
2667 dev = hw->dev[i];
2668 if (netif_running(dev))
2669 sky2_down(dev);
2670 }
2671
2672 sky2_reset(hw);
2673 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2674 netif_poll_enable(hw->dev[0]);
2675
2676 for (i = 0; i < hw->ports; i++) {
2677 dev = hw->dev[i];
2678 if (netif_running(dev)) {
2679 err = sky2_up(dev);
2680 if (err) {
2681 printk(KERN_INFO PFX "%s: could not restart %d\n",
2682 dev->name, err);
2683 dev_close(dev);
2684 }
2685 }
2686 }
2687
2688 sky2_idle_start(hw);
2689
2690 rtnl_unlock();
2691 }
2692
2693 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2694 {
2695 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2696 }
2697
2698 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2699 {
2700 const struct sky2_port *sky2 = netdev_priv(dev);
2701
2702 wol->supported = sky2_wol_supported(sky2->hw);
2703 wol->wolopts = sky2->wol;
2704 }
2705
2706 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2707 {
2708 struct sky2_port *sky2 = netdev_priv(dev);
2709 struct sky2_hw *hw = sky2->hw;
2710
2711 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2712 return -EOPNOTSUPP;
2713
2714 sky2->wol = wol->wolopts;
2715
2716 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2717 sky2_write32(hw, B0_CTST, sky2->wol
2718 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2719
2720 if (!netif_running(dev))
2721 sky2_wol_init(sky2);
2722 return 0;
2723 }
2724
2725 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2726 {
2727 if (sky2_is_copper(hw)) {
2728 u32 modes = SUPPORTED_10baseT_Half
2729 | SUPPORTED_10baseT_Full
2730 | SUPPORTED_100baseT_Half
2731 | SUPPORTED_100baseT_Full
2732 | SUPPORTED_Autoneg | SUPPORTED_TP;
2733
2734 if (hw->chip_id != CHIP_ID_YUKON_FE)
2735 modes |= SUPPORTED_1000baseT_Half
2736 | SUPPORTED_1000baseT_Full;
2737 return modes;
2738 } else
2739 return SUPPORTED_1000baseT_Half
2740 | SUPPORTED_1000baseT_Full
2741 | SUPPORTED_Autoneg
2742 | SUPPORTED_FIBRE;
2743 }
2744
2745 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2746 {
2747 struct sky2_port *sky2 = netdev_priv(dev);
2748 struct sky2_hw *hw = sky2->hw;
2749
2750 ecmd->transceiver = XCVR_INTERNAL;
2751 ecmd->supported = sky2_supported_modes(hw);
2752 ecmd->phy_address = PHY_ADDR_MARV;
2753 if (sky2_is_copper(hw)) {
2754 ecmd->supported = SUPPORTED_10baseT_Half
2755 | SUPPORTED_10baseT_Full
2756 | SUPPORTED_100baseT_Half
2757 | SUPPORTED_100baseT_Full
2758 | SUPPORTED_1000baseT_Half
2759 | SUPPORTED_1000baseT_Full
2760 | SUPPORTED_Autoneg | SUPPORTED_TP;
2761 ecmd->port = PORT_TP;
2762 ecmd->speed = sky2->speed;
2763 } else {
2764 ecmd->speed = SPEED_1000;
2765 ecmd->port = PORT_FIBRE;
2766 }
2767
2768 ecmd->advertising = sky2->advertising;
2769 ecmd->autoneg = sky2->autoneg;
2770 ecmd->duplex = sky2->duplex;
2771 return 0;
2772 }
2773
2774 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2775 {
2776 struct sky2_port *sky2 = netdev_priv(dev);
2777 const struct sky2_hw *hw = sky2->hw;
2778 u32 supported = sky2_supported_modes(hw);
2779
2780 if (ecmd->autoneg == AUTONEG_ENABLE) {
2781 ecmd->advertising = supported;
2782 sky2->duplex = -1;
2783 sky2->speed = -1;
2784 } else {
2785 u32 setting;
2786
2787 switch (ecmd->speed) {
2788 case SPEED_1000:
2789 if (ecmd->duplex == DUPLEX_FULL)
2790 setting = SUPPORTED_1000baseT_Full;
2791 else if (ecmd->duplex == DUPLEX_HALF)
2792 setting = SUPPORTED_1000baseT_Half;
2793 else
2794 return -EINVAL;
2795 break;
2796 case SPEED_100:
2797 if (ecmd->duplex == DUPLEX_FULL)
2798 setting = SUPPORTED_100baseT_Full;
2799 else if (ecmd->duplex == DUPLEX_HALF)
2800 setting = SUPPORTED_100baseT_Half;
2801 else
2802 return -EINVAL;
2803 break;
2804
2805 case SPEED_10:
2806 if (ecmd->duplex == DUPLEX_FULL)
2807 setting = SUPPORTED_10baseT_Full;
2808 else if (ecmd->duplex == DUPLEX_HALF)
2809 setting = SUPPORTED_10baseT_Half;
2810 else
2811 return -EINVAL;
2812 break;
2813 default:
2814 return -EINVAL;
2815 }
2816
2817 if ((setting & supported) == 0)
2818 return -EINVAL;
2819
2820 sky2->speed = ecmd->speed;
2821 sky2->duplex = ecmd->duplex;
2822 }
2823
2824 sky2->autoneg = ecmd->autoneg;
2825 sky2->advertising = ecmd->advertising;
2826
2827 if (netif_running(dev))
2828 sky2_phy_reinit(sky2);
2829
2830 return 0;
2831 }
2832
2833 static void sky2_get_drvinfo(struct net_device *dev,
2834 struct ethtool_drvinfo *info)
2835 {
2836 struct sky2_port *sky2 = netdev_priv(dev);
2837
2838 strcpy(info->driver, DRV_NAME);
2839 strcpy(info->version, DRV_VERSION);
2840 strcpy(info->fw_version, "N/A");
2841 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2842 }
2843
2844 static const struct sky2_stat {
2845 char name[ETH_GSTRING_LEN];
2846 u16 offset;
2847 } sky2_stats[] = {
2848 { "tx_bytes", GM_TXO_OK_HI },
2849 { "rx_bytes", GM_RXO_OK_HI },
2850 { "tx_broadcast", GM_TXF_BC_OK },
2851 { "rx_broadcast", GM_RXF_BC_OK },
2852 { "tx_multicast", GM_TXF_MC_OK },
2853 { "rx_multicast", GM_RXF_MC_OK },
2854 { "tx_unicast", GM_TXF_UC_OK },
2855 { "rx_unicast", GM_RXF_UC_OK },
2856 { "tx_mac_pause", GM_TXF_MPAUSE },
2857 { "rx_mac_pause", GM_RXF_MPAUSE },
2858 { "collisions", GM_TXF_COL },
2859 { "late_collision",GM_TXF_LAT_COL },
2860 { "aborted", GM_TXF_ABO_COL },
2861 { "single_collisions", GM_TXF_SNG_COL },
2862 { "multi_collisions", GM_TXF_MUL_COL },
2863
2864 { "rx_short", GM_RXF_SHT },
2865 { "rx_runt", GM_RXE_FRAG },
2866 { "rx_64_byte_packets", GM_RXF_64B },
2867 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2868 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2869 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2870 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2871 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2872 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2873 { "rx_too_long", GM_RXF_LNG_ERR },
2874 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2875 { "rx_jabber", GM_RXF_JAB_PKT },
2876 { "rx_fcs_error", GM_RXF_FCS_ERR },
2877
2878 { "tx_64_byte_packets", GM_TXF_64B },
2879 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2880 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2881 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2882 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2883 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2884 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2885 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2886 };
2887
2888 static u32 sky2_get_rx_csum(struct net_device *dev)
2889 {
2890 struct sky2_port *sky2 = netdev_priv(dev);
2891
2892 return sky2->rx_csum;
2893 }
2894
2895 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2896 {
2897 struct sky2_port *sky2 = netdev_priv(dev);
2898
2899 sky2->rx_csum = data;
2900
2901 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2902 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2903
2904 return 0;
2905 }
2906
2907 static u32 sky2_get_msglevel(struct net_device *netdev)
2908 {
2909 struct sky2_port *sky2 = netdev_priv(netdev);
2910 return sky2->msg_enable;
2911 }
2912
2913 static int sky2_nway_reset(struct net_device *dev)
2914 {
2915 struct sky2_port *sky2 = netdev_priv(dev);
2916
2917 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2918 return -EINVAL;
2919
2920 sky2_phy_reinit(sky2);
2921
2922 return 0;
2923 }
2924
2925 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2926 {
2927 struct sky2_hw *hw = sky2->hw;
2928 unsigned port = sky2->port;
2929 int i;
2930
2931 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2932 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2933 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2934 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2935
2936 for (i = 2; i < count; i++)
2937 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2938 }
2939
2940 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2941 {
2942 struct sky2_port *sky2 = netdev_priv(netdev);
2943 sky2->msg_enable = value;
2944 }
2945
2946 static int sky2_get_stats_count(struct net_device *dev)
2947 {
2948 return ARRAY_SIZE(sky2_stats);
2949 }
2950
2951 static void sky2_get_ethtool_stats(struct net_device *dev,
2952 struct ethtool_stats *stats, u64 * data)
2953 {
2954 struct sky2_port *sky2 = netdev_priv(dev);
2955
2956 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2957 }
2958
2959 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2960 {
2961 int i;
2962
2963 switch (stringset) {
2964 case ETH_SS_STATS:
2965 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2966 memcpy(data + i * ETH_GSTRING_LEN,
2967 sky2_stats[i].name, ETH_GSTRING_LEN);
2968 break;
2969 }
2970 }
2971
2972 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2973 {
2974 struct sky2_port *sky2 = netdev_priv(dev);
2975 return &sky2->net_stats;
2976 }
2977
2978 static int sky2_set_mac_address(struct net_device *dev, void *p)
2979 {
2980 struct sky2_port *sky2 = netdev_priv(dev);
2981 struct sky2_hw *hw = sky2->hw;
2982 unsigned port = sky2->port;
2983 const struct sockaddr *addr = p;
2984
2985 if (!is_valid_ether_addr(addr->sa_data))
2986 return -EADDRNOTAVAIL;
2987
2988 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2989 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2990 dev->dev_addr, ETH_ALEN);
2991 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2992 dev->dev_addr, ETH_ALEN);
2993
2994 /* virtual address for data */
2995 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2996
2997 /* physical address: used for pause frames */
2998 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2999
3000 return 0;
3001 }
3002
3003 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3004 {
3005 u32 bit;
3006
3007 bit = ether_crc(ETH_ALEN, addr) & 63;
3008 filter[bit >> 3] |= 1 << (bit & 7);
3009 }
3010
3011 static void sky2_set_multicast(struct net_device *dev)
3012 {
3013 struct sky2_port *sky2 = netdev_priv(dev);
3014 struct sky2_hw *hw = sky2->hw;
3015 unsigned port = sky2->port;
3016 struct dev_mc_list *list = dev->mc_list;
3017 u16 reg;
3018 u8 filter[8];
3019 int rx_pause;
3020 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3021
3022 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3023 memset(filter, 0, sizeof(filter));
3024
3025 reg = gma_read16(hw, port, GM_RX_CTRL);
3026 reg |= GM_RXCR_UCF_ENA;
3027
3028 if (dev->flags & IFF_PROMISC) /* promiscuous */
3029 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3030 else if (dev->flags & IFF_ALLMULTI)
3031 memset(filter, 0xff, sizeof(filter));
3032 else if (dev->mc_count == 0 && !rx_pause)
3033 reg &= ~GM_RXCR_MCF_ENA;
3034 else {
3035 int i;
3036 reg |= GM_RXCR_MCF_ENA;
3037
3038 if (rx_pause)
3039 sky2_add_filter(filter, pause_mc_addr);
3040
3041 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3042 sky2_add_filter(filter, list->dmi_addr);
3043 }
3044
3045 gma_write16(hw, port, GM_MC_ADDR_H1,
3046 (u16) filter[0] | ((u16) filter[1] << 8));
3047 gma_write16(hw, port, GM_MC_ADDR_H2,
3048 (u16) filter[2] | ((u16) filter[3] << 8));
3049 gma_write16(hw, port, GM_MC_ADDR_H3,
3050 (u16) filter[4] | ((u16) filter[5] << 8));
3051 gma_write16(hw, port, GM_MC_ADDR_H4,
3052 (u16) filter[6] | ((u16) filter[7] << 8));
3053
3054 gma_write16(hw, port, GM_RX_CTRL, reg);
3055 }
3056
3057 /* Can have one global because blinking is controlled by
3058 * ethtool and that is always under RTNL mutex
3059 */
3060 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3061 {
3062 u16 pg;
3063
3064 switch (hw->chip_id) {
3065 case CHIP_ID_YUKON_XL:
3066 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3067 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3068 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3069 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3070 PHY_M_LEDC_INIT_CTRL(7) |
3071 PHY_M_LEDC_STA1_CTRL(7) |
3072 PHY_M_LEDC_STA0_CTRL(7))
3073 : 0);
3074
3075 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3076 break;
3077
3078 default:
3079 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3080 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3081 on ? PHY_M_LED_ALL : 0);
3082 }
3083 }
3084
3085 /* blink LED's for finding board */
3086 static int sky2_phys_id(struct net_device *dev, u32 data)
3087 {
3088 struct sky2_port *sky2 = netdev_priv(dev);
3089 struct sky2_hw *hw = sky2->hw;
3090 unsigned port = sky2->port;
3091 u16 ledctrl, ledover = 0;
3092 long ms;
3093 int interrupted;
3094 int onoff = 1;
3095
3096 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3097 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3098 else
3099 ms = data * 1000;
3100
3101 /* save initial values */
3102 spin_lock_bh(&sky2->phy_lock);
3103 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3104 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3105 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3106 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3107 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3108 } else {
3109 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3110 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3111 }
3112
3113 interrupted = 0;
3114 while (!interrupted && ms > 0) {
3115 sky2_led(hw, port, onoff);
3116 onoff = !onoff;
3117
3118 spin_unlock_bh(&sky2->phy_lock);
3119 interrupted = msleep_interruptible(250);
3120 spin_lock_bh(&sky2->phy_lock);
3121
3122 ms -= 250;
3123 }
3124
3125 /* resume regularly scheduled programming */
3126 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3127 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3128 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3129 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3130 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3131 } else {
3132 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3133 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3134 }
3135 spin_unlock_bh(&sky2->phy_lock);
3136
3137 return 0;
3138 }
3139
3140 static void sky2_get_pauseparam(struct net_device *dev,
3141 struct ethtool_pauseparam *ecmd)
3142 {
3143 struct sky2_port *sky2 = netdev_priv(dev);
3144
3145 switch (sky2->flow_mode) {
3146 case FC_NONE:
3147 ecmd->tx_pause = ecmd->rx_pause = 0;
3148 break;
3149 case FC_TX:
3150 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3151 break;
3152 case FC_RX:
3153 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3154 break;
3155 case FC_BOTH:
3156 ecmd->tx_pause = ecmd->rx_pause = 1;
3157 }
3158
3159 ecmd->autoneg = sky2->autoneg;
3160 }
3161
3162 static int sky2_set_pauseparam(struct net_device *dev,
3163 struct ethtool_pauseparam *ecmd)
3164 {
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166
3167 sky2->autoneg = ecmd->autoneg;
3168 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3169
3170 if (netif_running(dev))
3171 sky2_phy_reinit(sky2);
3172
3173 return 0;
3174 }
3175
3176 static int sky2_get_coalesce(struct net_device *dev,
3177 struct ethtool_coalesce *ecmd)
3178 {
3179 struct sky2_port *sky2 = netdev_priv(dev);
3180 struct sky2_hw *hw = sky2->hw;
3181
3182 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3183 ecmd->tx_coalesce_usecs = 0;
3184 else {
3185 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3186 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3187 }
3188 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3189
3190 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3191 ecmd->rx_coalesce_usecs = 0;
3192 else {
3193 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3194 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3195 }
3196 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3197
3198 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3199 ecmd->rx_coalesce_usecs_irq = 0;
3200 else {
3201 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3202 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3203 }
3204
3205 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3206
3207 return 0;
3208 }
3209
3210 /* Note: this affect both ports */
3211 static int sky2_set_coalesce(struct net_device *dev,
3212 struct ethtool_coalesce *ecmd)
3213 {
3214 struct sky2_port *sky2 = netdev_priv(dev);
3215 struct sky2_hw *hw = sky2->hw;
3216 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3217
3218 if (ecmd->tx_coalesce_usecs > tmax ||
3219 ecmd->rx_coalesce_usecs > tmax ||
3220 ecmd->rx_coalesce_usecs_irq > tmax)
3221 return -EINVAL;
3222
3223 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3224 return -EINVAL;
3225 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3226 return -EINVAL;
3227 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3228 return -EINVAL;
3229
3230 if (ecmd->tx_coalesce_usecs == 0)
3231 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3232 else {
3233 sky2_write32(hw, STAT_TX_TIMER_INI,
3234 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3235 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3236 }
3237 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3238
3239 if (ecmd->rx_coalesce_usecs == 0)
3240 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3241 else {
3242 sky2_write32(hw, STAT_LEV_TIMER_INI,
3243 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3244 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3245 }
3246 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3247
3248 if (ecmd->rx_coalesce_usecs_irq == 0)
3249 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3250 else {
3251 sky2_write32(hw, STAT_ISR_TIMER_INI,
3252 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3253 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3254 }
3255 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3256 return 0;
3257 }
3258
3259 static void sky2_get_ringparam(struct net_device *dev,
3260 struct ethtool_ringparam *ering)
3261 {
3262 struct sky2_port *sky2 = netdev_priv(dev);
3263
3264 ering->rx_max_pending = RX_MAX_PENDING;
3265 ering->rx_mini_max_pending = 0;
3266 ering->rx_jumbo_max_pending = 0;
3267 ering->tx_max_pending = TX_RING_SIZE - 1;
3268
3269 ering->rx_pending = sky2->rx_pending;
3270 ering->rx_mini_pending = 0;
3271 ering->rx_jumbo_pending = 0;
3272 ering->tx_pending = sky2->tx_pending;
3273 }
3274
3275 static int sky2_set_ringparam(struct net_device *dev,
3276 struct ethtool_ringparam *ering)
3277 {
3278 struct sky2_port *sky2 = netdev_priv(dev);
3279 int err = 0;
3280
3281 if (ering->rx_pending > RX_MAX_PENDING ||
3282 ering->rx_pending < 8 ||
3283 ering->tx_pending < MAX_SKB_TX_LE ||
3284 ering->tx_pending > TX_RING_SIZE - 1)
3285 return -EINVAL;
3286
3287 if (netif_running(dev))
3288 sky2_down(dev);
3289
3290 sky2->rx_pending = ering->rx_pending;
3291 sky2->tx_pending = ering->tx_pending;
3292
3293 if (netif_running(dev)) {
3294 err = sky2_up(dev);
3295 if (err)
3296 dev_close(dev);
3297 else
3298 sky2_set_multicast(dev);
3299 }
3300
3301 return err;
3302 }
3303
3304 static int sky2_get_regs_len(struct net_device *dev)
3305 {
3306 return 0x4000;
3307 }
3308
3309 /*
3310 * Returns copy of control register region
3311 * Note: access to the RAM address register set will cause timeouts.
3312 */
3313 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3314 void *p)
3315 {
3316 const struct sky2_port *sky2 = netdev_priv(dev);
3317 const void __iomem *io = sky2->hw->regs;
3318
3319 BUG_ON(regs->len < B3_RI_WTO_R1);
3320 regs->version = 1;
3321 memset(p, 0, regs->len);
3322
3323 memcpy_fromio(p, io, B3_RAM_ADDR);
3324
3325 memcpy_fromio(p + B3_RI_WTO_R1,
3326 io + B3_RI_WTO_R1,
3327 regs->len - B3_RI_WTO_R1);
3328 }
3329
3330 static const struct ethtool_ops sky2_ethtool_ops = {
3331 .get_settings = sky2_get_settings,
3332 .set_settings = sky2_set_settings,
3333 .get_drvinfo = sky2_get_drvinfo,
3334 .get_wol = sky2_get_wol,
3335 .set_wol = sky2_set_wol,
3336 .get_msglevel = sky2_get_msglevel,
3337 .set_msglevel = sky2_set_msglevel,
3338 .nway_reset = sky2_nway_reset,
3339 .get_regs_len = sky2_get_regs_len,
3340 .get_regs = sky2_get_regs,
3341 .get_link = ethtool_op_get_link,
3342 .get_sg = ethtool_op_get_sg,
3343 .set_sg = ethtool_op_set_sg,
3344 .get_tx_csum = ethtool_op_get_tx_csum,
3345 .set_tx_csum = ethtool_op_set_tx_csum,
3346 .get_tso = ethtool_op_get_tso,
3347 .set_tso = ethtool_op_set_tso,
3348 .get_rx_csum = sky2_get_rx_csum,
3349 .set_rx_csum = sky2_set_rx_csum,
3350 .get_strings = sky2_get_strings,
3351 .get_coalesce = sky2_get_coalesce,
3352 .set_coalesce = sky2_set_coalesce,
3353 .get_ringparam = sky2_get_ringparam,
3354 .set_ringparam = sky2_set_ringparam,
3355 .get_pauseparam = sky2_get_pauseparam,
3356 .set_pauseparam = sky2_set_pauseparam,
3357 .phys_id = sky2_phys_id,
3358 .get_stats_count = sky2_get_stats_count,
3359 .get_ethtool_stats = sky2_get_ethtool_stats,
3360 .get_perm_addr = ethtool_op_get_perm_addr,
3361 };
3362
3363 /* Initialize network device */
3364 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3365 unsigned port,
3366 int highmem, int wol)
3367 {
3368 struct sky2_port *sky2;
3369 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3370
3371 if (!dev) {
3372 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3373 return NULL;
3374 }
3375
3376 SET_MODULE_OWNER(dev);
3377 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3378 dev->irq = hw->pdev->irq;
3379 dev->open = sky2_up;
3380 dev->stop = sky2_down;
3381 dev->do_ioctl = sky2_ioctl;
3382 dev->hard_start_xmit = sky2_xmit_frame;
3383 dev->get_stats = sky2_get_stats;
3384 dev->set_multicast_list = sky2_set_multicast;
3385 dev->set_mac_address = sky2_set_mac_address;
3386 dev->change_mtu = sky2_change_mtu;
3387 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3388 dev->tx_timeout = sky2_tx_timeout;
3389 dev->watchdog_timeo = TX_WATCHDOG;
3390 if (port == 0)
3391 dev->poll = sky2_poll;
3392 dev->weight = NAPI_WEIGHT;
3393 #ifdef CONFIG_NET_POLL_CONTROLLER
3394 /* Network console (only works on port 0)
3395 * because netpoll makes assumptions about NAPI
3396 */
3397 if (port == 0)
3398 dev->poll_controller = sky2_netpoll;
3399 #endif
3400
3401 sky2 = netdev_priv(dev);
3402 sky2->netdev = dev;
3403 sky2->hw = hw;
3404 sky2->msg_enable = netif_msg_init(debug, default_msg);
3405
3406 /* Auto speed and flow control */
3407 sky2->autoneg = AUTONEG_ENABLE;
3408 sky2->flow_mode = FC_BOTH;
3409
3410 sky2->duplex = -1;
3411 sky2->speed = -1;
3412 sky2->advertising = sky2_supported_modes(hw);
3413 sky2->rx_csum = 1;
3414 sky2->wol = wol;
3415
3416 spin_lock_init(&sky2->phy_lock);
3417 sky2->tx_pending = TX_DEF_PENDING;
3418 sky2->rx_pending = RX_DEF_PENDING;
3419
3420 hw->dev[port] = dev;
3421
3422 sky2->port = port;
3423
3424 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3425 if (highmem)
3426 dev->features |= NETIF_F_HIGHDMA;
3427
3428 #ifdef SKY2_VLAN_TAG_USED
3429 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3430 dev->vlan_rx_register = sky2_vlan_rx_register;
3431 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3432 #endif
3433
3434 /* read the mac address */
3435 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3436 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3437
3438 /* device is off until link detection */
3439 netif_carrier_off(dev);
3440 netif_stop_queue(dev);
3441
3442 return dev;
3443 }
3444
3445 static void __devinit sky2_show_addr(struct net_device *dev)
3446 {
3447 const struct sky2_port *sky2 = netdev_priv(dev);
3448
3449 if (netif_msg_probe(sky2))
3450 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3451 dev->name,
3452 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3453 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3454 }
3455
3456 /* Handle software interrupt used during MSI test */
3457 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3458 {
3459 struct sky2_hw *hw = dev_id;
3460 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3461
3462 if (status == 0)
3463 return IRQ_NONE;
3464
3465 if (status & Y2_IS_IRQ_SW) {
3466 hw->msi = 1;
3467 wake_up(&hw->msi_wait);
3468 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3469 }
3470 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3471
3472 return IRQ_HANDLED;
3473 }
3474
3475 /* Test interrupt path by forcing a a software IRQ */
3476 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3477 {
3478 struct pci_dev *pdev = hw->pdev;
3479 int err;
3480
3481 init_waitqueue_head (&hw->msi_wait);
3482
3483 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3484
3485 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3486 if (err) {
3487 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3488 return err;
3489 }
3490
3491 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3492 sky2_read8(hw, B0_CTST);
3493
3494 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3495
3496 if (!hw->msi) {
3497 /* MSI test failed, go back to INTx mode */
3498 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3499 "switching to INTx mode.\n");
3500
3501 err = -EOPNOTSUPP;
3502 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3503 }
3504
3505 sky2_write32(hw, B0_IMSK, 0);
3506 sky2_read32(hw, B0_IMSK);
3507
3508 free_irq(pdev->irq, hw);
3509
3510 return err;
3511 }
3512
3513 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3514 {
3515 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3516 u16 value;
3517
3518 if (!pm)
3519 return 0;
3520 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3521 return 0;
3522 return value & PCI_PM_CTRL_PME_ENABLE;
3523 }
3524
3525 static int __devinit sky2_probe(struct pci_dev *pdev,
3526 const struct pci_device_id *ent)
3527 {
3528 struct net_device *dev;
3529 struct sky2_hw *hw;
3530 int err, using_dac = 0, wol_default;
3531
3532 err = pci_enable_device(pdev);
3533 if (err) {
3534 dev_err(&pdev->dev, "cannot enable PCI device\n");
3535 goto err_out;
3536 }
3537
3538 err = pci_request_regions(pdev, DRV_NAME);
3539 if (err) {
3540 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3541 goto err_out;
3542 }
3543
3544 pci_set_master(pdev);
3545
3546 if (sizeof(dma_addr_t) > sizeof(u32) &&
3547 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3548 using_dac = 1;
3549 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3550 if (err < 0) {
3551 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3552 "for consistent allocations\n");
3553 goto err_out_free_regions;
3554 }
3555 } else {
3556 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3557 if (err) {
3558 dev_err(&pdev->dev, "no usable DMA configuration\n");
3559 goto err_out_free_regions;
3560 }
3561 }
3562
3563 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3564
3565 err = -ENOMEM;
3566 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3567 if (!hw) {
3568 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3569 goto err_out_free_regions;
3570 }
3571
3572 hw->pdev = pdev;
3573
3574 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3575 if (!hw->regs) {
3576 dev_err(&pdev->dev, "cannot map device registers\n");
3577 goto err_out_free_hw;
3578 }
3579
3580 #ifdef __BIG_ENDIAN
3581 /* The sk98lin vendor driver uses hardware byte swapping but
3582 * this driver uses software swapping.
3583 */
3584 {
3585 u32 reg;
3586 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3587 reg &= ~PCI_REV_DESC;
3588 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3589 }
3590 #endif
3591
3592 /* ring for status responses */
3593 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3594 &hw->st_dma);
3595 if (!hw->st_le)
3596 goto err_out_iounmap;
3597
3598 err = sky2_init(hw);
3599 if (err)
3600 goto err_out_iounmap;
3601
3602 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3603 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3604 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3605 hw->chip_id, hw->chip_rev);
3606
3607 sky2_reset(hw);
3608
3609 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3610 if (!dev) {
3611 err = -ENOMEM;
3612 goto err_out_free_pci;
3613 }
3614
3615 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3616 err = sky2_test_msi(hw);
3617 if (err == -EOPNOTSUPP)
3618 pci_disable_msi(pdev);
3619 else if (err)
3620 goto err_out_free_netdev;
3621 }
3622
3623 err = register_netdev(dev);
3624 if (err) {
3625 dev_err(&pdev->dev, "cannot register net device\n");
3626 goto err_out_free_netdev;
3627 }
3628
3629 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3630 dev->name, hw);
3631 if (err) {
3632 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3633 goto err_out_unregister;
3634 }
3635 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3636
3637 sky2_show_addr(dev);
3638
3639 if (hw->ports > 1) {
3640 struct net_device *dev1;
3641
3642 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3643 if (!dev1)
3644 dev_warn(&pdev->dev, "allocation for second device failed\n");
3645 else if ((err = register_netdev(dev1))) {
3646 dev_warn(&pdev->dev,
3647 "register of second port failed (%d)\n", err);
3648 hw->dev[1] = NULL;
3649 free_netdev(dev1);
3650 } else
3651 sky2_show_addr(dev1);
3652 }
3653
3654 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3655 INIT_WORK(&hw->restart_work, sky2_restart);
3656
3657 sky2_idle_start(hw);
3658
3659 pci_set_drvdata(pdev, hw);
3660
3661 return 0;
3662
3663 err_out_unregister:
3664 if (hw->msi)
3665 pci_disable_msi(pdev);
3666 unregister_netdev(dev);
3667 err_out_free_netdev:
3668 free_netdev(dev);
3669 err_out_free_pci:
3670 sky2_write8(hw, B0_CTST, CS_RST_SET);
3671 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3672 err_out_iounmap:
3673 iounmap(hw->regs);
3674 err_out_free_hw:
3675 kfree(hw);
3676 err_out_free_regions:
3677 pci_release_regions(pdev);
3678 pci_disable_device(pdev);
3679 err_out:
3680 return err;
3681 }
3682
3683 static void __devexit sky2_remove(struct pci_dev *pdev)
3684 {
3685 struct sky2_hw *hw = pci_get_drvdata(pdev);
3686 struct net_device *dev0, *dev1;
3687
3688 if (!hw)
3689 return;
3690
3691 del_timer_sync(&hw->idle_timer);
3692
3693 flush_scheduled_work();
3694
3695 sky2_write32(hw, B0_IMSK, 0);
3696 synchronize_irq(hw->pdev->irq);
3697
3698 dev0 = hw->dev[0];
3699 dev1 = hw->dev[1];
3700 if (dev1)
3701 unregister_netdev(dev1);
3702 unregister_netdev(dev0);
3703
3704 sky2_power_aux(hw);
3705
3706 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3707 sky2_write8(hw, B0_CTST, CS_RST_SET);
3708 sky2_read8(hw, B0_CTST);
3709
3710 free_irq(pdev->irq, hw);
3711 if (hw->msi)
3712 pci_disable_msi(pdev);
3713 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3714 pci_release_regions(pdev);
3715 pci_disable_device(pdev);
3716
3717 if (dev1)
3718 free_netdev(dev1);
3719 free_netdev(dev0);
3720 iounmap(hw->regs);
3721 kfree(hw);
3722
3723 pci_set_drvdata(pdev, NULL);
3724 }
3725
3726 #ifdef CONFIG_PM
3727 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3728 {
3729 struct sky2_hw *hw = pci_get_drvdata(pdev);
3730 int i, wol = 0;
3731
3732 del_timer_sync(&hw->idle_timer);
3733 netif_poll_disable(hw->dev[0]);
3734
3735 for (i = 0; i < hw->ports; i++) {
3736 struct net_device *dev = hw->dev[i];
3737 struct sky2_port *sky2 = netdev_priv(dev);
3738
3739 if (netif_running(dev))
3740 sky2_down(dev);
3741
3742 if (sky2->wol)
3743 sky2_wol_init(sky2);
3744
3745 wol |= sky2->wol;
3746 }
3747
3748 sky2_write32(hw, B0_IMSK, 0);
3749 sky2_power_aux(hw);
3750
3751 pci_save_state(pdev);
3752 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3753 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3754
3755 return 0;
3756 }
3757
3758 static int sky2_resume(struct pci_dev *pdev)
3759 {
3760 struct sky2_hw *hw = pci_get_drvdata(pdev);
3761 int i, err;
3762
3763 err = pci_set_power_state(pdev, PCI_D0);
3764 if (err)
3765 goto out;
3766
3767 err = pci_restore_state(pdev);
3768 if (err)
3769 goto out;
3770
3771 pci_enable_wake(pdev, PCI_D0, 0);
3772 sky2_reset(hw);
3773
3774 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3775
3776 for (i = 0; i < hw->ports; i++) {
3777 struct net_device *dev = hw->dev[i];
3778 if (netif_running(dev)) {
3779 err = sky2_up(dev);
3780 if (err) {
3781 printk(KERN_ERR PFX "%s: could not up: %d\n",
3782 dev->name, err);
3783 dev_close(dev);
3784 goto out;
3785 }
3786 }
3787 }
3788
3789 netif_poll_enable(hw->dev[0]);
3790 sky2_idle_start(hw);
3791 return 0;
3792 out:
3793 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3794 pci_disable_device(pdev);
3795 return err;
3796 }
3797 #endif
3798
3799 static void sky2_shutdown(struct pci_dev *pdev)
3800 {
3801 struct sky2_hw *hw = pci_get_drvdata(pdev);
3802 int i, wol = 0;
3803
3804 del_timer_sync(&hw->idle_timer);
3805 netif_poll_disable(hw->dev[0]);
3806
3807 for (i = 0; i < hw->ports; i++) {
3808 struct net_device *dev = hw->dev[i];
3809 struct sky2_port *sky2 = netdev_priv(dev);
3810
3811 if (sky2->wol) {
3812 wol = 1;
3813 sky2_wol_init(sky2);
3814 }
3815 }
3816
3817 if (wol)
3818 sky2_power_aux(hw);
3819
3820 pci_enable_wake(pdev, PCI_D3hot, wol);
3821 pci_enable_wake(pdev, PCI_D3cold, wol);
3822
3823 pci_disable_device(pdev);
3824 pci_set_power_state(pdev, PCI_D3hot);
3825
3826 }
3827
3828 static struct pci_driver sky2_driver = {
3829 .name = DRV_NAME,
3830 .id_table = sky2_id_table,
3831 .probe = sky2_probe,
3832 .remove = __devexit_p(sky2_remove),
3833 #ifdef CONFIG_PM
3834 .suspend = sky2_suspend,
3835 .resume = sky2_resume,
3836 #endif
3837 .shutdown = sky2_shutdown,
3838 };
3839
3840 static int __init sky2_init_module(void)
3841 {
3842 return pci_register_driver(&sky2_driver);
3843 }
3844
3845 static void __exit sky2_cleanup_module(void)
3846 {
3847 pci_unregister_driver(&sky2_driver);
3848 }
3849
3850 module_init(sky2_init_module);
3851 module_exit(sky2_cleanup_module);
3852
3853 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3854 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3855 MODULE_LICENSE("GPL");
3856 MODULE_VERSION(DRV_VERSION);
linux kernel for loongson