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[ARM] rtc-pcf8583: don't use BCD_TO_BIN/BIN_TO_BCD
[linux-2.6/linux-loongson.git] / drivers / net / tulip / dmfe.c
blob7f59a3d4fda2c01fe5f903696e8501f683e7bd15
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65 */
66
67 #define DRV_NAME "dmfe"
68 #define DRV_VERSION "1.36.4"
69 #define DRV_RELDATE "2002-01-17"
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/ptrace.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/dma-mapping.h>
82 #include <linux/init.h>
83 #include <linux/netdevice.h>
84 #include <linux/etherdevice.h>
85 #include <linux/ethtool.h>
86 #include <linux/skbuff.h>
87 #include <linux/delay.h>
88 #include <linux/spinlock.h>
89 #include <linux/crc32.h>
90 #include <linux/bitops.h>
91
92 #include <asm/processor.h>
93 #include <asm/io.h>
94 #include <asm/dma.h>
95 #include <asm/uaccess.h>
96 #include <asm/irq.h>
97
98
99 /* Board/System/Debug information/definition ---------------- */
100 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
101 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
102 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
103 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
104
105 #define DM9102_IO_SIZE 0x80
106 #define DM9102A_IO_SIZE 0x100
107 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
108 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
109 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
110 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
111 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
112 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
113 #define TX_BUF_ALLOC 0x600
114 #define RX_ALLOC_SIZE 0x620
115 #define DM910X_RESET 1
116 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
117 #define CR6_DEFAULT 0x00080000 /* HD */
118 #define CR7_DEFAULT 0x180c1
119 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
120 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
121 #define MAX_PACKET_SIZE 1514
122 #define DMFE_MAX_MULTICAST 14
123 #define RX_COPY_SIZE 100
124 #define MAX_CHECK_PACKET 0x8000
125 #define DM9801_NOISE_FLOOR 8
126 #define DM9802_NOISE_FLOOR 5
127
128 #define DMFE_10MHF 0
129 #define DMFE_100MHF 1
130 #define DMFE_10MFD 4
131 #define DMFE_100MFD 5
132 #define DMFE_AUTO 8
133 #define DMFE_1M_HPNA 0x10
134
135 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
136 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
137 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
138 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
139 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
140 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
141
142 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
143 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
144 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
145
146 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
147
148 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
149
150
151 /* CR9 definition: SROM/MII */
152 #define CR9_SROM_READ 0x4800
153 #define CR9_SRCS 0x1
154 #define CR9_SRCLK 0x2
155 #define CR9_CRDOUT 0x8
156 #define SROM_DATA_0 0x0
157 #define SROM_DATA_1 0x4
158 #define PHY_DATA_1 0x20000
159 #define PHY_DATA_0 0x00000
160 #define MDCLKH 0x10000
161
162 #define PHY_POWER_DOWN 0x800
163
164 #define SROM_V41_CODE 0x14
165
166 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
167
168 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
169 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
170
171 /* Sten Check */
172 #define DEVICE net_device
173
174 /* Structure/enum declaration ------------------------------- */
175 struct tx_desc {
176 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
177 char *tx_buf_ptr; /* Data for us */
178 struct tx_desc *next_tx_desc;
179 } __attribute__(( aligned(32) ));
180
181 struct rx_desc {
182 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
183 struct sk_buff *rx_skb_ptr; /* Data for us */
184 struct rx_desc *next_rx_desc;
185 } __attribute__(( aligned(32) ));
186
187 struct dmfe_board_info {
188 u32 chip_id; /* Chip vendor/Device ID */
189 u32 chip_revision; /* Chip revision */
190 struct DEVICE *dev; /* net device */
191 struct pci_dev *pdev; /* PCI device */
192 spinlock_t lock;
193
194 long ioaddr; /* I/O base address */
195 u32 cr0_data;
196 u32 cr5_data;
197 u32 cr6_data;
198 u32 cr7_data;
199 u32 cr15_data;
200
201 /* pointer for memory physical address */
202 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
203 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
204 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
205 dma_addr_t first_tx_desc_dma;
206 dma_addr_t first_rx_desc_dma;
207
208 /* descriptor pointer */
209 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
210 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
211 unsigned char *desc_pool_ptr; /* descriptor pool memory */
212 struct tx_desc *first_tx_desc;
213 struct tx_desc *tx_insert_ptr;
214 struct tx_desc *tx_remove_ptr;
215 struct rx_desc *first_rx_desc;
216 struct rx_desc *rx_insert_ptr;
217 struct rx_desc *rx_ready_ptr; /* packet come pointer */
218 unsigned long tx_packet_cnt; /* transmitted packet count */
219 unsigned long tx_queue_cnt; /* wait to send packet count */
220 unsigned long rx_avail_cnt; /* available rx descriptor count */
221 unsigned long interval_rx_cnt; /* rx packet count a callback time */
222
223 u16 HPNA_command; /* For HPNA register 16 */
224 u16 HPNA_timer; /* For HPNA remote device check */
225 u16 dbug_cnt;
226 u16 NIC_capability; /* NIC media capability */
227 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
228
229 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
230 u8 chip_type; /* Keep DM9102A chip type */
231 u8 media_mode; /* user specify media mode */
232 u8 op_mode; /* real work media mode */
233 u8 phy_addr;
234 u8 link_failed; /* Ever link failed */
235 u8 wait_reset; /* Hardware failed, need to reset */
236 u8 dm910x_chk_mode; /* Operating mode check */
237 u8 first_in_callback; /* Flag to record state */
238 struct timer_list timer;
239
240 /* System defined statistic counter */
241 struct net_device_stats stats;
242
243 /* Driver defined statistic counter */
244 unsigned long tx_fifo_underrun;
245 unsigned long tx_loss_carrier;
246 unsigned long tx_no_carrier;
247 unsigned long tx_late_collision;
248 unsigned long tx_excessive_collision;
249 unsigned long tx_jabber_timeout;
250 unsigned long reset_count;
251 unsigned long reset_cr8;
252 unsigned long reset_fatal;
253 unsigned long reset_TXtimeout;
254
255 /* NIC SROM data */
256 unsigned char srom[128];
257 };
258
259 enum dmfe_offsets {
260 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
261 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
262 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
263 DCR15 = 0x78
264 };
265
266 enum dmfe_CR6_bits {
267 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
268 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
269 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
270 };
271
272 /* Global variable declaration ----------------------------- */
273 static int __devinitdata printed_version;
274 static char version[] __devinitdata =
275 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
276 DRV_VERSION " (" DRV_RELDATE ")\n";
277
278 static int dmfe_debug;
279 static unsigned char dmfe_media_mode = DMFE_AUTO;
280 static u32 dmfe_cr6_user_set;
281
282 /* For module input parameter */
283 static int debug;
284 static u32 cr6set;
285 static unsigned char mode = 8;
286 static u8 chkmode = 1;
287 static u8 HPNA_mode; /* Default: Low Power/High Speed */
288 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
289 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
290 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
291 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
292 4: TX pause packet */
293
294
295 /* function declaration ------------------------------------- */
296 static int dmfe_open(struct DEVICE *);
297 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
298 static int dmfe_stop(struct DEVICE *);
299 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
300 static void dmfe_set_filter_mode(struct DEVICE *);
301 static const struct ethtool_ops netdev_ethtool_ops;
302 static u16 read_srom_word(long ,int);
303 static irqreturn_t dmfe_interrupt(int , void *);
304 #ifdef CONFIG_NET_POLL_CONTROLLER
305 static void poll_dmfe (struct net_device *dev);
306 #endif
307 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
308 static void allocate_rx_buffer(struct dmfe_board_info *);
309 static void update_cr6(u32, unsigned long);
310 static void send_filter_frame(struct DEVICE * ,int);
311 static void dm9132_id_table(struct DEVICE * ,int);
312 static u16 phy_read(unsigned long, u8, u8, u32);
313 static void phy_write(unsigned long, u8, u8, u16, u32);
314 static void phy_write_1bit(unsigned long, u32);
315 static u16 phy_read_1bit(unsigned long);
316 static u8 dmfe_sense_speed(struct dmfe_board_info *);
317 static void dmfe_process_mode(struct dmfe_board_info *);
318 static void dmfe_timer(unsigned long);
319 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
320 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
321 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
322 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
323 static void dmfe_dynamic_reset(struct DEVICE *);
324 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
325 static void dmfe_init_dm910x(struct DEVICE *);
326 static void dmfe_parse_srom(struct dmfe_board_info *);
327 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
328 static void dmfe_program_DM9802(struct dmfe_board_info *);
329 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
330 static void dmfe_set_phyxcer(struct dmfe_board_info *);
331
332 /* DM910X network baord routine ---------------------------- */
333
334 /*
335 * Search DM910X board ,allocate space and register it
336 */
337
338 static int __devinit dmfe_init_one (struct pci_dev *pdev,
339 const struct pci_device_id *ent)
340 {
341 struct dmfe_board_info *db; /* board information structure */
342 struct net_device *dev;
343 u32 dev_rev, pci_pmr;
344 int i, err;
345
346 DMFE_DBUG(0, "dmfe_init_one()", 0);
347
348 if (!printed_version++)
349 printk(version);
350
351 /* Init network device */
352 dev = alloc_etherdev(sizeof(*db));
353 if (dev == NULL)
354 return -ENOMEM;
355 SET_MODULE_OWNER(dev);
356 SET_NETDEV_DEV(dev, &pdev->dev);
357
358 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
359 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
360 err = -ENODEV;
361 goto err_out_free;
362 }
363
364 /* Enable Master/IO access, Disable memory access */
365 err = pci_enable_device(pdev);
366 if (err)
367 goto err_out_free;
368
369 if (!pci_resource_start(pdev, 0)) {
370 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
371 err = -ENODEV;
372 goto err_out_disable;
373 }
374
375 /* Read Chip revision */
376 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
377
378 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
379 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
380 err = -ENODEV;
381 goto err_out_disable;
382 }
383
384 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
385
386 /* Set Latency Timer 80h */
387 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
388 Need a PCI quirk.. */
389
390 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
391 #endif
392
393 if (pci_request_regions(pdev, DRV_NAME)) {
394 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
395 err = -ENODEV;
396 goto err_out_disable;
397 }
398
399 /* Init system & device */
400 db = netdev_priv(dev);
401
402 db->dev = dev;
403
404 /* Allocate Tx/Rx descriptor memory */
405 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
406 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
407
408 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
409 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
410 db->buf_pool_start = db->buf_pool_ptr;
411 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
412
413 db->chip_id = ent->driver_data;
414 db->ioaddr = pci_resource_start(pdev, 0);
415 db->chip_revision = dev_rev;
416
417 db->pdev = pdev;
418
419 dev->base_addr = db->ioaddr;
420 dev->irq = pdev->irq;
421 pci_set_drvdata(pdev, dev);
422 dev->open = &dmfe_open;
423 dev->hard_start_xmit = &dmfe_start_xmit;
424 dev->stop = &dmfe_stop;
425 dev->get_stats = &dmfe_get_stats;
426 dev->set_multicast_list = &dmfe_set_filter_mode;
427 #ifdef CONFIG_NET_POLL_CONTROLLER
428 dev->poll_controller = &poll_dmfe;
429 #endif
430 dev->ethtool_ops = &netdev_ethtool_ops;
431 netif_carrier_off(db->dev);
432 spin_lock_init(&db->lock);
433
434 pci_read_config_dword(pdev, 0x50, &pci_pmr);
435 pci_pmr &= 0x70000;
436 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
437 db->chip_type = 1; /* DM9102A E3 */
438 else
439 db->chip_type = 0;
440
441 /* read 64 word srom data */
442 for (i = 0; i < 64; i++)
443 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
444
445 /* Set Node address */
446 for (i = 0; i < 6; i++)
447 dev->dev_addr[i] = db->srom[20 + i];
448
449 err = register_netdev (dev);
450 if (err)
451 goto err_out_res;
452
453 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
454 dev->name,
455 ent->driver_data >> 16,
456 pci_name(pdev));
457 for (i = 0; i < 6; i++)
458 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
459 printk(", irq %d.\n", dev->irq);
460
461 pci_set_master(pdev);
462
463 return 0;
464
465 err_out_res:
466 pci_release_regions(pdev);
467 err_out_disable:
468 pci_disable_device(pdev);
469 err_out_free:
470 pci_set_drvdata(pdev, NULL);
471 free_netdev(dev);
472
473 return err;
474 }
475
476
477 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
478 {
479 struct net_device *dev = pci_get_drvdata(pdev);
480 struct dmfe_board_info *db = netdev_priv(dev);
481
482 DMFE_DBUG(0, "dmfe_remove_one()", 0);
483
484 if (dev) {
485 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
486 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
487 db->desc_pool_dma_ptr);
488 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
489 db->buf_pool_ptr, db->buf_pool_dma_ptr);
490 unregister_netdev(dev);
491 pci_release_regions(pdev);
492 free_netdev(dev); /* free board information */
493 pci_set_drvdata(pdev, NULL);
494 }
495
496 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
497 }
498
499
500 /*
501 * Open the interface.
502 * The interface is opened whenever "ifconfig" actives it.
503 */
504
505 static int dmfe_open(struct DEVICE *dev)
506 {
507 int ret;
508 struct dmfe_board_info *db = netdev_priv(dev);
509
510 DMFE_DBUG(0, "dmfe_open", 0);
511
512 ret = request_irq(dev->irq, &dmfe_interrupt, IRQF_SHARED, dev->name, dev);
513 if (ret)
514 return ret;
515
516 /* system variable init */
517 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
518 db->tx_packet_cnt = 0;
519 db->tx_queue_cnt = 0;
520 db->rx_avail_cnt = 0;
521 db->link_failed = 1;
522 db->wait_reset = 0;
523
524 db->first_in_callback = 0;
525 db->NIC_capability = 0xf; /* All capability*/
526 db->PHY_reg4 = 0x1e0;
527
528 /* CR6 operation mode decision */
529 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
530 (db->chip_revision >= 0x02000030) ) {
531 db->cr6_data |= DMFE_TXTH_256;
532 db->cr0_data = CR0_DEFAULT;
533 db->dm910x_chk_mode=4; /* Enter the normal mode */
534 } else {
535 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
536 db->cr0_data = 0;
537 db->dm910x_chk_mode = 1; /* Enter the check mode */
538 }
539
540 /* Initilize DM910X board */
541 dmfe_init_dm910x(dev);
542
543 /* Active System Interface */
544 netif_wake_queue(dev);
545
546 /* set and active a timer process */
547 init_timer(&db->timer);
548 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
549 db->timer.data = (unsigned long)dev;
550 db->timer.function = &dmfe_timer;
551 add_timer(&db->timer);
552
553 return 0;
554 }
555
556
557 /* Initilize DM910X board
558 * Reset DM910X board
559 * Initilize TX/Rx descriptor chain structure
560 * Send the set-up frame
561 * Enable Tx/Rx machine
562 */
563
564 static void dmfe_init_dm910x(struct DEVICE *dev)
565 {
566 struct dmfe_board_info *db = netdev_priv(dev);
567 unsigned long ioaddr = db->ioaddr;
568
569 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
570
571 /* Reset DM910x MAC controller */
572 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
573 udelay(100);
574 outl(db->cr0_data, ioaddr + DCR0);
575 udelay(5);
576
577 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
578 db->phy_addr = 1;
579
580 /* Parser SROM and media mode */
581 dmfe_parse_srom(db);
582 db->media_mode = dmfe_media_mode;
583
584 /* RESET Phyxcer Chip by GPR port bit 7 */
585 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
586 if (db->chip_id == PCI_DM9009_ID) {
587 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
588 mdelay(300); /* Delay 300 ms */
589 }
590 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
591
592 /* Process Phyxcer Media Mode */
593 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
594 dmfe_set_phyxcer(db);
595
596 /* Media Mode Process */
597 if ( !(db->media_mode & DMFE_AUTO) )
598 db->op_mode = db->media_mode; /* Force Mode */
599
600 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
601 dmfe_descriptor_init(db, ioaddr);
602
603 /* Init CR6 to program DM910x operation */
604 update_cr6(db->cr6_data, ioaddr);
605
606 /* Send setup frame */
607 if (db->chip_id == PCI_DM9132_ID)
608 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
609 else
610 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
611
612 /* Init CR7, interrupt active bit */
613 db->cr7_data = CR7_DEFAULT;
614 outl(db->cr7_data, ioaddr + DCR7);
615
616 /* Init CR15, Tx jabber and Rx watchdog timer */
617 outl(db->cr15_data, ioaddr + DCR15);
618
619 /* Enable DM910X Tx/Rx function */
620 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
621 update_cr6(db->cr6_data, ioaddr);
622 }
623
624
625 /*
626 * Hardware start transmission.
627 * Send a packet to media from the upper layer.
628 */
629
630 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
631 {
632 struct dmfe_board_info *db = netdev_priv(dev);
633 struct tx_desc *txptr;
634 unsigned long flags;
635
636 DMFE_DBUG(0, "dmfe_start_xmit", 0);
637
638 /* Resource flag check */
639 netif_stop_queue(dev);
640
641 /* Too large packet check */
642 if (skb->len > MAX_PACKET_SIZE) {
643 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
644 dev_kfree_skb(skb);
645 return 0;
646 }
647
648 spin_lock_irqsave(&db->lock, flags);
649
650 /* No Tx resource check, it never happen nromally */
651 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
652 spin_unlock_irqrestore(&db->lock, flags);
653 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
654 return 1;
655 }
656
657 /* Disable NIC interrupt */
658 outl(0, dev->base_addr + DCR7);
659
660 /* transmit this packet */
661 txptr = db->tx_insert_ptr;
662 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
663 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
664
665 /* Point to next transmit free descriptor */
666 db->tx_insert_ptr = txptr->next_tx_desc;
667
668 /* Transmit Packet Process */
669 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
670 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
671 db->tx_packet_cnt++; /* Ready to send */
672 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
673 dev->trans_start = jiffies; /* saved time stamp */
674 } else {
675 db->tx_queue_cnt++; /* queue TX packet */
676 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
677 }
678
679 /* Tx resource check */
680 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
681 netif_wake_queue(dev);
682
683 /* Restore CR7 to enable interrupt */
684 spin_unlock_irqrestore(&db->lock, flags);
685 outl(db->cr7_data, dev->base_addr + DCR7);
686
687 /* free this SKB */
688 dev_kfree_skb(skb);
689
690 return 0;
691 }
692
693
694 /*
695 * Stop the interface.
696 * The interface is stopped when it is brought.
697 */
698
699 static int dmfe_stop(struct DEVICE *dev)
700 {
701 struct dmfe_board_info *db = netdev_priv(dev);
702 unsigned long ioaddr = dev->base_addr;
703
704 DMFE_DBUG(0, "dmfe_stop", 0);
705
706 /* disable system */
707 netif_stop_queue(dev);
708
709 /* deleted timer */
710 del_timer_sync(&db->timer);
711
712 /* Reset & stop DM910X board */
713 outl(DM910X_RESET, ioaddr + DCR0);
714 udelay(5);
715 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
716
717 /* free interrupt */
718 free_irq(dev->irq, dev);
719
720 /* free allocated rx buffer */
721 dmfe_free_rxbuffer(db);
722
723 #if 0
724 /* show statistic counter */
725 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
726 db->tx_fifo_underrun, db->tx_excessive_collision,
727 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
728 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
729 db->reset_fatal, db->reset_TXtimeout);
730 #endif
731
732 return 0;
733 }
734
735
736 /*
737 * DM9102 insterrupt handler
738 * receive the packet to upper layer, free the transmitted packet
739 */
740
741 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
742 {
743 struct DEVICE *dev = dev_id;
744 struct dmfe_board_info *db = netdev_priv(dev);
745 unsigned long ioaddr = dev->base_addr;
746 unsigned long flags;
747
748 DMFE_DBUG(0, "dmfe_interrupt()", 0);
749
750 spin_lock_irqsave(&db->lock, flags);
751
752 /* Got DM910X status */
753 db->cr5_data = inl(ioaddr + DCR5);
754 outl(db->cr5_data, ioaddr + DCR5);
755 if ( !(db->cr5_data & 0xc1) ) {
756 spin_unlock_irqrestore(&db->lock, flags);
757 return IRQ_HANDLED;
758 }
759
760 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
761 outl(0, ioaddr + DCR7);
762
763 /* Check system status */
764 if (db->cr5_data & 0x2000) {
765 /* system bus error happen */
766 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
767 db->reset_fatal++;
768 db->wait_reset = 1; /* Need to RESET */
769 spin_unlock_irqrestore(&db->lock, flags);
770 return IRQ_HANDLED;
771 }
772
773 /* Received the coming packet */
774 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
775 dmfe_rx_packet(dev, db);
776
777 /* reallocate rx descriptor buffer */
778 if (db->rx_avail_cnt<RX_DESC_CNT)
779 allocate_rx_buffer(db);
780
781 /* Free the transmitted descriptor */
782 if ( db->cr5_data & 0x01)
783 dmfe_free_tx_pkt(dev, db);
784
785 /* Mode Check */
786 if (db->dm910x_chk_mode & 0x2) {
787 db->dm910x_chk_mode = 0x4;
788 db->cr6_data |= 0x100;
789 update_cr6(db->cr6_data, db->ioaddr);
790 }
791
792 /* Restore CR7 to enable interrupt mask */
793 outl(db->cr7_data, ioaddr + DCR7);
794
795 spin_unlock_irqrestore(&db->lock, flags);
796 return IRQ_HANDLED;
797 }
798
799
800 #ifdef CONFIG_NET_POLL_CONTROLLER
801 /*
802 * Polling 'interrupt' - used by things like netconsole to send skbs
803 * without having to re-enable interrupts. It's not called while
804 * the interrupt routine is executing.
805 */
806
807 static void poll_dmfe (struct net_device *dev)
808 {
809 /* disable_irq here is not very nice, but with the lockless
810 interrupt handler we have no other choice. */
811 disable_irq(dev->irq);
812 dmfe_interrupt (dev->irq, dev);
813 enable_irq(dev->irq);
814 }
815 #endif
816
817 /*
818 * Free TX resource after TX complete
819 */
820
821 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
822 {
823 struct tx_desc *txptr;
824 unsigned long ioaddr = dev->base_addr;
825 u32 tdes0;
826
827 txptr = db->tx_remove_ptr;
828 while(db->tx_packet_cnt) {
829 tdes0 = le32_to_cpu(txptr->tdes0);
830 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
831 if (tdes0 & 0x80000000)
832 break;
833
834 /* A packet sent completed */
835 db->tx_packet_cnt--;
836 db->stats.tx_packets++;
837
838 /* Transmit statistic counter */
839 if ( tdes0 != 0x7fffffff ) {
840 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
841 db->stats.collisions += (tdes0 >> 3) & 0xf;
842 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
843 if (tdes0 & TDES0_ERR_MASK) {
844 db->stats.tx_errors++;
845
846 if (tdes0 & 0x0002) { /* UnderRun */
847 db->tx_fifo_underrun++;
848 if ( !(db->cr6_data & CR6_SFT) ) {
849 db->cr6_data = db->cr6_data | CR6_SFT;
850 update_cr6(db->cr6_data, db->ioaddr);
851 }
852 }
853 if (tdes0 & 0x0100)
854 db->tx_excessive_collision++;
855 if (tdes0 & 0x0200)
856 db->tx_late_collision++;
857 if (tdes0 & 0x0400)
858 db->tx_no_carrier++;
859 if (tdes0 & 0x0800)
860 db->tx_loss_carrier++;
861 if (tdes0 & 0x4000)
862 db->tx_jabber_timeout++;
863 }
864 }
865
866 txptr = txptr->next_tx_desc;
867 }/* End of while */
868
869 /* Update TX remove pointer to next */
870 db->tx_remove_ptr = txptr;
871
872 /* Send the Tx packet in queue */
873 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
874 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
875 db->tx_packet_cnt++; /* Ready to send */
876 db->tx_queue_cnt--;
877 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
878 dev->trans_start = jiffies; /* saved time stamp */
879 }
880
881 /* Resource available check */
882 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
883 netif_wake_queue(dev); /* Active upper layer, send again */
884 }
885
886
887 /*
888 * Calculate the CRC valude of the Rx packet
889 * flag = 1 : return the reverse CRC (for the received packet CRC)
890 * 0 : return the normal CRC (for Hash Table index)
891 */
892
893 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
894 {
895 u32 crc = crc32(~0, Data, Len);
896 if (flag) crc = ~crc;
897 return crc;
898 }
899
900
901 /*
902 * Receive the come packet and pass to upper layer
903 */
904
905 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
906 {
907 struct rx_desc *rxptr;
908 struct sk_buff *skb;
909 int rxlen;
910 u32 rdes0;
911
912 rxptr = db->rx_ready_ptr;
913
914 while(db->rx_avail_cnt) {
915 rdes0 = le32_to_cpu(rxptr->rdes0);
916 if (rdes0 & 0x80000000) /* packet owner check */
917 break;
918
919 db->rx_avail_cnt--;
920 db->interval_rx_cnt++;
921
922 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
923 if ( (rdes0 & 0x300) != 0x300) {
924 /* A packet without First/Last flag */
925 /* reuse this SKB */
926 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
927 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
928 } else {
929 /* A packet with First/Last flag */
930 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
931
932 /* error summary bit check */
933 if (rdes0 & 0x8000) {
934 /* This is a error packet */
935 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
936 db->stats.rx_errors++;
937 if (rdes0 & 1)
938 db->stats.rx_fifo_errors++;
939 if (rdes0 & 2)
940 db->stats.rx_crc_errors++;
941 if (rdes0 & 0x80)
942 db->stats.rx_length_errors++;
943 }
944
945 if ( !(rdes0 & 0x8000) ||
946 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
947 skb = rxptr->rx_skb_ptr;
948
949 /* Received Packet CRC check need or not */
950 if ( (db->dm910x_chk_mode & 1) &&
951 (cal_CRC(skb->data, rxlen, 1) !=
952 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
953 /* Found a error received packet */
954 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
955 db->dm910x_chk_mode = 3;
956 } else {
957 /* Good packet, send to upper layer */
958 /* Shorst packet used new SKB */
959 if ( (rxlen < RX_COPY_SIZE) &&
960 ( (skb = dev_alloc_skb(rxlen + 2) )
961 != NULL) ) {
962 /* size less than COPY_SIZE, allocate a rxlen SKB */
963 skb->dev = dev;
964 skb_reserve(skb, 2); /* 16byte align */
965 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->data, rxlen);
966 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
967 } else {
968 skb->dev = dev;
969 skb_put(skb, rxlen);
970 }
971 skb->protocol = eth_type_trans(skb, dev);
972 netif_rx(skb);
973 dev->last_rx = jiffies;
974 db->stats.rx_packets++;
975 db->stats.rx_bytes += rxlen;
976 }
977 } else {
978 /* Reuse SKB buffer when the packet is error */
979 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
980 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
981 }
982 }
983
984 rxptr = rxptr->next_rx_desc;
985 }
986
987 db->rx_ready_ptr = rxptr;
988 }
989
990
991 /*
992 * Get statistics from driver.
993 */
994
995 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
996 {
997 struct dmfe_board_info *db = netdev_priv(dev);
998
999 DMFE_DBUG(0, "dmfe_get_stats", 0);
1000 return &db->stats;
1001 }
1002
1003
1004 /*
1005 * Set DM910X multicast address
1006 */
1007
1008 static void dmfe_set_filter_mode(struct DEVICE * dev)
1009 {
1010 struct dmfe_board_info *db = netdev_priv(dev);
1011 unsigned long flags;
1012
1013 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1014 spin_lock_irqsave(&db->lock, flags);
1015
1016 if (dev->flags & IFF_PROMISC) {
1017 DMFE_DBUG(0, "Enable PROM Mode", 0);
1018 db->cr6_data |= CR6_PM | CR6_PBF;
1019 update_cr6(db->cr6_data, db->ioaddr);
1020 spin_unlock_irqrestore(&db->lock, flags);
1021 return;
1022 }
1023
1024 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1025 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1026 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1027 db->cr6_data |= CR6_PAM;
1028 spin_unlock_irqrestore(&db->lock, flags);
1029 return;
1030 }
1031
1032 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1033 if (db->chip_id == PCI_DM9132_ID)
1034 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1035 else
1036 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1037 spin_unlock_irqrestore(&db->lock, flags);
1038 }
1039
1040 static void netdev_get_drvinfo(struct net_device *dev,
1041 struct ethtool_drvinfo *info)
1042 {
1043 struct dmfe_board_info *np = netdev_priv(dev);
1044
1045 strcpy(info->driver, DRV_NAME);
1046 strcpy(info->version, DRV_VERSION);
1047 if (np->pdev)
1048 strcpy(info->bus_info, pci_name(np->pdev));
1049 else
1050 sprintf(info->bus_info, "EISA 0x%lx %d",
1051 dev->base_addr, dev->irq);
1052 }
1053
1054 static const struct ethtool_ops netdev_ethtool_ops = {
1055 .get_drvinfo = netdev_get_drvinfo,
1056 .get_link = ethtool_op_get_link,
1057 };
1058
1059 /*
1060 * A periodic timer routine
1061 * Dynamic media sense, allocate Rx buffer...
1062 */
1063
1064 static void dmfe_timer(unsigned long data)
1065 {
1066 u32 tmp_cr8;
1067 unsigned char tmp_cr12;
1068 struct DEVICE *dev = (struct DEVICE *) data;
1069 struct dmfe_board_info *db = netdev_priv(dev);
1070 unsigned long flags;
1071
1072 DMFE_DBUG(0, "dmfe_timer()", 0);
1073 spin_lock_irqsave(&db->lock, flags);
1074
1075 /* Media mode process when Link OK before enter this route */
1076 if (db->first_in_callback == 0) {
1077 db->first_in_callback = 1;
1078 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1079 db->cr6_data &= ~0x40000;
1080 update_cr6(db->cr6_data, db->ioaddr);
1081 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1082 db->cr6_data |= 0x40000;
1083 update_cr6(db->cr6_data, db->ioaddr);
1084 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1085 add_timer(&db->timer);
1086 spin_unlock_irqrestore(&db->lock, flags);
1087 return;
1088 }
1089 }
1090
1091
1092 /* Operating Mode Check */
1093 if ( (db->dm910x_chk_mode & 0x1) &&
1094 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1095 db->dm910x_chk_mode = 0x4;
1096
1097 /* Dynamic reset DM910X : system error or transmit time-out */
1098 tmp_cr8 = inl(db->ioaddr + DCR8);
1099 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1100 db->reset_cr8++;
1101 db->wait_reset = 1;
1102 }
1103 db->interval_rx_cnt = 0;
1104
1105 /* TX polling kick monitor */
1106 if ( db->tx_packet_cnt &&
1107 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1108 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1109
1110 /* TX Timeout */
1111 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1112 db->reset_TXtimeout++;
1113 db->wait_reset = 1;
1114 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1115 dev->name);
1116 }
1117 }
1118
1119 if (db->wait_reset) {
1120 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1121 db->reset_count++;
1122 dmfe_dynamic_reset(dev);
1123 db->first_in_callback = 0;
1124 db->timer.expires = DMFE_TIMER_WUT;
1125 add_timer(&db->timer);
1126 spin_unlock_irqrestore(&db->lock, flags);
1127 return;
1128 }
1129
1130 /* Link status check, Dynamic media type change */
1131 if (db->chip_id == PCI_DM9132_ID)
1132 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1133 else
1134 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1135
1136 if ( ((db->chip_id == PCI_DM9102_ID) &&
1137 (db->chip_revision == 0x02000030)) ||
1138 ((db->chip_id == PCI_DM9132_ID) &&
1139 (db->chip_revision == 0x02000010)) ) {
1140 /* DM9102A Chip */
1141 if (tmp_cr12 & 2)
1142 tmp_cr12 = 0x0; /* Link failed */
1143 else
1144 tmp_cr12 = 0x3; /* Link OK */
1145 }
1146
1147 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1148 /* Link Failed */
1149 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1150 db->link_failed = 1;
1151 netif_carrier_off(db->dev);
1152
1153 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1154 /* AUTO or force 1M Homerun/Longrun don't need */
1155 if ( !(db->media_mode & 0x38) )
1156 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1157
1158 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1159 if (db->media_mode & DMFE_AUTO) {
1160 /* 10/100M link failed, used 1M Home-Net */
1161 db->cr6_data|=0x00040000; /* bit18=1, MII */
1162 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1163 update_cr6(db->cr6_data, db->ioaddr);
1164 }
1165 } else
1166 if ((tmp_cr12 & 0x3) && db->link_failed) {
1167 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1168 db->link_failed = 0;
1169
1170 /* Auto Sense Speed */
1171 if ( (db->media_mode & DMFE_AUTO) &&
1172 dmfe_sense_speed(db) )
1173 db->link_failed = 1;
1174 else
1175 netif_carrier_on(db->dev);
1176 dmfe_process_mode(db);
1177 /* SHOW_MEDIA_TYPE(db->op_mode); */
1178 }
1179
1180 /* HPNA remote command check */
1181 if (db->HPNA_command & 0xf00) {
1182 db->HPNA_timer--;
1183 if (!db->HPNA_timer)
1184 dmfe_HPNA_remote_cmd_chk(db);
1185 }
1186
1187 /* Timer active again */
1188 db->timer.expires = DMFE_TIMER_WUT;
1189 add_timer(&db->timer);
1190 spin_unlock_irqrestore(&db->lock, flags);
1191 }
1192
1193
1194 /*
1195 * Dynamic reset the DM910X board
1196 * Stop DM910X board
1197 * Free Tx/Rx allocated memory
1198 * Reset DM910X board
1199 * Re-initilize DM910X board
1200 */
1201
1202 static void dmfe_dynamic_reset(struct DEVICE *dev)
1203 {
1204 struct dmfe_board_info *db = netdev_priv(dev);
1205
1206 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1207
1208 /* Sopt MAC controller */
1209 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1210 update_cr6(db->cr6_data, dev->base_addr);
1211 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1212 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1213
1214 /* Disable upper layer interface */
1215 netif_stop_queue(dev);
1216
1217 /* Free Rx Allocate buffer */
1218 dmfe_free_rxbuffer(db);
1219
1220 /* system variable init */
1221 db->tx_packet_cnt = 0;
1222 db->tx_queue_cnt = 0;
1223 db->rx_avail_cnt = 0;
1224 db->link_failed = 1;
1225 db->wait_reset = 0;
1226
1227 /* Re-initilize DM910X board */
1228 dmfe_init_dm910x(dev);
1229
1230 /* Restart upper layer interface */
1231 netif_wake_queue(dev);
1232 }
1233
1234
1235 /*
1236 * free all allocated rx buffer
1237 */
1238
1239 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1240 {
1241 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1242
1243 /* free allocated rx buffer */
1244 while (db->rx_avail_cnt) {
1245 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1246 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1247 db->rx_avail_cnt--;
1248 }
1249 }
1250
1251
1252 /*
1253 * Reuse the SK buffer
1254 */
1255
1256 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1257 {
1258 struct rx_desc *rxptr = db->rx_insert_ptr;
1259
1260 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1261 rxptr->rx_skb_ptr = skb;
1262 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1263 wmb();
1264 rxptr->rdes0 = cpu_to_le32(0x80000000);
1265 db->rx_avail_cnt++;
1266 db->rx_insert_ptr = rxptr->next_rx_desc;
1267 } else
1268 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1269 }
1270
1271
1272 /*
1273 * Initialize transmit/Receive descriptor
1274 * Using Chain structure, and allocate Tx/Rx buffer
1275 */
1276
1277 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1278 {
1279 struct tx_desc *tmp_tx;
1280 struct rx_desc *tmp_rx;
1281 unsigned char *tmp_buf;
1282 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1283 dma_addr_t tmp_buf_dma;
1284 int i;
1285
1286 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1287
1288 /* tx descriptor start pointer */
1289 db->tx_insert_ptr = db->first_tx_desc;
1290 db->tx_remove_ptr = db->first_tx_desc;
1291 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1292
1293 /* rx descriptor start pointer */
1294 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1295 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1296 db->rx_insert_ptr = db->first_rx_desc;
1297 db->rx_ready_ptr = db->first_rx_desc;
1298 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1299
1300 /* Init Transmit chain */
1301 tmp_buf = db->buf_pool_start;
1302 tmp_buf_dma = db->buf_pool_dma_start;
1303 tmp_tx_dma = db->first_tx_desc_dma;
1304 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1305 tmp_tx->tx_buf_ptr = tmp_buf;
1306 tmp_tx->tdes0 = cpu_to_le32(0);
1307 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1308 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1309 tmp_tx_dma += sizeof(struct tx_desc);
1310 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1311 tmp_tx->next_tx_desc = tmp_tx + 1;
1312 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1313 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1314 }
1315 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1316 tmp_tx->next_tx_desc = db->first_tx_desc;
1317
1318 /* Init Receive descriptor chain */
1319 tmp_rx_dma=db->first_rx_desc_dma;
1320 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1321 tmp_rx->rdes0 = cpu_to_le32(0);
1322 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1323 tmp_rx_dma += sizeof(struct rx_desc);
1324 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1325 tmp_rx->next_rx_desc = tmp_rx + 1;
1326 }
1327 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1328 tmp_rx->next_rx_desc = db->first_rx_desc;
1329
1330 /* pre-allocate Rx buffer */
1331 allocate_rx_buffer(db);
1332 }
1333
1334
1335 /*
1336 * Update CR6 value
1337 * Firstly stop DM910X , then written value and start
1338 */
1339
1340 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1341 {
1342 u32 cr6_tmp;
1343
1344 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1345 outl(cr6_tmp, ioaddr + DCR6);
1346 udelay(5);
1347 outl(cr6_data, ioaddr + DCR6);
1348 udelay(5);
1349 }
1350
1351
1352 /*
1353 * Send a setup frame for DM9132
1354 * This setup frame initilize DM910X address filter mode
1355 */
1356
1357 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1358 {
1359 struct dev_mc_list *mcptr;
1360 u16 * addrptr;
1361 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1362 u32 hash_val;
1363 u16 i, hash_table[4];
1364
1365 DMFE_DBUG(0, "dm9132_id_table()", 0);
1366
1367 /* Node address */
1368 addrptr = (u16 *) dev->dev_addr;
1369 outw(addrptr[0], ioaddr);
1370 ioaddr += 4;
1371 outw(addrptr[1], ioaddr);
1372 ioaddr += 4;
1373 outw(addrptr[2], ioaddr);
1374 ioaddr += 4;
1375
1376 /* Clear Hash Table */
1377 for (i = 0; i < 4; i++)
1378 hash_table[i] = 0x0;
1379
1380 /* broadcast address */
1381 hash_table[3] = 0x8000;
1382
1383 /* the multicast address in Hash Table : 64 bits */
1384 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1385 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1386 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1387 }
1388
1389 /* Write the hash table to MAC MD table */
1390 for (i = 0; i < 4; i++, ioaddr += 4)
1391 outw(hash_table[i], ioaddr);
1392 }
1393
1394
1395 /*
1396 * Send a setup frame for DM9102/DM9102A
1397 * This setup frame initilize DM910X address filter mode
1398 */
1399
1400 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1401 {
1402 struct dmfe_board_info *db = netdev_priv(dev);
1403 struct dev_mc_list *mcptr;
1404 struct tx_desc *txptr;
1405 u16 * addrptr;
1406 u32 * suptr;
1407 int i;
1408
1409 DMFE_DBUG(0, "send_filter_frame()", 0);
1410
1411 txptr = db->tx_insert_ptr;
1412 suptr = (u32 *) txptr->tx_buf_ptr;
1413
1414 /* Node address */
1415 addrptr = (u16 *) dev->dev_addr;
1416 *suptr++ = addrptr[0];
1417 *suptr++ = addrptr[1];
1418 *suptr++ = addrptr[2];
1419
1420 /* broadcast address */
1421 *suptr++ = 0xffff;
1422 *suptr++ = 0xffff;
1423 *suptr++ = 0xffff;
1424
1425 /* fit the multicast address */
1426 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1427 addrptr = (u16 *) mcptr->dmi_addr;
1428 *suptr++ = addrptr[0];
1429 *suptr++ = addrptr[1];
1430 *suptr++ = addrptr[2];
1431 }
1432
1433 for (; i<14; i++) {
1434 *suptr++ = 0xffff;
1435 *suptr++ = 0xffff;
1436 *suptr++ = 0xffff;
1437 }
1438
1439 /* prepare the setup frame */
1440 db->tx_insert_ptr = txptr->next_tx_desc;
1441 txptr->tdes1 = cpu_to_le32(0x890000c0);
1442
1443 /* Resource Check and Send the setup packet */
1444 if (!db->tx_packet_cnt) {
1445 /* Resource Empty */
1446 db->tx_packet_cnt++;
1447 txptr->tdes0 = cpu_to_le32(0x80000000);
1448 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1449 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1450 update_cr6(db->cr6_data, dev->base_addr);
1451 dev->trans_start = jiffies;
1452 } else
1453 db->tx_queue_cnt++; /* Put in TX queue */
1454 }
1455
1456
1457 /*
1458 * Allocate rx buffer,
1459 * As possible as allocate maxiumn Rx buffer
1460 */
1461
1462 static void allocate_rx_buffer(struct dmfe_board_info *db)
1463 {
1464 struct rx_desc *rxptr;
1465 struct sk_buff *skb;
1466
1467 rxptr = db->rx_insert_ptr;
1468
1469 while(db->rx_avail_cnt < RX_DESC_CNT) {
1470 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1471 break;
1472 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1473 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1474 wmb();
1475 rxptr->rdes0 = cpu_to_le32(0x80000000);
1476 rxptr = rxptr->next_rx_desc;
1477 db->rx_avail_cnt++;
1478 }
1479
1480 db->rx_insert_ptr = rxptr;
1481 }
1482
1483
1484 /*
1485 * Read one word data from the serial ROM
1486 */
1487
1488 static u16 read_srom_word(long ioaddr, int offset)
1489 {
1490 int i;
1491 u16 srom_data = 0;
1492 long cr9_ioaddr = ioaddr + DCR9;
1493
1494 outl(CR9_SROM_READ, cr9_ioaddr);
1495 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1496
1497 /* Send the Read Command 110b */
1498 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1499 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1500 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1501
1502 /* Send the offset */
1503 for (i = 5; i >= 0; i--) {
1504 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1505 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1506 }
1507
1508 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1509
1510 for (i = 16; i > 0; i--) {
1511 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1512 udelay(5);
1513 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1514 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1515 udelay(5);
1516 }
1517
1518 outl(CR9_SROM_READ, cr9_ioaddr);
1519 return srom_data;
1520 }
1521
1522
1523 /*
1524 * Auto sense the media mode
1525 */
1526
1527 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1528 {
1529 u8 ErrFlag = 0;
1530 u16 phy_mode;
1531
1532 /* CR6 bit18=0, select 10/100M */
1533 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1534
1535 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1536 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1537
1538 if ( (phy_mode & 0x24) == 0x24 ) {
1539 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1540 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1541 else /* DM9102/DM9102A */
1542 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1543 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1544 switch (phy_mode) {
1545 case 0x1000: db->op_mode = DMFE_10MHF; break;
1546 case 0x2000: db->op_mode = DMFE_10MFD; break;
1547 case 0x4000: db->op_mode = DMFE_100MHF; break;
1548 case 0x8000: db->op_mode = DMFE_100MFD; break;
1549 default: db->op_mode = DMFE_10MHF;
1550 ErrFlag = 1;
1551 break;
1552 }
1553 } else {
1554 db->op_mode = DMFE_10MHF;
1555 DMFE_DBUG(0, "Link Failed :", phy_mode);
1556 ErrFlag = 1;
1557 }
1558
1559 return ErrFlag;
1560 }
1561
1562
1563 /*
1564 * Set 10/100 phyxcer capability
1565 * AUTO mode : phyxcer register4 is NIC capability
1566 * Force mode: phyxcer register4 is the force media
1567 */
1568
1569 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1570 {
1571 u16 phy_reg;
1572
1573 /* Select 10/100M phyxcer */
1574 db->cr6_data &= ~0x40000;
1575 update_cr6(db->cr6_data, db->ioaddr);
1576
1577 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1578 if (db->chip_id == PCI_DM9009_ID) {
1579 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1580 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1581 }
1582
1583 /* Phyxcer capability setting */
1584 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1585
1586 if (db->media_mode & DMFE_AUTO) {
1587 /* AUTO Mode */
1588 phy_reg |= db->PHY_reg4;
1589 } else {
1590 /* Force Mode */
1591 switch(db->media_mode) {
1592 case DMFE_10MHF: phy_reg |= 0x20; break;
1593 case DMFE_10MFD: phy_reg |= 0x40; break;
1594 case DMFE_100MHF: phy_reg |= 0x80; break;
1595 case DMFE_100MFD: phy_reg |= 0x100; break;
1596 }
1597 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1598 }
1599
1600 /* Write new capability to Phyxcer Reg4 */
1601 if ( !(phy_reg & 0x01e0)) {
1602 phy_reg|=db->PHY_reg4;
1603 db->media_mode|=DMFE_AUTO;
1604 }
1605 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1606
1607 /* Restart Auto-Negotiation */
1608 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1609 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1610 if ( !db->chip_type )
1611 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1612 }
1613
1614
1615 /*
1616 * Process op-mode
1617 * AUTO mode : PHY controller in Auto-negotiation Mode
1618 * Force mode: PHY controller in force mode with HUB
1619 * N-way force capability with SWITCH
1620 */
1621
1622 static void dmfe_process_mode(struct dmfe_board_info *db)
1623 {
1624 u16 phy_reg;
1625
1626 /* Full Duplex Mode Check */
1627 if (db->op_mode & 0x4)
1628 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1629 else
1630 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1631
1632 /* Transciver Selection */
1633 if (db->op_mode & 0x10) /* 1M HomePNA */
1634 db->cr6_data |= 0x40000;/* External MII select */
1635 else
1636 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1637
1638 update_cr6(db->cr6_data, db->ioaddr);
1639
1640 /* 10/100M phyxcer force mode need */
1641 if ( !(db->media_mode & 0x18)) {
1642 /* Forece Mode */
1643 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1644 if ( !(phy_reg & 0x1) ) {
1645 /* parter without N-Way capability */
1646 phy_reg = 0x0;
1647 switch(db->op_mode) {
1648 case DMFE_10MHF: phy_reg = 0x0; break;
1649 case DMFE_10MFD: phy_reg = 0x100; break;
1650 case DMFE_100MHF: phy_reg = 0x2000; break;
1651 case DMFE_100MFD: phy_reg = 0x2100; break;
1652 }
1653 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1654 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1655 mdelay(20);
1656 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1657 }
1658 }
1659 }
1660
1661
1662 /*
1663 * Write a word to Phy register
1664 */
1665
1666 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1667 {
1668 u16 i;
1669 unsigned long ioaddr;
1670
1671 if (chip_id == PCI_DM9132_ID) {
1672 ioaddr = iobase + 0x80 + offset * 4;
1673 outw(phy_data, ioaddr);
1674 } else {
1675 /* DM9102/DM9102A Chip */
1676 ioaddr = iobase + DCR9;
1677
1678 /* Send 33 synchronization clock to Phy controller */
1679 for (i = 0; i < 35; i++)
1680 phy_write_1bit(ioaddr, PHY_DATA_1);
1681
1682 /* Send start command(01) to Phy */
1683 phy_write_1bit(ioaddr, PHY_DATA_0);
1684 phy_write_1bit(ioaddr, PHY_DATA_1);
1685
1686 /* Send write command(01) to Phy */
1687 phy_write_1bit(ioaddr, PHY_DATA_0);
1688 phy_write_1bit(ioaddr, PHY_DATA_1);
1689
1690 /* Send Phy address */
1691 for (i = 0x10; i > 0; i = i >> 1)
1692 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1693
1694 /* Send register address */
1695 for (i = 0x10; i > 0; i = i >> 1)
1696 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1697
1698 /* written trasnition */
1699 phy_write_1bit(ioaddr, PHY_DATA_1);
1700 phy_write_1bit(ioaddr, PHY_DATA_0);
1701
1702 /* Write a word data to PHY controller */
1703 for ( i = 0x8000; i > 0; i >>= 1)
1704 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1705 }
1706 }
1707
1708
1709 /*
1710 * Read a word data from phy register
1711 */
1712
1713 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1714 {
1715 int i;
1716 u16 phy_data;
1717 unsigned long ioaddr;
1718
1719 if (chip_id == PCI_DM9132_ID) {
1720 /* DM9132 Chip */
1721 ioaddr = iobase + 0x80 + offset * 4;
1722 phy_data = inw(ioaddr);
1723 } else {
1724 /* DM9102/DM9102A Chip */
1725 ioaddr = iobase + DCR9;
1726
1727 /* Send 33 synchronization clock to Phy controller */
1728 for (i = 0; i < 35; i++)
1729 phy_write_1bit(ioaddr, PHY_DATA_1);
1730
1731 /* Send start command(01) to Phy */
1732 phy_write_1bit(ioaddr, PHY_DATA_0);
1733 phy_write_1bit(ioaddr, PHY_DATA_1);
1734
1735 /* Send read command(10) to Phy */
1736 phy_write_1bit(ioaddr, PHY_DATA_1);
1737 phy_write_1bit(ioaddr, PHY_DATA_0);
1738
1739 /* Send Phy address */
1740 for (i = 0x10; i > 0; i = i >> 1)
1741 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1742
1743 /* Send register address */
1744 for (i = 0x10; i > 0; i = i >> 1)
1745 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1746
1747 /* Skip transition state */
1748 phy_read_1bit(ioaddr);
1749
1750 /* read 16bit data */
1751 for (phy_data = 0, i = 0; i < 16; i++) {
1752 phy_data <<= 1;
1753 phy_data |= phy_read_1bit(ioaddr);
1754 }
1755 }
1756
1757 return phy_data;
1758 }
1759
1760
1761 /*
1762 * Write one bit data to Phy Controller
1763 */
1764
1765 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1766 {
1767 outl(phy_data, ioaddr); /* MII Clock Low */
1768 udelay(1);
1769 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1770 udelay(1);
1771 outl(phy_data, ioaddr); /* MII Clock Low */
1772 udelay(1);
1773 }
1774
1775
1776 /*
1777 * Read one bit phy data from PHY controller
1778 */
1779
1780 static u16 phy_read_1bit(unsigned long ioaddr)
1781 {
1782 u16 phy_data;
1783
1784 outl(0x50000, ioaddr);
1785 udelay(1);
1786 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1787 outl(0x40000, ioaddr);
1788 udelay(1);
1789
1790 return phy_data;
1791 }
1792
1793
1794 /*
1795 * Parser SROM and media mode
1796 */
1797
1798 static void dmfe_parse_srom(struct dmfe_board_info * db)
1799 {
1800 char * srom = db->srom;
1801 int dmfe_mode, tmp_reg;
1802
1803 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1804
1805 /* Init CR15 */
1806 db->cr15_data = CR15_DEFAULT;
1807
1808 /* Check SROM Version */
1809 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1810 /* SROM V4.01 */
1811 /* Get NIC support media mode */
1812 db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2);
1813 db->PHY_reg4 = 0;
1814 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1815 switch( db->NIC_capability & tmp_reg ) {
1816 case 0x1: db->PHY_reg4 |= 0x0020; break;
1817 case 0x2: db->PHY_reg4 |= 0x0040; break;
1818 case 0x4: db->PHY_reg4 |= 0x0080; break;
1819 case 0x8: db->PHY_reg4 |= 0x0100; break;
1820 }
1821 }
1822
1823 /* Media Mode Force or not check */
1824 dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) &
1825 le32_to_cpup((__le32 *)srom + 36/4);
1826 switch(dmfe_mode) {
1827 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1828 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1829 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1830 case 0x100:
1831 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1832 }
1833
1834 /* Special Function setting */
1835 /* VLAN function */
1836 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1837 db->cr15_data |= 0x40;
1838
1839 /* Flow Control */
1840 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1841 db->cr15_data |= 0x400;
1842
1843 /* TX pause packet */
1844 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1845 db->cr15_data |= 0x9800;
1846 }
1847
1848 /* Parse HPNA parameter */
1849 db->HPNA_command = 1;
1850
1851 /* Accept remote command or not */
1852 if (HPNA_rx_cmd == 0)
1853 db->HPNA_command |= 0x8000;
1854
1855 /* Issue remote command & operation mode */
1856 if (HPNA_tx_cmd == 1)
1857 switch(HPNA_mode) { /* Issue Remote Command */
1858 case 0: db->HPNA_command |= 0x0904; break;
1859 case 1: db->HPNA_command |= 0x0a00; break;
1860 case 2: db->HPNA_command |= 0x0506; break;
1861 case 3: db->HPNA_command |= 0x0602; break;
1862 }
1863 else
1864 switch(HPNA_mode) { /* Don't Issue */
1865 case 0: db->HPNA_command |= 0x0004; break;
1866 case 1: db->HPNA_command |= 0x0000; break;
1867 case 2: db->HPNA_command |= 0x0006; break;
1868 case 3: db->HPNA_command |= 0x0002; break;
1869 }
1870
1871 /* Check DM9801 or DM9802 present or not */
1872 db->HPNA_present = 0;
1873 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1874 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1875 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1876 /* DM9801 or DM9802 present */
1877 db->HPNA_timer = 8;
1878 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1879 /* DM9801 HomeRun */
1880 db->HPNA_present = 1;
1881 dmfe_program_DM9801(db, tmp_reg);
1882 } else {
1883 /* DM9802 LongRun */
1884 db->HPNA_present = 2;
1885 dmfe_program_DM9802(db);
1886 }
1887 }
1888
1889 }
1890
1891
1892 /*
1893 * Init HomeRun DM9801
1894 */
1895
1896 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1897 {
1898 uint reg17, reg25;
1899
1900 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1901 switch(HPNA_rev) {
1902 case 0xb900: /* DM9801 E3 */
1903 db->HPNA_command |= 0x1000;
1904 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1905 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1906 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1907 break;
1908 case 0xb901: /* DM9801 E4 */
1909 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1910 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1911 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1912 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1913 break;
1914 case 0xb902: /* DM9801 E5 */
1915 case 0xb903: /* DM9801 E6 */
1916 default:
1917 db->HPNA_command |= 0x1000;
1918 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1919 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1920 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1921 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1922 break;
1923 }
1924 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1925 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1926 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1927 }
1928
1929
1930 /*
1931 * Init HomeRun DM9802
1932 */
1933
1934 static void dmfe_program_DM9802(struct dmfe_board_info * db)
1935 {
1936 uint phy_reg;
1937
1938 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1939 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1940 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1941 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1942 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1943 }
1944
1945
1946 /*
1947 * Check remote HPNA power and speed status. If not correct,
1948 * issue command again.
1949 */
1950
1951 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1952 {
1953 uint phy_reg;
1954
1955 /* Got remote device status */
1956 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1957 switch(phy_reg) {
1958 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1959 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1960 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1961 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1962 }
1963
1964 /* Check remote device status match our setting ot not */
1965 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1966 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1967 db->HPNA_timer=8;
1968 } else
1969 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1970 }
1971
1972
1973
1974 static struct pci_device_id dmfe_pci_tbl[] = {
1975 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1976 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1977 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1978 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1979 { 0, }
1980 };
1981 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1982
1983
1984 static struct pci_driver dmfe_driver = {
1985 .name = "dmfe",
1986 .id_table = dmfe_pci_tbl,
1987 .probe = dmfe_init_one,
1988 .remove = __devexit_p(dmfe_remove_one),
1989 };
1990
1991 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1992 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1993 MODULE_LICENSE("GPL");
1994 MODULE_VERSION(DRV_VERSION);
1995
1996 module_param(debug, int, 0);
1997 module_param(mode, byte, 0);
1998 module_param(cr6set, int, 0);
1999 module_param(chkmode, byte, 0);
2000 module_param(HPNA_mode, byte, 0);
2001 module_param(HPNA_rx_cmd, byte, 0);
2002 module_param(HPNA_tx_cmd, byte, 0);
2003 module_param(HPNA_NoiseFloor, byte, 0);
2004 module_param(SF_mode, byte, 0);
2005 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2006 MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2007 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2008
2009 /* Description:
2010 * when user used insmod to add module, system invoked init_module()
2011 * to initilize and register.
2012 */
2013
2014 static int __init dmfe_init_module(void)
2015 {
2016 int rc;
2017
2018 printk(version);
2019 printed_version = 1;
2020
2021 DMFE_DBUG(0, "init_module() ", debug);
2022
2023 if (debug)
2024 dmfe_debug = debug; /* set debug flag */
2025 if (cr6set)
2026 dmfe_cr6_user_set = cr6set;
2027
2028 switch(mode) {
2029 case DMFE_10MHF:
2030 case DMFE_100MHF:
2031 case DMFE_10MFD:
2032 case DMFE_100MFD:
2033 case DMFE_1M_HPNA:
2034 dmfe_media_mode = mode;
2035 break;
2036 default:dmfe_media_mode = DMFE_AUTO;
2037 break;
2038 }
2039
2040 if (HPNA_mode > 4)
2041 HPNA_mode = 0; /* Default: LP/HS */
2042 if (HPNA_rx_cmd > 1)
2043 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2044 if (HPNA_tx_cmd > 1)
2045 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2046 if (HPNA_NoiseFloor > 15)
2047 HPNA_NoiseFloor = 0;
2048
2049 rc = pci_register_driver(&dmfe_driver);
2050 if (rc < 0)
2051 return rc;
2052
2053 return 0;
2054 }
2055
2056
2057 /*
2058 * Description:
2059 * when user used rmmod to delete module, system invoked clean_module()
2060 * to un-register all registered services.
2061 */
2062
2063 static void __exit dmfe_cleanup_module(void)
2064 {
2065 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2066 pci_unregister_driver(&dmfe_driver);
2067 }
2068
2069 module_init(dmfe_init_module);
2070 module_exit(dmfe_cleanup_module);
linux kernel for loongson