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[ARM] rtc-pcf8583: don't use BCD_TO_BIN/BIN_TO_BCD
[linux-2.6/linux-loongson.git] / drivers / net / tulip / de4x5.c
blob4b3cd3d8b62abba1fa54d93fc4afb7a6666a0e10
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/slab.h>
454 #include <linux/pci.h>
455 #include <linux/eisa.h>
456 #include <linux/delay.h>
457 #include <linux/init.h>
458 #include <linux/spinlock.h>
459 #include <linux/crc32.h>
460 #include <linux/netdevice.h>
461 #include <linux/etherdevice.h>
462 #include <linux/skbuff.h>
463 #include <linux/time.h>
464 #include <linux/types.h>
465 #include <linux/unistd.h>
466 #include <linux/ctype.h>
467 #include <linux/dma-mapping.h>
468 #include <linux/moduleparam.h>
469 #include <linux/bitops.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
483
484 #define c_char const char
485 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 int fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile s32 status;
760 u32 des1;
761 u32 buf;
762 u32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 int fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 int tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff *skb; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 int useSROM; /* For non-DEC card use SROM */
842 int useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
900 static int de4x5_close(struct net_device *dev);
901 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903 static void set_multicast_list(struct net_device *dev);
904 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906 /*
907 ** Private functions
908 */
909 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910 static int de4x5_init(struct net_device *dev);
911 static int de4x5_sw_reset(struct net_device *dev);
912 static int de4x5_rx(struct net_device *dev);
913 static int de4x5_tx(struct net_device *dev);
914 static int de4x5_ast(struct net_device *dev);
915 static int de4x5_txur(struct net_device *dev);
916 static int de4x5_rx_ovfc(struct net_device *dev);
917
918 static int autoconf_media(struct net_device *dev);
919 static void create_packet(struct net_device *dev, char *frame, int len);
920 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921 static int dc21040_autoconf(struct net_device *dev);
922 static int dc21041_autoconf(struct net_device *dev);
923 static int dc21140m_autoconf(struct net_device *dev);
924 static int dc2114x_autoconf(struct net_device *dev);
925 static int srom_autoconf(struct net_device *dev);
926 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929 static int test_for_100Mb(struct net_device *dev, int msec);
930 static int wait_for_link(struct net_device *dev);
931 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
932 static int is_spd_100(struct net_device *dev);
933 static int is_100_up(struct net_device *dev);
934 static int is_10_up(struct net_device *dev);
935 static int is_anc_capable(struct net_device *dev);
936 static int ping_media(struct net_device *dev, int msec);
937 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938 static void de4x5_free_rx_buffs(struct net_device *dev);
939 static void de4x5_free_tx_buffs(struct net_device *dev);
940 static void de4x5_save_skbs(struct net_device *dev);
941 static void de4x5_rst_desc_ring(struct net_device *dev);
942 static void de4x5_cache_state(struct net_device *dev, int flag);
943 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946 static void de4x5_setup_intr(struct net_device *dev);
947 static void de4x5_init_connection(struct net_device *dev);
948 static int de4x5_reset_phy(struct net_device *dev);
949 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951 static int test_tp(struct net_device *dev, s32 msec);
952 static int EISA_signature(char *name, struct device *device);
953 static int PCI_signature(char *name, struct de4x5_private *lp);
954 static void DevicePresent(struct net_device *dev, u_long iobase);
955 static void enet_addr_rst(u_long aprom_addr);
956 static int de4x5_bad_srom(struct de4x5_private *lp);
957 static short srom_rd(u_long address, u_char offset);
958 static void srom_latch(u_int command, u_long address);
959 static void srom_command(u_int command, u_long address);
960 static void srom_address(u_int command, u_long address, u_char offset);
961 static short srom_data(u_int command, u_long address);
962 /*static void srom_busy(u_int command, u_long address);*/
963 static void sendto_srom(u_int command, u_long addr);
964 static int getfrom_srom(u_long addr);
965 static int srom_map_media(struct net_device *dev);
966 static int srom_infoleaf_info(struct net_device *dev);
967 static void srom_init(struct net_device *dev);
968 static void srom_exec(struct net_device *dev, u_char *p);
969 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static int mii_rdata(u_long ioaddr);
972 static void mii_wdata(int data, int len, u_long ioaddr);
973 static void mii_ta(u_long rw, u_long ioaddr);
974 static int mii_swap(int data, int len);
975 static void mii_address(u_char addr, u_long ioaddr);
976 static void sendto_mii(u32 command, int data, u_long ioaddr);
977 static int getfrom_mii(u32 command, u_long ioaddr);
978 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979 static int mii_get_phy(struct net_device *dev);
980 static void SetMulticastFilter(struct net_device *dev);
981 static int get_hw_addr(struct net_device *dev);
982 static void srom_repair(struct net_device *dev, int card);
983 static int test_bad_enet(struct net_device *dev, int status);
984 static int an_exception(struct de4x5_private *lp);
985 static char *build_setup_frame(struct net_device *dev, int mode);
986 static void disable_ast(struct net_device *dev);
987 static void enable_ast(struct net_device *dev, u32 time_out);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
992 static void yawn(struct net_device *dev, int state);
993 static void de4x5_parse_params(struct net_device *dev);
994 static void de4x5_dbg_open(struct net_device *dev);
995 static void de4x5_dbg_mii(struct net_device *dev, int k);
996 static void de4x5_dbg_media(struct net_device *dev);
997 static void de4x5_dbg_srom(struct de4x5_srom *p);
998 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
999 static int de4x5_strncmp(char *a, char *b, int n);
1000 static int dc21041_infoleaf(struct net_device *dev);
1001 static int dc21140_infoleaf(struct net_device *dev);
1002 static int dc21142_infoleaf(struct net_device *dev);
1003 static int dc21143_infoleaf(struct net_device *dev);
1004 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1010 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1011
1012 /*
1013 ** Note now that module autoprobing is allowed under EISA and PCI. The
1014 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1015 ** to "do the right thing".
1016 */
1017
1018 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1019
1020 module_param(io, int, 0);
1021 module_param(de4x5_debug, int, 0);
1022 module_param(dec_only, int, 0);
1023 module_param(args, charp, 0);
1024
1025 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1026 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1027 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1028 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1029 MODULE_LICENSE("GPL");
1030
1031 /*
1032 ** List the SROM infoleaf functions and chipsets
1033 */
1034 struct InfoLeaf {
1035 int chipset;
1036 int (*fn)(struct net_device *);
1037 };
1038 static struct InfoLeaf infoleaf_array[] = {
1039 {DC21041, dc21041_infoleaf},
1040 {DC21140, dc21140_infoleaf},
1041 {DC21142, dc21142_infoleaf},
1042 {DC21143, dc21143_infoleaf}
1043 };
1044 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1045
1046 /*
1047 ** List the SROM info block functions
1048 */
1049 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1050 type0_infoblock,
1051 type1_infoblock,
1052 type2_infoblock,
1053 type3_infoblock,
1054 type4_infoblock,
1055 type5_infoblock,
1056 compact_infoblock
1057 };
1058
1059 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1060
1061 /*
1062 ** Miscellaneous defines...
1063 */
1064 #define RESET_DE4X5 {\
1065 int i;\
1066 i=inl(DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i | BMR_SWR, DE4X5_BMR);\
1069 mdelay(1);\
1070 outl(i, DE4X5_BMR);\
1071 mdelay(1);\
1072 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1073 mdelay(1);\
1074 }
1075
1076 #define PHY_HARD_RESET {\
1077 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1078 mdelay(1); /* Assert for 1ms */\
1079 outl(0x00, DE4X5_GEP);\
1080 mdelay(2); /* Wait for 2ms */\
1081 }
1082
1083
1084 static int __devinit
1085 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1086 {
1087 char name[DE4X5_NAME_LENGTH + 1];
1088 struct de4x5_private *lp = netdev_priv(dev);
1089 struct pci_dev *pdev = NULL;
1090 int i, status=0;
1091
1092 gendev->driver_data = dev;
1093
1094 /* Ensure we're not sleeping */
1095 if (lp->bus == EISA) {
1096 outb(WAKEUP, PCI_CFPM);
1097 } else {
1098 pdev = to_pci_dev (gendev);
1099 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1100 }
1101 mdelay(10);
1102
1103 RESET_DE4X5;
1104
1105 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1106 return -ENXIO; /* Hardware could not reset */
1107 }
1108
1109 /*
1110 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1111 */
1112 lp->useSROM = FALSE;
1113 if (lp->bus == PCI) {
1114 PCI_signature(name, lp);
1115 } else {
1116 EISA_signature(name, gendev);
1117 }
1118
1119 if (*name == '\0') { /* Not found a board signature */
1120 return -ENXIO;
1121 }
1122
1123 dev->base_addr = iobase;
1124 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1125
1126 printk(", h/w address ");
1127 status = get_hw_addr(dev);
1128 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1129 printk("%2.2x:", dev->dev_addr[i]);
1130 }
1131 printk("%2.2x,\n", dev->dev_addr[i]);
1132
1133 if (status != 0) {
1134 printk(" which has an Ethernet PROM CRC error.\n");
1135 return -ENXIO;
1136 } else {
1137 lp->cache.gepc = GEP_INIT;
1138 lp->asBit = GEP_SLNK;
1139 lp->asPolarity = GEP_SLNK;
1140 lp->asBitValid = TRUE;
1141 lp->timeout = -1;
1142 lp->gendev = gendev;
1143 spin_lock_init(&lp->lock);
1144 init_timer(&lp->timer);
1145 de4x5_parse_params(dev);
1146
1147 /*
1148 ** Choose correct autosensing in case someone messed up
1149 */
1150 lp->autosense = lp->params.autosense;
1151 if (lp->chipset != DC21140) {
1152 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1153 lp->params.autosense = TP;
1154 }
1155 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1156 lp->params.autosense = BNC;
1157 }
1158 }
1159 lp->fdx = lp->params.fdx;
1160 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1161
1162 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1163 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1164 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1165 #endif
1166 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1167 &lp->dma_rings, GFP_ATOMIC);
1168 if (lp->rx_ring == NULL) {
1169 return -ENOMEM;
1170 }
1171
1172 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1173
1174 /*
1175 ** Set up the RX descriptor ring (Intels)
1176 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1177 */
1178 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1179 for (i=0; i<NUM_RX_DESC; i++) {
1180 lp->rx_ring[i].status = 0;
1181 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1182 lp->rx_ring[i].buf = 0;
1183 lp->rx_ring[i].next = 0;
1184 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1185 }
1186
1187 #else
1188 {
1189 dma_addr_t dma_rx_bufs;
1190
1191 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1192 * sizeof(struct de4x5_desc);
1193 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1194 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1195 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1196 for (i=0; i<NUM_RX_DESC; i++) {
1197 lp->rx_ring[i].status = 0;
1198 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1199 lp->rx_ring[i].buf =
1200 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1201 lp->rx_ring[i].next = 0;
1202 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1203 }
1204
1205 }
1206 #endif
1207
1208 barrier();
1209
1210 lp->rxRingSize = NUM_RX_DESC;
1211 lp->txRingSize = NUM_TX_DESC;
1212
1213 /* Write the end of list marker to the descriptor lists */
1214 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1215 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1216
1217 /* Tell the adapter where the TX/RX rings are located. */
1218 outl(lp->dma_rings, DE4X5_RRBA);
1219 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1220 DE4X5_TRBA);
1221
1222 /* Initialise the IRQ mask and Enable/Disable */
1223 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1224 lp->irq_en = IMR_NIM | IMR_AIM;
1225
1226 /* Create a loopback packet frame for later media probing */
1227 create_packet(dev, lp->frame, sizeof(lp->frame));
1228
1229 /* Check if the RX overflow bug needs testing for */
1230 i = lp->cfrv & 0x000000fe;
1231 if ((lp->chipset == DC21140) && (i == 0x20)) {
1232 lp->rx_ovf = 1;
1233 }
1234
1235 /* Initialise the SROM pointers if possible */
1236 if (lp->useSROM) {
1237 lp->state = INITIALISED;
1238 if (srom_infoleaf_info(dev)) {
1239 dma_free_coherent (gendev, lp->dma_size,
1240 lp->rx_ring, lp->dma_rings);
1241 return -ENXIO;
1242 }
1243 srom_init(dev);
1244 }
1245
1246 lp->state = CLOSED;
1247
1248 /*
1249 ** Check for an MII interface
1250 */
1251 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1252 mii_get_phy(dev);
1253 }
1254
1255 #ifndef __sparc_v9__
1256 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1257 #else
1258 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1259 #endif
1260 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1261 }
1262
1263 if (de4x5_debug & DEBUG_VERSION) {
1264 printk(version);
1265 }
1266
1267 /* The DE4X5-specific entries in the device structure. */
1268 SET_MODULE_OWNER(dev);
1269 SET_NETDEV_DEV(dev, gendev);
1270 dev->open = &de4x5_open;
1271 dev->hard_start_xmit = &de4x5_queue_pkt;
1272 dev->stop = &de4x5_close;
1273 dev->get_stats = &de4x5_get_stats;
1274 dev->set_multicast_list = &set_multicast_list;
1275 dev->do_ioctl = &de4x5_ioctl;
1276
1277 dev->mem_start = 0;
1278
1279 /* Fill in the generic fields of the device structure. */
1280 if ((status = register_netdev (dev))) {
1281 dma_free_coherent (gendev, lp->dma_size,
1282 lp->rx_ring, lp->dma_rings);
1283 return status;
1284 }
1285
1286 /* Let the adapter sleep to save power */
1287 yawn(dev, SLEEP);
1288
1289 return status;
1290 }
1291
1292
1293 static int
1294 de4x5_open(struct net_device *dev)
1295 {
1296 struct de4x5_private *lp = netdev_priv(dev);
1297 u_long iobase = dev->base_addr;
1298 int i, status = 0;
1299 s32 omr;
1300
1301 /* Allocate the RX buffers */
1302 for (i=0; i<lp->rxRingSize; i++) {
1303 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1304 de4x5_free_rx_buffs(dev);
1305 return -EAGAIN;
1306 }
1307 }
1308
1309 /*
1310 ** Wake up the adapter
1311 */
1312 yawn(dev, WAKEUP);
1313
1314 /*
1315 ** Re-initialize the DE4X5...
1316 */
1317 status = de4x5_init(dev);
1318 spin_lock_init(&lp->lock);
1319 lp->state = OPEN;
1320 de4x5_dbg_open(dev);
1321
1322 if (request_irq(dev->irq, (void *)de4x5_interrupt, IRQF_SHARED,
1323 lp->adapter_name, dev)) {
1324 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1325 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1326 lp->adapter_name, dev)) {
1327 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1328 disable_ast(dev);
1329 de4x5_free_rx_buffs(dev);
1330 de4x5_free_tx_buffs(dev);
1331 yawn(dev, SLEEP);
1332 lp->state = CLOSED;
1333 return -EAGAIN;
1334 } else {
1335 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1336 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1337 }
1338 }
1339
1340 lp->interrupt = UNMASK_INTERRUPTS;
1341 dev->trans_start = jiffies;
1342
1343 START_DE4X5;
1344
1345 de4x5_setup_intr(dev);
1346
1347 if (de4x5_debug & DEBUG_OPEN) {
1348 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1349 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1350 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1351 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1352 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1353 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1354 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1355 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1356 }
1357
1358 return status;
1359 }
1360
1361 /*
1362 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1363 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1364 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1365 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1366 ** to be data corruption problems if it is larger (UDP errors seen from a
1367 ** ttcp source).
1368 */
1369 static int
1370 de4x5_init(struct net_device *dev)
1371 {
1372 /* Lock out other processes whilst setting up the hardware */
1373 netif_stop_queue(dev);
1374
1375 de4x5_sw_reset(dev);
1376
1377 /* Autoconfigure the connected port */
1378 autoconf_media(dev);
1379
1380 return 0;
1381 }
1382
1383 static int
1384 de4x5_sw_reset(struct net_device *dev)
1385 {
1386 struct de4x5_private *lp = netdev_priv(dev);
1387 u_long iobase = dev->base_addr;
1388 int i, j, status = 0;
1389 s32 bmr, omr;
1390
1391 /* Select the MII or SRL port now and RESET the MAC */
1392 if (!lp->useSROM) {
1393 if (lp->phy[lp->active].id != 0) {
1394 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1395 } else {
1396 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1397 }
1398 de4x5_switch_mac_port(dev);
1399 }
1400
1401 /*
1402 ** Set the programmable burst length to 8 longwords for all the DC21140
1403 ** Fasternet chips and 4 longwords for all others: DMA errors result
1404 ** without these values. Cache align 16 long.
1405 */
1406 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1407 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1408 outl(bmr, DE4X5_BMR);
1409
1410 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1411 if (lp->chipset == DC21140) {
1412 omr |= (OMR_SDP | OMR_SB);
1413 }
1414 lp->setup_f = PERFECT;
1415 outl(lp->dma_rings, DE4X5_RRBA);
1416 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1417 DE4X5_TRBA);
1418
1419 lp->rx_new = lp->rx_old = 0;
1420 lp->tx_new = lp->tx_old = 0;
1421
1422 for (i = 0; i < lp->rxRingSize; i++) {
1423 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1424 }
1425
1426 for (i = 0; i < lp->txRingSize; i++) {
1427 lp->tx_ring[i].status = cpu_to_le32(0);
1428 }
1429
1430 barrier();
1431
1432 /* Build the setup frame depending on filtering mode */
1433 SetMulticastFilter(dev);
1434
1435 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1436 outl(omr|OMR_ST, DE4X5_OMR);
1437
1438 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1439
1440 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1441 mdelay(1);
1442 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1443 }
1444 outl(omr, DE4X5_OMR); /* Stop everything! */
1445
1446 if (j == 0) {
1447 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1448 inl(DE4X5_STS));
1449 status = -EIO;
1450 }
1451
1452 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1453 lp->tx_old = lp->tx_new;
1454
1455 return status;
1456 }
1457
1458 /*
1459 ** Writes a socket buffer address to the next available transmit descriptor.
1460 */
1461 static int
1462 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1463 {
1464 struct de4x5_private *lp = netdev_priv(dev);
1465 u_long iobase = dev->base_addr;
1466 int status = 0;
1467 u_long flags = 0;
1468
1469 netif_stop_queue(dev);
1470 if (lp->tx_enable == NO) { /* Cannot send for now */
1471 return -1;
1472 }
1473
1474 /*
1475 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1476 ** interrupts are lost by delayed descriptor status updates relative to
1477 ** the irq assertion, especially with a busy PCI bus.
1478 */
1479 spin_lock_irqsave(&lp->lock, flags);
1480 de4x5_tx(dev);
1481 spin_unlock_irqrestore(&lp->lock, flags);
1482
1483 /* Test if cache is already locked - requeue skb if so */
1484 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1485 return -1;
1486
1487 /* Transmit descriptor ring full or stale skb */
1488 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1489 if (lp->interrupt) {
1490 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1491 } else {
1492 de4x5_put_cache(dev, skb);
1493 }
1494 if (de4x5_debug & DEBUG_TX) {
1495 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1496 }
1497 } else if (skb->len > 0) {
1498 /* If we already have stuff queued locally, use that first */
1499 if (lp->cache.skb && !lp->interrupt) {
1500 de4x5_put_cache(dev, skb);
1501 skb = de4x5_get_cache(dev);
1502 }
1503
1504 while (skb && !netif_queue_stopped(dev) &&
1505 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1506 spin_lock_irqsave(&lp->lock, flags);
1507 netif_stop_queue(dev);
1508 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1509 lp->stats.tx_bytes += skb->len;
1510 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1511
1512 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1513 dev->trans_start = jiffies;
1514
1515 if (TX_BUFFS_AVAIL) {
1516 netif_start_queue(dev); /* Another pkt may be queued */
1517 }
1518 skb = de4x5_get_cache(dev);
1519 spin_unlock_irqrestore(&lp->lock, flags);
1520 }
1521 if (skb) de4x5_putb_cache(dev, skb);
1522 }
1523
1524 lp->cache.lock = 0;
1525
1526 return status;
1527 }
1528
1529 /*
1530 ** The DE4X5 interrupt handler.
1531 **
1532 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1533 ** so that the asserted interrupt always has some real data to work with -
1534 ** if these I/O accesses are ever changed to memory accesses, ensure the
1535 ** STS write is read immediately to complete the transaction if the adapter
1536 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1537 ** is high and descriptor status bits cannot be set before the associated
1538 ** interrupt is asserted and this routine entered.
1539 */
1540 static irqreturn_t
1541 de4x5_interrupt(int irq, void *dev_id)
1542 {
1543 struct net_device *dev = dev_id;
1544 struct de4x5_private *lp;
1545 s32 imr, omr, sts, limit;
1546 u_long iobase;
1547 unsigned int handled = 0;
1548
1549 lp = netdev_priv(dev);
1550 spin_lock(&lp->lock);
1551 iobase = dev->base_addr;
1552
1553 DISABLE_IRQs; /* Ensure non re-entrancy */
1554
1555 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1556 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1557
1558 synchronize_irq(dev->irq);
1559
1560 for (limit=0; limit<8; limit++) {
1561 sts = inl(DE4X5_STS); /* Read IRQ status */
1562 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1563
1564 if (!(sts & lp->irq_mask)) break;/* All done */
1565 handled = 1;
1566
1567 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1568 de4x5_rx(dev);
1569
1570 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1571 de4x5_tx(dev);
1572
1573 if (sts & STS_LNF) { /* TP Link has failed */
1574 lp->irq_mask &= ~IMR_LFM;
1575 }
1576
1577 if (sts & STS_UNF) { /* Transmit underrun */
1578 de4x5_txur(dev);
1579 }
1580
1581 if (sts & STS_SE) { /* Bus Error */
1582 STOP_DE4X5;
1583 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1584 dev->name, sts);
1585 spin_unlock(&lp->lock);
1586 return IRQ_HANDLED;
1587 }
1588 }
1589
1590 /* Load the TX ring with any locally stored packets */
1591 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1592 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1593 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1594 }
1595 lp->cache.lock = 0;
1596 }
1597
1598 lp->interrupt = UNMASK_INTERRUPTS;
1599 ENABLE_IRQs;
1600 spin_unlock(&lp->lock);
1601
1602 return IRQ_RETVAL(handled);
1603 }
1604
1605 static int
1606 de4x5_rx(struct net_device *dev)
1607 {
1608 struct de4x5_private *lp = netdev_priv(dev);
1609 u_long iobase = dev->base_addr;
1610 int entry;
1611 s32 status;
1612
1613 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1614 entry=lp->rx_new) {
1615 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1616
1617 if (lp->rx_ovf) {
1618 if (inl(DE4X5_MFC) & MFC_FOCM) {
1619 de4x5_rx_ovfc(dev);
1620 break;
1621 }
1622 }
1623
1624 if (status & RD_FS) { /* Remember the start of frame */
1625 lp->rx_old = entry;
1626 }
1627
1628 if (status & RD_LS) { /* Valid frame status */
1629 if (lp->tx_enable) lp->linkOK++;
1630 if (status & RD_ES) { /* There was an error. */
1631 lp->stats.rx_errors++; /* Update the error stats. */
1632 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1633 if (status & RD_CE) lp->stats.rx_crc_errors++;
1634 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1635 if (status & RD_TL) lp->stats.rx_length_errors++;
1636 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1637 if (status & RD_CS) lp->pktStats.rx_collision++;
1638 if (status & RD_DB) lp->pktStats.rx_dribble++;
1639 if (status & RD_OF) lp->pktStats.rx_overflow++;
1640 } else { /* A valid frame received */
1641 struct sk_buff *skb;
1642 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1643 >> 16) - 4;
1644
1645 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1646 printk("%s: Insufficient memory; nuking packet.\n",
1647 dev->name);
1648 lp->stats.rx_dropped++;
1649 } else {
1650 de4x5_dbg_rx(skb, pkt_len);
1651
1652 /* Push up the protocol stack */
1653 skb->protocol=eth_type_trans(skb,dev);
1654 de4x5_local_stats(dev, skb->data, pkt_len);
1655 netif_rx(skb);
1656
1657 /* Update stats */
1658 dev->last_rx = jiffies;
1659 lp->stats.rx_packets++;
1660 lp->stats.rx_bytes += pkt_len;
1661 }
1662 }
1663
1664 /* Change buffer ownership for this frame, back to the adapter */
1665 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1666 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1667 barrier();
1668 }
1669 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1670 barrier();
1671 }
1672
1673 /*
1674 ** Update entry information
1675 */
1676 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1677 }
1678
1679 return 0;
1680 }
1681
1682 static inline void
1683 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1684 {
1685 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1686 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1687 DMA_TO_DEVICE);
1688 if ((u_long) lp->tx_skb[entry] > 1)
1689 dev_kfree_skb_irq(lp->tx_skb[entry]);
1690 lp->tx_skb[entry] = NULL;
1691 }
1692
1693 /*
1694 ** Buffer sent - check for TX buffer errors.
1695 */
1696 static int
1697 de4x5_tx(struct net_device *dev)
1698 {
1699 struct de4x5_private *lp = netdev_priv(dev);
1700 u_long iobase = dev->base_addr;
1701 int entry;
1702 s32 status;
1703
1704 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1705 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1706 if (status < 0) { /* Buffer not sent yet */
1707 break;
1708 } else if (status != 0x7fffffff) { /* Not setup frame */
1709 if (status & TD_ES) { /* An error happened */
1710 lp->stats.tx_errors++;
1711 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1712 if (status & TD_LC) lp->stats.tx_window_errors++;
1713 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1714 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1715 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1716
1717 if (TX_PKT_PENDING) {
1718 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1719 }
1720 } else { /* Packet sent */
1721 lp->stats.tx_packets++;
1722 if (lp->tx_enable) lp->linkOK++;
1723 }
1724 /* Update the collision counter */
1725 lp->stats.collisions += ((status & TD_EC) ? 16 :
1726 ((status & TD_CC) >> 3));
1727
1728 /* Free the buffer. */
1729 if (lp->tx_skb[entry] != NULL)
1730 de4x5_free_tx_buff(lp, entry);
1731 }
1732
1733 /* Update all the pointers */
1734 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1735 }
1736
1737 /* Any resources available? */
1738 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1739 if (lp->interrupt)
1740 netif_wake_queue(dev);
1741 else
1742 netif_start_queue(dev);
1743 }
1744
1745 return 0;
1746 }
1747
1748 static int
1749 de4x5_ast(struct net_device *dev)
1750 {
1751 struct de4x5_private *lp = netdev_priv(dev);
1752 int next_tick = DE4X5_AUTOSENSE_MS;
1753
1754 disable_ast(dev);
1755
1756 if (lp->useSROM) {
1757 next_tick = srom_autoconf(dev);
1758 } else if (lp->chipset == DC21140) {
1759 next_tick = dc21140m_autoconf(dev);
1760 } else if (lp->chipset == DC21041) {
1761 next_tick = dc21041_autoconf(dev);
1762 } else if (lp->chipset == DC21040) {
1763 next_tick = dc21040_autoconf(dev);
1764 }
1765 lp->linkOK = 0;
1766 enable_ast(dev, next_tick);
1767
1768 return 0;
1769 }
1770
1771 static int
1772 de4x5_txur(struct net_device *dev)
1773 {
1774 struct de4x5_private *lp = netdev_priv(dev);
1775 u_long iobase = dev->base_addr;
1776 int omr;
1777
1778 omr = inl(DE4X5_OMR);
1779 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1780 omr &= ~(OMR_ST|OMR_SR);
1781 outl(omr, DE4X5_OMR);
1782 while (inl(DE4X5_STS) & STS_TS);
1783 if ((omr & OMR_TR) < OMR_TR) {
1784 omr += 0x4000;
1785 } else {
1786 omr |= OMR_SF;
1787 }
1788 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1789 }
1790
1791 return 0;
1792 }
1793
1794 static int
1795 de4x5_rx_ovfc(struct net_device *dev)
1796 {
1797 struct de4x5_private *lp = netdev_priv(dev);
1798 u_long iobase = dev->base_addr;
1799 int omr;
1800
1801 omr = inl(DE4X5_OMR);
1802 outl(omr & ~OMR_SR, DE4X5_OMR);
1803 while (inl(DE4X5_STS) & STS_RS);
1804
1805 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1806 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1807 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1808 }
1809
1810 outl(omr, DE4X5_OMR);
1811
1812 return 0;
1813 }
1814
1815 static int
1816 de4x5_close(struct net_device *dev)
1817 {
1818 struct de4x5_private *lp = netdev_priv(dev);
1819 u_long iobase = dev->base_addr;
1820 s32 imr, omr;
1821
1822 disable_ast(dev);
1823
1824 netif_stop_queue(dev);
1825
1826 if (de4x5_debug & DEBUG_CLOSE) {
1827 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1828 dev->name, inl(DE4X5_STS));
1829 }
1830
1831 /*
1832 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1833 */
1834 DISABLE_IRQs;
1835 STOP_DE4X5;
1836
1837 /* Free the associated irq */
1838 free_irq(dev->irq, dev);
1839 lp->state = CLOSED;
1840
1841 /* Free any socket buffers */
1842 de4x5_free_rx_buffs(dev);
1843 de4x5_free_tx_buffs(dev);
1844
1845 /* Put the adapter to sleep to save power */
1846 yawn(dev, SLEEP);
1847
1848 return 0;
1849 }
1850
1851 static struct net_device_stats *
1852 de4x5_get_stats(struct net_device *dev)
1853 {
1854 struct de4x5_private *lp = netdev_priv(dev);
1855 u_long iobase = dev->base_addr;
1856
1857 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1858
1859 return &lp->stats;
1860 }
1861
1862 static void
1863 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1864 {
1865 struct de4x5_private *lp = netdev_priv(dev);
1866 int i;
1867
1868 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1869 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1870 lp->pktStats.bins[i]++;
1871 i = DE4X5_PKT_STAT_SZ;
1872 }
1873 }
1874 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1875 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1876 lp->pktStats.broadcast++;
1877 } else {
1878 lp->pktStats.multicast++;
1879 }
1880 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1881 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1882 lp->pktStats.unicast++;
1883 }
1884
1885 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1886 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1887 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1888 }
1889
1890 return;
1891 }
1892
1893 /*
1894 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1895 ** If the flag is changed on a descriptor that is being read by the hardware,
1896 ** I assume PCI transaction ordering will mean you are either successful or
1897 ** just miss asserting the change to the hardware. Anyway you're messing with
1898 ** a descriptor you don't own, but this shouldn't kill the chip provided
1899 ** the descriptor register is read only to the hardware.
1900 */
1901 static void
1902 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1903 {
1904 struct de4x5_private *lp = netdev_priv(dev);
1905 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1906 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1907
1908 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1909 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1910 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1911 lp->tx_skb[lp->tx_new] = skb;
1912 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1913 barrier();
1914
1915 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1916 barrier();
1917 }
1918
1919 /*
1920 ** Set or clear the multicast filter for this adaptor.
1921 */
1922 static void
1923 set_multicast_list(struct net_device *dev)
1924 {
1925 struct de4x5_private *lp = netdev_priv(dev);
1926 u_long iobase = dev->base_addr;
1927
1928 /* First, double check that the adapter is open */
1929 if (lp->state == OPEN) {
1930 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1931 u32 omr;
1932 omr = inl(DE4X5_OMR);
1933 omr |= OMR_PR;
1934 outl(omr, DE4X5_OMR);
1935 } else {
1936 SetMulticastFilter(dev);
1937 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1938 SETUP_FRAME_LEN, (struct sk_buff *)1);
1939
1940 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1941 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1942 dev->trans_start = jiffies;
1943 }
1944 }
1945 }
1946
1947 /*
1948 ** Calculate the hash code and update the logical address filter
1949 ** from a list of ethernet multicast addresses.
1950 ** Little endian crc one liner from Matt Thomas, DEC.
1951 */
1952 static void
1953 SetMulticastFilter(struct net_device *dev)
1954 {
1955 struct de4x5_private *lp = netdev_priv(dev);
1956 struct dev_mc_list *dmi=dev->mc_list;
1957 u_long iobase = dev->base_addr;
1958 int i, j, bit, byte;
1959 u16 hashcode;
1960 u32 omr, crc;
1961 char *pa;
1962 unsigned char *addrs;
1963
1964 omr = inl(DE4X5_OMR);
1965 omr &= ~(OMR_PR | OMR_PM);
1966 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1967
1968 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1969 omr |= OMR_PM; /* Pass all multicasts */
1970 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1971 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1972 addrs=dmi->dmi_addr;
1973 dmi=dmi->next;
1974 if ((*addrs & 0x01) == 1) { /* multicast address? */
1975 crc = ether_crc_le(ETH_ALEN, addrs);
1976 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1977
1978 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1979 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1980
1981 byte <<= 1; /* calc offset into setup frame */
1982 if (byte & 0x02) {
1983 byte -= 1;
1984 }
1985 lp->setup_frame[byte] |= bit;
1986 }
1987 }
1988 } else { /* Perfect filtering */
1989 for (j=0; j<dev->mc_count; j++) {
1990 addrs=dmi->dmi_addr;
1991 dmi=dmi->next;
1992 for (i=0; i<ETH_ALEN; i++) {
1993 *(pa + (i&1)) = *addrs++;
1994 if (i & 0x01) pa += 4;
1995 }
1996 }
1997 }
1998 outl(omr, DE4X5_OMR);
1999
2000 return;
2001 }
2002
2003 #ifdef CONFIG_EISA
2004
2005 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2006
2007 static int __init de4x5_eisa_probe (struct device *gendev)
2008 {
2009 struct eisa_device *edev;
2010 u_long iobase;
2011 u_char irq, regval;
2012 u_short vendor;
2013 u32 cfid;
2014 int status, device;
2015 struct net_device *dev;
2016 struct de4x5_private *lp;
2017
2018 edev = to_eisa_device (gendev);
2019 iobase = edev->base_addr;
2020
2021 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2022 return -EBUSY;
2023
2024 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2025 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2026 status = -EBUSY;
2027 goto release_reg_1;
2028 }
2029
2030 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2031 status = -ENOMEM;
2032 goto release_reg_2;
2033 }
2034 lp = netdev_priv(dev);
2035
2036 cfid = (u32) inl(PCI_CFID);
2037 lp->cfrv = (u_short) inl(PCI_CFRV);
2038 device = (cfid >> 8) & 0x00ffff00;
2039 vendor = (u_short) cfid;
2040
2041 /* Read the EISA Configuration Registers */
2042 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2043 #ifdef CONFIG_ALPHA
2044 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2045 * care about the EISA configuration, and thus doesn't
2046 * configure the PLX bridge properly. Oh well... Simply mimic
2047 * the EISA config file to sort it out. */
2048
2049 /* EISA REG1: Assert DecChip 21040 HW Reset */
2050 outb (ER1_IAM | 1, EISA_REG1);
2051 mdelay (1);
2052
2053 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2054 outb (ER1_IAM, EISA_REG1);
2055 mdelay (1);
2056
2057 /* EISA REG3: R/W Burst Transfer Enable */
2058 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2059
2060 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2061 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2062 #endif
2063 irq = de4x5_irq[(regval >> 1) & 0x03];
2064
2065 if (is_DC2114x) {
2066 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2067 }
2068 lp->chipset = device;
2069 lp->bus = EISA;
2070
2071 /* Write the PCI Configuration Registers */
2072 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2073 outl(0x00006000, PCI_CFLT);
2074 outl(iobase, PCI_CBIO);
2075
2076 DevicePresent(dev, EISA_APROM);
2077
2078 dev->irq = irq;
2079
2080 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2081 return 0;
2082 }
2083
2084 free_netdev (dev);
2085 release_reg_2:
2086 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2087 release_reg_1:
2088 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2089
2090 return status;
2091 }
2092
2093 static int __devexit de4x5_eisa_remove (struct device *device)
2094 {
2095 struct net_device *dev;
2096 u_long iobase;
2097
2098 dev = device->driver_data;
2099 iobase = dev->base_addr;
2100
2101 unregister_netdev (dev);
2102 free_netdev (dev);
2103 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2104 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2105
2106 return 0;
2107 }
2108
2109 static struct eisa_device_id de4x5_eisa_ids[] = {
2110 { "DEC4250", 0 }, /* 0 is the board name index... */
2111 { "" }
2112 };
2113 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2114
2115 static struct eisa_driver de4x5_eisa_driver = {
2116 .id_table = de4x5_eisa_ids,
2117 .driver = {
2118 .name = "de4x5",
2119 .probe = de4x5_eisa_probe,
2120 .remove = __devexit_p (de4x5_eisa_remove),
2121 }
2122 };
2123 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2124 #endif
2125
2126 #ifdef CONFIG_PCI
2127
2128 /*
2129 ** This function searches the current bus (which is >0) for a DECchip with an
2130 ** SROM, so that in multiport cards that have one SROM shared between multiple
2131 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2132 ** For single port cards this is a time waster...
2133 */
2134 static void __devinit
2135 srom_search(struct net_device *dev, struct pci_dev *pdev)
2136 {
2137 u_char pb;
2138 u_short vendor, status;
2139 u_int irq = 0, device;
2140 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2141 int i, j, cfrv;
2142 struct de4x5_private *lp = netdev_priv(dev);
2143 struct list_head *walk;
2144
2145 list_for_each(walk, &pdev->bus_list) {
2146 struct pci_dev *this_dev = pci_dev_b(walk);
2147
2148 /* Skip the pci_bus list entry */
2149 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2150
2151 vendor = this_dev->vendor;
2152 device = this_dev->device << 8;
2153 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2154
2155 /* Get the chip configuration revision register */
2156 pb = this_dev->bus->number;
2157 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2158
2159 /* Set the device number information */
2160 lp->device = PCI_SLOT(this_dev->devfn);
2161 lp->bus_num = pb;
2162
2163 /* Set the chipset information */
2164 if (is_DC2114x) {
2165 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2166 }
2167 lp->chipset = device;
2168
2169 /* Get the board I/O address (64 bits on sparc64) */
2170 iobase = pci_resource_start(this_dev, 0);
2171
2172 /* Fetch the IRQ to be used */
2173 irq = this_dev->irq;
2174 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2175
2176 /* Check if I/O accesses are enabled */
2177 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2178 if (!(status & PCI_COMMAND_IO)) continue;
2179
2180 /* Search for a valid SROM attached to this DECchip */
2181 DevicePresent(dev, DE4X5_APROM);
2182 for (j=0, i=0; i<ETH_ALEN; i++) {
2183 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2184 }
2185 if ((j != 0) && (j != 0x5fa)) {
2186 last.chipset = device;
2187 last.bus = pb;
2188 last.irq = irq;
2189 for (i=0; i<ETH_ALEN; i++) {
2190 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2191 }
2192 return;
2193 }
2194 }
2195
2196 return;
2197 }
2198
2199 /*
2200 ** PCI bus I/O device probe
2201 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2202 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2203 ** enabled by the user first in the set up utility. Hence we just check for
2204 ** enabled features and silently ignore the card if they're not.
2205 **
2206 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2207 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2208 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2209 ** PC doesn't conform to the PCI standard)!
2210 **
2211 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2212 ** kernels use the V0.535[n] drivers.
2213 */
2214
2215 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2216 const struct pci_device_id *ent)
2217 {
2218 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2219 u_short vendor, status;
2220 u_int irq = 0, device;
2221 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2222 int error;
2223 struct net_device *dev;
2224 struct de4x5_private *lp;
2225
2226 dev_num = PCI_SLOT(pdev->devfn);
2227 pb = pdev->bus->number;
2228
2229 if (io) { /* probe a single PCI device */
2230 pbus = (u_short)(io >> 8);
2231 dnum = (u_short)(io & 0xff);
2232 if ((pbus != pb) || (dnum != dev_num))
2233 return -ENODEV;
2234 }
2235
2236 vendor = pdev->vendor;
2237 device = pdev->device << 8;
2238 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2239 return -ENODEV;
2240
2241 /* Ok, the device seems to be for us. */
2242 if ((error = pci_enable_device (pdev)))
2243 return error;
2244
2245 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2246 error = -ENOMEM;
2247 goto disable_dev;
2248 }
2249
2250 lp = netdev_priv(dev);
2251 lp->bus = PCI;
2252 lp->bus_num = 0;
2253
2254 /* Search for an SROM on this bus */
2255 if (lp->bus_num != pb) {
2256 lp->bus_num = pb;
2257 srom_search(dev, pdev);
2258 }
2259
2260 /* Get the chip configuration revision register */
2261 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2262
2263 /* Set the device number information */
2264 lp->device = dev_num;
2265 lp->bus_num = pb;
2266
2267 /* Set the chipset information */
2268 if (is_DC2114x) {
2269 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2270 }
2271 lp->chipset = device;
2272
2273 /* Get the board I/O address (64 bits on sparc64) */
2274 iobase = pci_resource_start(pdev, 0);
2275
2276 /* Fetch the IRQ to be used */
2277 irq = pdev->irq;
2278 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2279 error = -ENODEV;
2280 goto free_dev;
2281 }
2282
2283 /* Check if I/O accesses and Bus Mastering are enabled */
2284 pci_read_config_word(pdev, PCI_COMMAND, &status);
2285 #ifdef __powerpc__
2286 if (!(status & PCI_COMMAND_IO)) {
2287 status |= PCI_COMMAND_IO;
2288 pci_write_config_word(pdev, PCI_COMMAND, status);
2289 pci_read_config_word(pdev, PCI_COMMAND, &status);
2290 }
2291 #endif /* __powerpc__ */
2292 if (!(status & PCI_COMMAND_IO)) {
2293 error = -ENODEV;
2294 goto free_dev;
2295 }
2296
2297 if (!(status & PCI_COMMAND_MASTER)) {
2298 status |= PCI_COMMAND_MASTER;
2299 pci_write_config_word(pdev, PCI_COMMAND, status);
2300 pci_read_config_word(pdev, PCI_COMMAND, &status);
2301 }
2302 if (!(status & PCI_COMMAND_MASTER)) {
2303 error = -ENODEV;
2304 goto free_dev;
2305 }
2306
2307 /* Check the latency timer for values >= 0x60 */
2308 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2309 if (timer < 0x60) {
2310 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2311 }
2312
2313 DevicePresent(dev, DE4X5_APROM);
2314
2315 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2316 error = -EBUSY;
2317 goto free_dev;
2318 }
2319
2320 dev->irq = irq;
2321
2322 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2323 goto release;
2324 }
2325
2326 return 0;
2327
2328 release:
2329 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2330 free_dev:
2331 free_netdev (dev);
2332 disable_dev:
2333 pci_disable_device (pdev);
2334 return error;
2335 }
2336
2337 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2338 {
2339 struct net_device *dev;
2340 u_long iobase;
2341
2342 dev = pdev->dev.driver_data;
2343 iobase = dev->base_addr;
2344
2345 unregister_netdev (dev);
2346 free_netdev (dev);
2347 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2348 pci_disable_device (pdev);
2349 }
2350
2351 static struct pci_device_id de4x5_pci_tbl[] = {
2352 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2354 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2356 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2358 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2360 { },
2361 };
2362
2363 static struct pci_driver de4x5_pci_driver = {
2364 .name = "de4x5",
2365 .id_table = de4x5_pci_tbl,
2366 .probe = de4x5_pci_probe,
2367 .remove = __devexit_p (de4x5_pci_remove),
2368 };
2369
2370 #endif
2371
2372 /*
2373 ** Auto configure the media here rather than setting the port at compile
2374 ** time. This routine is called by de4x5_init() and when a loss of media is
2375 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2376 ** [TP] or no recent receive activity) to check whether the user has been
2377 ** sneaky and changed the port on us.
2378 */
2379 static int
2380 autoconf_media(struct net_device *dev)
2381 {
2382 struct de4x5_private *lp = netdev_priv(dev);
2383 u_long iobase = dev->base_addr;
2384 int next_tick = DE4X5_AUTOSENSE_MS;
2385
2386 lp->linkOK = 0;
2387 lp->c_media = AUTO; /* Bogus last media */
2388 disable_ast(dev);
2389 inl(DE4X5_MFC); /* Zero the lost frames counter */
2390 lp->media = INIT;
2391 lp->tcount = 0;
2392
2393 if (lp->useSROM) {
2394 next_tick = srom_autoconf(dev);
2395 } else if (lp->chipset == DC21040) {
2396 next_tick = dc21040_autoconf(dev);
2397 } else if (lp->chipset == DC21041) {
2398 next_tick = dc21041_autoconf(dev);
2399 } else if (lp->chipset == DC21140) {
2400 next_tick = dc21140m_autoconf(dev);
2401 }
2402
2403 enable_ast(dev, next_tick);
2404
2405 return (lp->media);
2406 }
2407
2408 /*
2409 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2410 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2411 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2412 ** The only way to test for that is to place a loopback packet onto the
2413 ** network and watch for errors. Since we're messing with the interrupt mask
2414 ** register, disable the board interrupts and do not allow any more packets to
2415 ** be queued to the hardware. Re-enable everything only when the media is
2416 ** found.
2417 ** I may have to "age out" locally queued packets so that the higher layer
2418 ** timeouts don't effectively duplicate packets on the network.
2419 */
2420 static int
2421 dc21040_autoconf(struct net_device *dev)
2422 {
2423 struct de4x5_private *lp = netdev_priv(dev);
2424 u_long iobase = dev->base_addr;
2425 int next_tick = DE4X5_AUTOSENSE_MS;
2426 s32 imr;
2427
2428 switch (lp->media) {
2429 case INIT:
2430 DISABLE_IRQs;
2431 lp->tx_enable = NO;
2432 lp->timeout = -1;
2433 de4x5_save_skbs(dev);
2434 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2435 lp->media = TP;
2436 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2437 lp->media = BNC_AUI;
2438 } else if (lp->autosense == EXT_SIA) {
2439 lp->media = EXT_SIA;
2440 } else {
2441 lp->media = NC;
2442 }
2443 lp->local_state = 0;
2444 next_tick = dc21040_autoconf(dev);
2445 break;
2446
2447 case TP:
2448 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2449 TP_SUSPECT, test_tp);
2450 break;
2451
2452 case TP_SUSPECT:
2453 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2454 break;
2455
2456 case BNC:
2457 case AUI:
2458 case BNC_AUI:
2459 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2460 BNC_AUI_SUSPECT, ping_media);
2461 break;
2462
2463 case BNC_AUI_SUSPECT:
2464 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2465 break;
2466
2467 case EXT_SIA:
2468 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2469 NC, EXT_SIA_SUSPECT, ping_media);
2470 break;
2471
2472 case EXT_SIA_SUSPECT:
2473 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2474 break;
2475
2476 case NC:
2477 /* default to TP for all */
2478 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2479 if (lp->media != lp->c_media) {
2480 de4x5_dbg_media(dev);
2481 lp->c_media = lp->media;
2482 }
2483 lp->media = INIT;
2484 lp->tx_enable = NO;
2485 break;
2486 }
2487
2488 return next_tick;
2489 }
2490
2491 static int
2492 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2493 int next_state, int suspect_state,
2494 int (*fn)(struct net_device *, int))
2495 {
2496 struct de4x5_private *lp = netdev_priv(dev);
2497 int next_tick = DE4X5_AUTOSENSE_MS;
2498 int linkBad;
2499
2500 switch (lp->local_state) {
2501 case 0:
2502 reset_init_sia(dev, csr13, csr14, csr15);
2503 lp->local_state++;
2504 next_tick = 500;
2505 break;
2506
2507 case 1:
2508 if (!lp->tx_enable) {
2509 linkBad = fn(dev, timeout);
2510 if (linkBad < 0) {
2511 next_tick = linkBad & ~TIMER_CB;
2512 } else {
2513 if (linkBad && (lp->autosense == AUTO)) {
2514 lp->local_state = 0;
2515 lp->media = next_state;
2516 } else {
2517 de4x5_init_connection(dev);
2518 }
2519 }
2520 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2521 lp->media = suspect_state;
2522 next_tick = 3000;
2523 }
2524 break;
2525 }
2526
2527 return next_tick;
2528 }
2529
2530 static int
2531 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2532 int (*fn)(struct net_device *, int),
2533 int (*asfn)(struct net_device *))
2534 {
2535 struct de4x5_private *lp = netdev_priv(dev);
2536 int next_tick = DE4X5_AUTOSENSE_MS;
2537 int linkBad;
2538
2539 switch (lp->local_state) {
2540 case 1:
2541 if (lp->linkOK) {
2542 lp->media = prev_state;
2543 } else {
2544 lp->local_state++;
2545 next_tick = asfn(dev);
2546 }
2547 break;
2548
2549 case 2:
2550 linkBad = fn(dev, timeout);
2551 if (linkBad < 0) {
2552 next_tick = linkBad & ~TIMER_CB;
2553 } else if (!linkBad) {
2554 lp->local_state--;
2555 lp->media = prev_state;
2556 } else {
2557 lp->media = INIT;
2558 lp->tcount++;
2559 }
2560 }
2561
2562 return next_tick;
2563 }
2564
2565 /*
2566 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2567 ** before BNC, because the BNC port will indicate activity if it's not
2568 ** terminated correctly. The only way to test for that is to place a loopback
2569 ** packet onto the network and watch for errors. Since we're messing with
2570 ** the interrupt mask register, disable the board interrupts and do not allow
2571 ** any more packets to be queued to the hardware. Re-enable everything only
2572 ** when the media is found.
2573 */
2574 static int
2575 dc21041_autoconf(struct net_device *dev)
2576 {
2577 struct de4x5_private *lp = netdev_priv(dev);
2578 u_long iobase = dev->base_addr;
2579 s32 sts, irqs, irq_mask, imr, omr;
2580 int next_tick = DE4X5_AUTOSENSE_MS;
2581
2582 switch (lp->media) {
2583 case INIT:
2584 DISABLE_IRQs;
2585 lp->tx_enable = NO;
2586 lp->timeout = -1;
2587 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2588 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2589 lp->media = TP; /* On chip auto negotiation is broken */
2590 } else if (lp->autosense == TP) {
2591 lp->media = TP;
2592 } else if (lp->autosense == BNC) {
2593 lp->media = BNC;
2594 } else if (lp->autosense == AUI) {
2595 lp->media = AUI;
2596 } else {
2597 lp->media = NC;
2598 }
2599 lp->local_state = 0;
2600 next_tick = dc21041_autoconf(dev);
2601 break;
2602
2603 case TP_NW:
2604 if (lp->timeout < 0) {
2605 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2606 outl(omr | OMR_FDX, DE4X5_OMR);
2607 }
2608 irqs = STS_LNF | STS_LNP;
2609 irq_mask = IMR_LFM | IMR_LPM;
2610 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2611 if (sts < 0) {
2612 next_tick = sts & ~TIMER_CB;
2613 } else {
2614 if (sts & STS_LNP) {
2615 lp->media = ANS;
2616 } else {
2617 lp->media = AUI;
2618 }
2619 next_tick = dc21041_autoconf(dev);
2620 }
2621 break;
2622
2623 case ANS:
2624 if (!lp->tx_enable) {
2625 irqs = STS_LNP;
2626 irq_mask = IMR_LPM;
2627 sts = test_ans(dev, irqs, irq_mask, 3000);
2628 if (sts < 0) {
2629 next_tick = sts & ~TIMER_CB;
2630 } else {
2631 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2632 lp->media = TP;
2633 next_tick = dc21041_autoconf(dev);
2634 } else {
2635 lp->local_state = 1;
2636 de4x5_init_connection(dev);
2637 }
2638 }
2639 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2640 lp->media = ANS_SUSPECT;
2641 next_tick = 3000;
2642 }
2643 break;
2644
2645 case ANS_SUSPECT:
2646 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2647 break;
2648
2649 case TP:
2650 if (!lp->tx_enable) {
2651 if (lp->timeout < 0) {
2652 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2653 outl(omr & ~OMR_FDX, DE4X5_OMR);
2654 }
2655 irqs = STS_LNF | STS_LNP;
2656 irq_mask = IMR_LFM | IMR_LPM;
2657 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2658 if (sts < 0) {
2659 next_tick = sts & ~TIMER_CB;
2660 } else {
2661 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2662 if (inl(DE4X5_SISR) & SISR_NRA) {
2663 lp->media = AUI; /* Non selected port activity */
2664 } else {
2665 lp->media = BNC;
2666 }
2667 next_tick = dc21041_autoconf(dev);
2668 } else {
2669 lp->local_state = 1;
2670 de4x5_init_connection(dev);
2671 }
2672 }
2673 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2674 lp->media = TP_SUSPECT;
2675 next_tick = 3000;
2676 }
2677 break;
2678
2679 case TP_SUSPECT:
2680 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2681 break;
2682
2683 case AUI:
2684 if (!lp->tx_enable) {
2685 if (lp->timeout < 0) {
2686 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2687 outl(omr & ~OMR_FDX, DE4X5_OMR);
2688 }
2689 irqs = 0;
2690 irq_mask = 0;
2691 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2692 if (sts < 0) {
2693 next_tick = sts & ~TIMER_CB;
2694 } else {
2695 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2696 lp->media = BNC;
2697 next_tick = dc21041_autoconf(dev);
2698 } else {
2699 lp->local_state = 1;
2700 de4x5_init_connection(dev);
2701 }
2702 }
2703 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2704 lp->media = AUI_SUSPECT;
2705 next_tick = 3000;
2706 }
2707 break;
2708
2709 case AUI_SUSPECT:
2710 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2711 break;
2712
2713 case BNC:
2714 switch (lp->local_state) {
2715 case 0:
2716 if (lp->timeout < 0) {
2717 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2718 outl(omr & ~OMR_FDX, DE4X5_OMR);
2719 }
2720 irqs = 0;
2721 irq_mask = 0;
2722 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2723 if (sts < 0) {
2724 next_tick = sts & ~TIMER_CB;
2725 } else {
2726 lp->local_state++; /* Ensure media connected */
2727 next_tick = dc21041_autoconf(dev);
2728 }
2729 break;
2730
2731 case 1:
2732 if (!lp->tx_enable) {
2733 if ((sts = ping_media(dev, 3000)) < 0) {
2734 next_tick = sts & ~TIMER_CB;
2735 } else {
2736 if (sts) {
2737 lp->local_state = 0;
2738 lp->media = NC;
2739 } else {
2740 de4x5_init_connection(dev);
2741 }
2742 }
2743 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2744 lp->media = BNC_SUSPECT;
2745 next_tick = 3000;
2746 }
2747 break;
2748 }
2749 break;
2750
2751 case BNC_SUSPECT:
2752 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2753 break;
2754
2755 case NC:
2756 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2757 outl(omr | OMR_FDX, DE4X5_OMR);
2758 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2759 if (lp->media != lp->c_media) {
2760 de4x5_dbg_media(dev);
2761 lp->c_media = lp->media;
2762 }
2763 lp->media = INIT;
2764 lp->tx_enable = NO;
2765 break;
2766 }
2767
2768 return next_tick;
2769 }
2770
2771 /*
2772 ** Some autonegotiation chips are broken in that they do not return the
2773 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2774 ** register, except at the first power up negotiation.
2775 */
2776 static int
2777 dc21140m_autoconf(struct net_device *dev)
2778 {
2779 struct de4x5_private *lp = netdev_priv(dev);
2780 int ana, anlpa, cap, cr, slnk, sr;
2781 int next_tick = DE4X5_AUTOSENSE_MS;
2782 u_long imr, omr, iobase = dev->base_addr;
2783
2784 switch(lp->media) {
2785 case INIT:
2786 if (lp->timeout < 0) {
2787 DISABLE_IRQs;
2788 lp->tx_enable = FALSE;
2789 lp->linkOK = 0;
2790 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2791 }
2792 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2793 next_tick &= ~TIMER_CB;
2794 } else {
2795 if (lp->useSROM) {
2796 if (srom_map_media(dev) < 0) {
2797 lp->tcount++;
2798 return next_tick;
2799 }
2800 srom_exec(dev, lp->phy[lp->active].gep);
2801 if (lp->infoblock_media == ANS) {
2802 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2803 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2804 }
2805 } else {
2806 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2807 SET_10Mb;
2808 if (lp->autosense == _100Mb) {
2809 lp->media = _100Mb;
2810 } else if (lp->autosense == _10Mb) {
2811 lp->media = _10Mb;
2812 } else if ((lp->autosense == AUTO) &&
2813 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2814 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2815 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2816 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2817 lp->media = ANS;
2818 } else if (lp->autosense == AUTO) {
2819 lp->media = SPD_DET;
2820 } else if (is_spd_100(dev) && is_100_up(dev)) {
2821 lp->media = _100Mb;
2822 } else {
2823 lp->media = NC;
2824 }
2825 }
2826 lp->local_state = 0;
2827 next_tick = dc21140m_autoconf(dev);
2828 }
2829 break;
2830
2831 case ANS:
2832 switch (lp->local_state) {
2833 case 0:
2834 if (lp->timeout < 0) {
2835 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2836 }
2837 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2838 if (cr < 0) {
2839 next_tick = cr & ~TIMER_CB;
2840 } else {
2841 if (cr) {
2842 lp->local_state = 0;
2843 lp->media = SPD_DET;
2844 } else {
2845 lp->local_state++;
2846 }
2847 next_tick = dc21140m_autoconf(dev);
2848 }
2849 break;
2850
2851 case 1:
2852 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2853 next_tick = sr & ~TIMER_CB;
2854 } else {
2855 lp->media = SPD_DET;
2856 lp->local_state = 0;
2857 if (sr) { /* Success! */
2858 lp->tmp = MII_SR_ASSC;
2859 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2860 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2861 if (!(anlpa & MII_ANLPA_RF) &&
2862 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2863 if (cap & MII_ANA_100M) {
2864 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2865 lp->media = _100Mb;
2866 } else if (cap & MII_ANA_10M) {
2867 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2868
2869 lp->media = _10Mb;
2870 }
2871 }
2872 } /* Auto Negotiation failed to finish */
2873 next_tick = dc21140m_autoconf(dev);
2874 } /* Auto Negotiation failed to start */
2875 break;
2876 }
2877 break;
2878
2879 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2880 if (lp->timeout < 0) {
2881 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2882 (~gep_rd(dev) & GEP_LNP));
2883 SET_100Mb_PDET;
2884 }
2885 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2886 next_tick = slnk & ~TIMER_CB;
2887 } else {
2888 if (is_spd_100(dev) && is_100_up(dev)) {
2889 lp->media = _100Mb;
2890 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2891 lp->media = _10Mb;
2892 } else {
2893 lp->media = NC;
2894 }
2895 next_tick = dc21140m_autoconf(dev);
2896 }
2897 break;
2898
2899 case _100Mb: /* Set 100Mb/s */
2900 next_tick = 3000;
2901 if (!lp->tx_enable) {
2902 SET_100Mb;
2903 de4x5_init_connection(dev);
2904 } else {
2905 if (!lp->linkOK && (lp->autosense == AUTO)) {
2906 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2907 lp->media = INIT;
2908 lp->tcount++;
2909 next_tick = DE4X5_AUTOSENSE_MS;
2910 }
2911 }
2912 }
2913 break;
2914
2915 case BNC:
2916 case AUI:
2917 case _10Mb: /* Set 10Mb/s */
2918 next_tick = 3000;
2919 if (!lp->tx_enable) {
2920 SET_10Mb;
2921 de4x5_init_connection(dev);
2922 } else {
2923 if (!lp->linkOK && (lp->autosense == AUTO)) {
2924 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2925 lp->media = INIT;
2926 lp->tcount++;
2927 next_tick = DE4X5_AUTOSENSE_MS;
2928 }
2929 }
2930 }
2931 break;
2932
2933 case NC:
2934 if (lp->media != lp->c_media) {
2935 de4x5_dbg_media(dev);
2936 lp->c_media = lp->media;
2937 }
2938 lp->media = INIT;
2939 lp->tx_enable = FALSE;
2940 break;
2941 }
2942
2943 return next_tick;
2944 }
2945
2946 /*
2947 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2948 ** changing how I figure out the media - but trying to keep it backwards
2949 ** compatible with the de500-xa and de500-aa.
2950 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2951 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2952 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2953 ** active.
2954 ** When autonegotiation is working, the ANS part searches the SROM for
2955 ** the highest common speed (TP) link that both can run and if that can
2956 ** be full duplex. That infoblock is executed and then the link speed set.
2957 **
2958 ** Only _10Mb and _100Mb are tested here.
2959 */
2960 static int
2961 dc2114x_autoconf(struct net_device *dev)
2962 {
2963 struct de4x5_private *lp = netdev_priv(dev);
2964 u_long iobase = dev->base_addr;
2965 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2966 int next_tick = DE4X5_AUTOSENSE_MS;
2967
2968 switch (lp->media) {
2969 case INIT:
2970 if (lp->timeout < 0) {
2971 DISABLE_IRQs;
2972 lp->tx_enable = FALSE;
2973 lp->linkOK = 0;
2974 lp->timeout = -1;
2975 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2976 if (lp->params.autosense & ~AUTO) {
2977 srom_map_media(dev); /* Fixed media requested */
2978 if (lp->media != lp->params.autosense) {
2979 lp->tcount++;
2980 lp->media = INIT;
2981 return next_tick;
2982 }
2983 lp->media = INIT;
2984 }
2985 }
2986 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2987 next_tick &= ~TIMER_CB;
2988 } else {
2989 if (lp->autosense == _100Mb) {
2990 lp->media = _100Mb;
2991 } else if (lp->autosense == _10Mb) {
2992 lp->media = _10Mb;
2993 } else if (lp->autosense == TP) {
2994 lp->media = TP;
2995 } else if (lp->autosense == BNC) {
2996 lp->media = BNC;
2997 } else if (lp->autosense == AUI) {
2998 lp->media = AUI;
2999 } else {
3000 lp->media = SPD_DET;
3001 if ((lp->infoblock_media == ANS) &&
3002 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3003 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3004 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3005 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3006 lp->media = ANS;
3007 }
3008 }
3009 lp->local_state = 0;
3010 next_tick = dc2114x_autoconf(dev);
3011 }
3012 break;
3013
3014 case ANS:
3015 switch (lp->local_state) {
3016 case 0:
3017 if (lp->timeout < 0) {
3018 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3019 }
3020 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3021 if (cr < 0) {
3022 next_tick = cr & ~TIMER_CB;
3023 } else {
3024 if (cr) {
3025 lp->local_state = 0;
3026 lp->media = SPD_DET;
3027 } else {
3028 lp->local_state++;
3029 }
3030 next_tick = dc2114x_autoconf(dev);
3031 }
3032 break;
3033
3034 case 1:
3035 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3036 next_tick = sr & ~TIMER_CB;
3037 } else {
3038 lp->media = SPD_DET;
3039 lp->local_state = 0;
3040 if (sr) { /* Success! */
3041 lp->tmp = MII_SR_ASSC;
3042 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3043 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3044 if (!(anlpa & MII_ANLPA_RF) &&
3045 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3046 if (cap & MII_ANA_100M) {
3047 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3048 lp->media = _100Mb;
3049 } else if (cap & MII_ANA_10M) {
3050 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3051 lp->media = _10Mb;
3052 }
3053 }
3054 } /* Auto Negotiation failed to finish */
3055 next_tick = dc2114x_autoconf(dev);
3056 } /* Auto Negotiation failed to start */
3057 break;
3058 }
3059 break;
3060
3061 case AUI:
3062 if (!lp->tx_enable) {
3063 if (lp->timeout < 0) {
3064 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3065 outl(omr & ~OMR_FDX, DE4X5_OMR);
3066 }
3067 irqs = 0;
3068 irq_mask = 0;
3069 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3070 if (sts < 0) {
3071 next_tick = sts & ~TIMER_CB;
3072 } else {
3073 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3074 lp->media = BNC;
3075 next_tick = dc2114x_autoconf(dev);
3076 } else {
3077 lp->local_state = 1;
3078 de4x5_init_connection(dev);
3079 }
3080 }
3081 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3082 lp->media = AUI_SUSPECT;
3083 next_tick = 3000;
3084 }
3085 break;
3086
3087 case AUI_SUSPECT:
3088 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3089 break;
3090
3091 case BNC:
3092 switch (lp->local_state) {
3093 case 0:
3094 if (lp->timeout < 0) {
3095 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3096 outl(omr & ~OMR_FDX, DE4X5_OMR);
3097 }
3098 irqs = 0;
3099 irq_mask = 0;
3100 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3101 if (sts < 0) {
3102 next_tick = sts & ~TIMER_CB;
3103 } else {
3104 lp->local_state++; /* Ensure media connected */
3105 next_tick = dc2114x_autoconf(dev);
3106 }
3107 break;
3108
3109 case 1:
3110 if (!lp->tx_enable) {
3111 if ((sts = ping_media(dev, 3000)) < 0) {
3112 next_tick = sts & ~TIMER_CB;
3113 } else {
3114 if (sts) {
3115 lp->local_state = 0;
3116 lp->tcount++;
3117 lp->media = INIT;
3118 } else {
3119 de4x5_init_connection(dev);
3120 }
3121 }
3122 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3123 lp->media = BNC_SUSPECT;
3124 next_tick = 3000;
3125 }
3126 break;
3127 }
3128 break;
3129
3130 case BNC_SUSPECT:
3131 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3132 break;
3133
3134 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3135 if (srom_map_media(dev) < 0) {
3136 lp->tcount++;
3137 lp->media = INIT;
3138 return next_tick;
3139 }
3140 if (lp->media == _100Mb) {
3141 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3142 lp->media = SPD_DET;
3143 return (slnk & ~TIMER_CB);
3144 }
3145 } else {
3146 if (wait_for_link(dev) < 0) {
3147 lp->media = SPD_DET;
3148 return PDET_LINK_WAIT;
3149 }
3150 }
3151 if (lp->media == ANS) { /* Do MII parallel detection */
3152 if (is_spd_100(dev)) {
3153 lp->media = _100Mb;
3154 } else {
3155 lp->media = _10Mb;
3156 }
3157 next_tick = dc2114x_autoconf(dev);
3158 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3159 (((lp->media == _10Mb) || (lp->media == TP) ||
3160 (lp->media == BNC) || (lp->media == AUI)) &&
3161 is_10_up(dev))) {
3162 next_tick = dc2114x_autoconf(dev);
3163 } else {
3164 lp->tcount++;
3165 lp->media = INIT;
3166 }
3167 break;
3168
3169 case _10Mb:
3170 next_tick = 3000;
3171 if (!lp->tx_enable) {
3172 SET_10Mb;
3173 de4x5_init_connection(dev);
3174 } else {
3175 if (!lp->linkOK && (lp->autosense == AUTO)) {
3176 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3177 lp->media = INIT;
3178 lp->tcount++;
3179 next_tick = DE4X5_AUTOSENSE_MS;
3180 }
3181 }
3182 }
3183 break;
3184
3185 case _100Mb:
3186 next_tick = 3000;
3187 if (!lp->tx_enable) {
3188 SET_100Mb;
3189 de4x5_init_connection(dev);
3190 } else {
3191 if (!lp->linkOK && (lp->autosense == AUTO)) {
3192 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3193 lp->media = INIT;
3194 lp->tcount++;
3195 next_tick = DE4X5_AUTOSENSE_MS;
3196 }
3197 }
3198 }
3199 break;
3200
3201 default:
3202 lp->tcount++;
3203 printk("Huh?: media:%02x\n", lp->media);
3204 lp->media = INIT;
3205 break;
3206 }
3207
3208 return next_tick;
3209 }
3210
3211 static int
3212 srom_autoconf(struct net_device *dev)
3213 {
3214 struct de4x5_private *lp = netdev_priv(dev);
3215
3216 return lp->infoleaf_fn(dev);
3217 }
3218
3219 /*
3220 ** This mapping keeps the original media codes and FDX flag unchanged.
3221 ** While it isn't strictly necessary, it helps me for the moment...
3222 ** The early return avoids a media state / SROM media space clash.
3223 */
3224 static int
3225 srom_map_media(struct net_device *dev)
3226 {
3227 struct de4x5_private *lp = netdev_priv(dev);
3228
3229 lp->fdx = 0;
3230 if (lp->infoblock_media == lp->media)
3231 return 0;
3232
3233 switch(lp->infoblock_media) {
3234 case SROM_10BASETF:
3235 if (!lp->params.fdx) return -1;
3236 lp->fdx = TRUE;
3237 case SROM_10BASET:
3238 if (lp->params.fdx && !lp->fdx) return -1;
3239 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3240 lp->media = _10Mb;
3241 } else {
3242 lp->media = TP;
3243 }
3244 break;
3245
3246 case SROM_10BASE2:
3247 lp->media = BNC;
3248 break;
3249
3250 case SROM_10BASE5:
3251 lp->media = AUI;
3252 break;
3253
3254 case SROM_100BASETF:
3255 if (!lp->params.fdx) return -1;
3256 lp->fdx = TRUE;
3257 case SROM_100BASET:
3258 if (lp->params.fdx && !lp->fdx) return -1;
3259 lp->media = _100Mb;
3260 break;
3261
3262 case SROM_100BASET4:
3263 lp->media = _100Mb;
3264 break;
3265
3266 case SROM_100BASEFF:
3267 if (!lp->params.fdx) return -1;
3268 lp->fdx = TRUE;
3269 case SROM_100BASEF:
3270 if (lp->params.fdx && !lp->fdx) return -1;
3271 lp->media = _100Mb;
3272 break;
3273
3274 case ANS:
3275 lp->media = ANS;
3276 lp->fdx = lp->params.fdx;
3277 break;
3278
3279 default:
3280 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3281 lp->infoblock_media);
3282 return -1;
3283 break;
3284 }
3285
3286 return 0;
3287 }
3288
3289 static void
3290 de4x5_init_connection(struct net_device *dev)
3291 {
3292 struct de4x5_private *lp = netdev_priv(dev);
3293 u_long iobase = dev->base_addr;
3294 u_long flags = 0;
3295
3296 if (lp->media != lp->c_media) {
3297 de4x5_dbg_media(dev);
3298 lp->c_media = lp->media; /* Stop scrolling media messages */
3299 }
3300
3301 spin_lock_irqsave(&lp->lock, flags);
3302 de4x5_rst_desc_ring(dev);
3303 de4x5_setup_intr(dev);
3304 lp->tx_enable = YES;
3305 spin_unlock_irqrestore(&lp->lock, flags);
3306 outl(POLL_DEMAND, DE4X5_TPD);
3307
3308 netif_wake_queue(dev);
3309
3310 return;
3311 }
3312
3313 /*
3314 ** General PHY reset function. Some MII devices don't reset correctly
3315 ** since their MII address pins can float at voltages that are dependent
3316 ** on the signal pin use. Do a double reset to ensure a reset.
3317 */
3318 static int
3319 de4x5_reset_phy(struct net_device *dev)
3320 {
3321 struct de4x5_private *lp = netdev_priv(dev);
3322 u_long iobase = dev->base_addr;
3323 int next_tick = 0;
3324
3325 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3326 if (lp->timeout < 0) {
3327 if (lp->useSROM) {
3328 if (lp->phy[lp->active].rst) {
3329 srom_exec(dev, lp->phy[lp->active].rst);
3330 srom_exec(dev, lp->phy[lp->active].rst);
3331 } else if (lp->rst) { /* Type 5 infoblock reset */
3332 srom_exec(dev, lp->rst);
3333 srom_exec(dev, lp->rst);
3334 }
3335 } else {
3336 PHY_HARD_RESET;
3337 }
3338 if (lp->useMII) {
3339 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3340 }
3341 }
3342 if (lp->useMII) {
3343 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3344 }
3345 } else if (lp->chipset == DC21140) {
3346 PHY_HARD_RESET;
3347 }
3348
3349 return next_tick;
3350 }
3351
3352 static int
3353 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3354 {
3355 struct de4x5_private *lp = netdev_priv(dev);
3356 u_long iobase = dev->base_addr;
3357 s32 sts, csr12;
3358
3359 if (lp->timeout < 0) {
3360 lp->timeout = msec/100;
3361 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3362 reset_init_sia(dev, csr13, csr14, csr15);
3363 }
3364
3365 /* set up the interrupt mask */
3366 outl(irq_mask, DE4X5_IMR);
3367
3368 /* clear all pending interrupts */
3369 sts = inl(DE4X5_STS);
3370 outl(sts, DE4X5_STS);
3371
3372 /* clear csr12 NRA and SRA bits */
3373 if ((lp->chipset == DC21041) || lp->useSROM) {
3374 csr12 = inl(DE4X5_SISR);
3375 outl(csr12, DE4X5_SISR);
3376 }
3377 }
3378
3379 sts = inl(DE4X5_STS) & ~TIMER_CB;
3380
3381 if (!(sts & irqs) && --lp->timeout) {
3382 sts = 100 | TIMER_CB;
3383 } else {
3384 lp->timeout = -1;
3385 }
3386
3387 return sts;
3388 }
3389
3390 static int
3391 test_tp(struct net_device *dev, s32 msec)
3392 {
3393 struct de4x5_private *lp = netdev_priv(dev);
3394 u_long iobase = dev->base_addr;
3395 int sisr;
3396
3397 if (lp->timeout < 0) {
3398 lp->timeout = msec/100;
3399 }
3400
3401 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3402
3403 if (sisr && --lp->timeout) {
3404 sisr = 100 | TIMER_CB;
3405 } else {
3406 lp->timeout = -1;
3407 }
3408
3409 return sisr;
3410 }
3411
3412 /*
3413 ** Samples the 100Mb Link State Signal. The sample interval is important
3414 ** because too fast a rate can give erroneous results and confuse the
3415 ** speed sense algorithm.
3416 */
3417 #define SAMPLE_INTERVAL 500 /* ms */
3418 #define SAMPLE_DELAY 2000 /* ms */
3419 static int
3420 test_for_100Mb(struct net_device *dev, int msec)
3421 {
3422 struct de4x5_private *lp = netdev_priv(dev);
3423 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3424
3425 if (lp->timeout < 0) {
3426 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3427 if (msec > SAMPLE_DELAY) {
3428 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3429 gep = SAMPLE_DELAY | TIMER_CB;
3430 return gep;
3431 } else {
3432 lp->timeout = msec/SAMPLE_INTERVAL;
3433 }
3434 }
3435
3436 if (lp->phy[lp->active].id || lp->useSROM) {
3437 gep = is_100_up(dev) | is_spd_100(dev);
3438 } else {
3439 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3440 }
3441 if (!(gep & ret) && --lp->timeout) {
3442 gep = SAMPLE_INTERVAL | TIMER_CB;
3443 } else {
3444 lp->timeout = -1;
3445 }
3446
3447 return gep;
3448 }
3449
3450 static int
3451 wait_for_link(struct net_device *dev)
3452 {
3453 struct de4x5_private *lp = netdev_priv(dev);
3454
3455 if (lp->timeout < 0) {
3456 lp->timeout = 1;
3457 }
3458
3459 if (lp->timeout--) {
3460 return TIMER_CB;
3461 } else {
3462 lp->timeout = -1;
3463 }
3464
3465 return 0;
3466 }
3467
3468 /*
3469 **
3470 **
3471 */
3472 static int
3473 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3474 {
3475 struct de4x5_private *lp = netdev_priv(dev);
3476 int test;
3477 u_long iobase = dev->base_addr;
3478
3479 if (lp->timeout < 0) {
3480 lp->timeout = msec/100;
3481 }
3482
3483 if (pol) pol = ~0;
3484 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3485 test = (reg ^ pol) & mask;
3486
3487 if (test && --lp->timeout) {
3488 reg = 100 | TIMER_CB;
3489 } else {
3490 lp->timeout = -1;
3491 }
3492
3493 return reg;
3494 }
3495
3496 static int
3497 is_spd_100(struct net_device *dev)
3498 {
3499 struct de4x5_private *lp = netdev_priv(dev);
3500 u_long iobase = dev->base_addr;
3501 int spd;
3502
3503 if (lp->useMII) {
3504 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3505 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3506 spd &= lp->phy[lp->active].spd.mask;
3507 } else if (!lp->useSROM) { /* de500-xa */
3508 spd = ((~gep_rd(dev)) & GEP_SLNK);
3509 } else {
3510 if ((lp->ibn == 2) || !lp->asBitValid)
3511 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3512
3513 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3514 (lp->linkOK & ~lp->asBitValid);
3515 }
3516
3517 return spd;
3518 }
3519
3520 static int
3521 is_100_up(struct net_device *dev)
3522 {
3523 struct de4x5_private *lp = netdev_priv(dev);
3524 u_long iobase = dev->base_addr;
3525
3526 if (lp->useMII) {
3527 /* Double read for sticky bits & temporary drops */
3528 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3529 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3530 } else if (!lp->useSROM) { /* de500-xa */
3531 return ((~gep_rd(dev)) & GEP_SLNK);
3532 } else {
3533 if ((lp->ibn == 2) || !lp->asBitValid)
3534 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3535
3536 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3537 (lp->linkOK & ~lp->asBitValid));
3538 }
3539 }
3540
3541 static int
3542 is_10_up(struct net_device *dev)
3543 {
3544 struct de4x5_private *lp = netdev_priv(dev);
3545 u_long iobase = dev->base_addr;
3546
3547 if (lp->useMII) {
3548 /* Double read for sticky bits & temporary drops */
3549 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3550 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3551 } else if (!lp->useSROM) { /* de500-xa */
3552 return ((~gep_rd(dev)) & GEP_LNP);
3553 } else {
3554 if ((lp->ibn == 2) || !lp->asBitValid)
3555 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3556 (~inl(DE4X5_SISR)&SISR_LS10):
3557 0);
3558
3559 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3560 (lp->linkOK & ~lp->asBitValid));
3561 }
3562 }
3563
3564 static int
3565 is_anc_capable(struct net_device *dev)
3566 {
3567 struct de4x5_private *lp = netdev_priv(dev);
3568 u_long iobase = dev->base_addr;
3569
3570 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3571 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3572 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3573 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3574 } else {
3575 return 0;
3576 }
3577 }
3578
3579 /*
3580 ** Send a packet onto the media and watch for send errors that indicate the
3581 ** media is bad or unconnected.
3582 */
3583 static int
3584 ping_media(struct net_device *dev, int msec)
3585 {
3586 struct de4x5_private *lp = netdev_priv(dev);
3587 u_long iobase = dev->base_addr;
3588 int sisr;
3589
3590 if (lp->timeout < 0) {
3591 lp->timeout = msec/100;
3592
3593 lp->tmp = lp->tx_new; /* Remember the ring position */
3594 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3595 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3596 outl(POLL_DEMAND, DE4X5_TPD);
3597 }
3598
3599 sisr = inl(DE4X5_SISR);
3600
3601 if ((!(sisr & SISR_NCR)) &&
3602 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3603 (--lp->timeout)) {
3604 sisr = 100 | TIMER_CB;
3605 } else {
3606 if ((!(sisr & SISR_NCR)) &&
3607 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3608 lp->timeout) {
3609 sisr = 0;
3610 } else {
3611 sisr = 1;
3612 }
3613 lp->timeout = -1;
3614 }
3615
3616 return sisr;
3617 }
3618
3619 /*
3620 ** This function does 2 things: on Intels it kmalloc's another buffer to
3621 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3622 ** into which the packet is copied.
3623 */
3624 static struct sk_buff *
3625 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3626 {
3627 struct de4x5_private *lp = netdev_priv(dev);
3628 struct sk_buff *p;
3629
3630 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3631 struct sk_buff *ret;
3632 u_long i=0, tmp;
3633
3634 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3635 if (!p) return NULL;
3636
3637 p->dev = dev;
3638 tmp = virt_to_bus(p->data);
3639 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3640 skb_reserve(p, i);
3641 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3642
3643 ret = lp->rx_skb[index];
3644 lp->rx_skb[index] = p;
3645
3646 if ((u_long) ret > 1) {
3647 skb_put(ret, len);
3648 }
3649
3650 return ret;
3651
3652 #else
3653 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3654
3655 p = dev_alloc_skb(len + 2);
3656 if (!p) return NULL;
3657
3658 p->dev = dev;
3659 skb_reserve(p, 2); /* Align */
3660 if (index < lp->rx_old) { /* Wrapped buffer */
3661 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3662 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3663 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3664 } else { /* Linear buffer */
3665 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3666 }
3667
3668 return p;
3669 #endif
3670 }
3671
3672 static void
3673 de4x5_free_rx_buffs(struct net_device *dev)
3674 {
3675 struct de4x5_private *lp = netdev_priv(dev);
3676 int i;
3677
3678 for (i=0; i<lp->rxRingSize; i++) {
3679 if ((u_long) lp->rx_skb[i] > 1) {
3680 dev_kfree_skb(lp->rx_skb[i]);
3681 }
3682 lp->rx_ring[i].status = 0;
3683 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3684 }
3685
3686 return;
3687 }
3688
3689 static void
3690 de4x5_free_tx_buffs(struct net_device *dev)
3691 {
3692 struct de4x5_private *lp = netdev_priv(dev);
3693 int i;
3694
3695 for (i=0; i<lp->txRingSize; i++) {
3696 if (lp->tx_skb[i])
3697 de4x5_free_tx_buff(lp, i);
3698 lp->tx_ring[i].status = 0;
3699 }
3700
3701 /* Unload the locally queued packets */
3702 while (lp->cache.skb) {
3703 dev_kfree_skb(de4x5_get_cache(dev));
3704 }
3705
3706 return;
3707 }
3708
3709 /*
3710 ** When a user pulls a connection, the DECchip can end up in a
3711 ** 'running - waiting for end of transmission' state. This means that we
3712 ** have to perform a chip soft reset to ensure that we can synchronize
3713 ** the hardware and software and make any media probes using a loopback
3714 ** packet meaningful.
3715 */
3716 static void
3717 de4x5_save_skbs(struct net_device *dev)
3718 {
3719 struct de4x5_private *lp = netdev_priv(dev);
3720 u_long iobase = dev->base_addr;
3721 s32 omr;
3722
3723 if (!lp->cache.save_cnt) {
3724 STOP_DE4X5;
3725 de4x5_tx(dev); /* Flush any sent skb's */
3726 de4x5_free_tx_buffs(dev);
3727 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3728 de4x5_sw_reset(dev);
3729 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3730 lp->cache.save_cnt++;
3731 START_DE4X5;
3732 }
3733
3734 return;
3735 }
3736
3737 static void
3738 de4x5_rst_desc_ring(struct net_device *dev)
3739 {
3740 struct de4x5_private *lp = netdev_priv(dev);
3741 u_long iobase = dev->base_addr;
3742 int i;
3743 s32 omr;
3744
3745 if (lp->cache.save_cnt) {
3746 STOP_DE4X5;
3747 outl(lp->dma_rings, DE4X5_RRBA);
3748 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3749 DE4X5_TRBA);
3750
3751 lp->rx_new = lp->rx_old = 0;
3752 lp->tx_new = lp->tx_old = 0;
3753
3754 for (i = 0; i < lp->rxRingSize; i++) {
3755 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3756 }
3757
3758 for (i = 0; i < lp->txRingSize; i++) {
3759 lp->tx_ring[i].status = cpu_to_le32(0);
3760 }
3761
3762 barrier();
3763 lp->cache.save_cnt--;
3764 START_DE4X5;
3765 }
3766
3767 return;
3768 }
3769
3770 static void
3771 de4x5_cache_state(struct net_device *dev, int flag)
3772 {
3773 struct de4x5_private *lp = netdev_priv(dev);
3774 u_long iobase = dev->base_addr;
3775
3776 switch(flag) {
3777 case DE4X5_SAVE_STATE:
3778 lp->cache.csr0 = inl(DE4X5_BMR);
3779 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3780 lp->cache.csr7 = inl(DE4X5_IMR);
3781 break;
3782
3783 case DE4X5_RESTORE_STATE:
3784 outl(lp->cache.csr0, DE4X5_BMR);
3785 outl(lp->cache.csr6, DE4X5_OMR);
3786 outl(lp->cache.csr7, DE4X5_IMR);
3787 if (lp->chipset == DC21140) {
3788 gep_wr(lp->cache.gepc, dev);
3789 gep_wr(lp->cache.gep, dev);
3790 } else {
3791 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3792 lp->cache.csr15);
3793 }
3794 break;
3795 }
3796
3797 return;
3798 }
3799
3800 static void
3801 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3802 {
3803 struct de4x5_private *lp = netdev_priv(dev);
3804 struct sk_buff *p;
3805
3806 if (lp->cache.skb) {
3807 for (p=lp->cache.skb; p->next; p=p->next);
3808 p->next = skb;
3809 } else {
3810 lp->cache.skb = skb;
3811 }
3812 skb->next = NULL;
3813
3814 return;
3815 }
3816
3817 static void
3818 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3819 {
3820 struct de4x5_private *lp = netdev_priv(dev);
3821 struct sk_buff *p = lp->cache.skb;
3822
3823 lp->cache.skb = skb;
3824 skb->next = p;
3825
3826 return;
3827 }
3828
3829 static struct sk_buff *
3830 de4x5_get_cache(struct net_device *dev)
3831 {
3832 struct de4x5_private *lp = netdev_priv(dev);
3833 struct sk_buff *p = lp->cache.skb;
3834
3835 if (p) {
3836 lp->cache.skb = p->next;
3837 p->next = NULL;
3838 }
3839
3840 return p;
3841 }
3842
3843 /*
3844 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3845 ** is received and the auto-negotiation status is NWAY OK.
3846 */
3847 static int
3848 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3849 {
3850 struct de4x5_private *lp = netdev_priv(dev);
3851 u_long iobase = dev->base_addr;
3852 s32 sts, ans;
3853
3854 if (lp->timeout < 0) {
3855 lp->timeout = msec/100;
3856 outl(irq_mask, DE4X5_IMR);
3857
3858 /* clear all pending interrupts */
3859 sts = inl(DE4X5_STS);
3860 outl(sts, DE4X5_STS);
3861 }
3862
3863 ans = inl(DE4X5_SISR) & SISR_ANS;
3864 sts = inl(DE4X5_STS) & ~TIMER_CB;
3865
3866 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3867 sts = 100 | TIMER_CB;
3868 } else {
3869 lp->timeout = -1;
3870 }
3871
3872 return sts;
3873 }
3874
3875 static void
3876 de4x5_setup_intr(struct net_device *dev)
3877 {
3878 struct de4x5_private *lp = netdev_priv(dev);
3879 u_long iobase = dev->base_addr;
3880 s32 imr, sts;
3881
3882 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3883 imr = 0;
3884 UNMASK_IRQs;
3885 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3886 outl(sts, DE4X5_STS);
3887 ENABLE_IRQs;
3888 }
3889
3890 return;
3891 }
3892
3893 /*
3894 **
3895 */
3896 static void
3897 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3898 {
3899 struct de4x5_private *lp = netdev_priv(dev);
3900 u_long iobase = dev->base_addr;
3901
3902 RESET_SIA;
3903 if (lp->useSROM) {
3904 if (lp->ibn == 3) {
3905 srom_exec(dev, lp->phy[lp->active].rst);
3906 srom_exec(dev, lp->phy[lp->active].gep);
3907 outl(1, DE4X5_SICR);
3908 return;
3909 } else {
3910 csr15 = lp->cache.csr15;
3911 csr14 = lp->cache.csr14;
3912 csr13 = lp->cache.csr13;
3913 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3914 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3915 }
3916 } else {
3917 outl(csr15, DE4X5_SIGR);
3918 }
3919 outl(csr14, DE4X5_STRR);
3920 outl(csr13, DE4X5_SICR);
3921
3922 mdelay(10);
3923
3924 return;
3925 }
3926
3927 /*
3928 ** Create a loopback ethernet packet
3929 */
3930 static void
3931 create_packet(struct net_device *dev, char *frame, int len)
3932 {
3933 int i;
3934 char *buf = frame;
3935
3936 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3937 *buf++ = dev->dev_addr[i];
3938 }
3939 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3940 *buf++ = dev->dev_addr[i];
3941 }
3942
3943 *buf++ = 0; /* Packet length (2 bytes) */
3944 *buf++ = 1;
3945
3946 return;
3947 }
3948
3949 /*
3950 ** Look for a particular board name in the EISA configuration space
3951 */
3952 static int
3953 EISA_signature(char *name, struct device *device)
3954 {
3955 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3956 struct eisa_device *edev;
3957
3958 *name = '\0';
3959 edev = to_eisa_device (device);
3960 i = edev->id.driver_data;
3961
3962 if (i >= 0 && i < siglen) {
3963 strcpy (name, de4x5_signatures[i]);
3964 status = 1;
3965 }
3966
3967 return status; /* return the device name string */
3968 }
3969
3970 /*
3971 ** Look for a particular board name in the PCI configuration space
3972 */
3973 static int
3974 PCI_signature(char *name, struct de4x5_private *lp)
3975 {
3976 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3977
3978 if (lp->chipset == DC21040) {
3979 strcpy(name, "DE434/5");
3980 return status;
3981 } else { /* Search for a DEC name in the SROM */
3982 int i = *((char *)&lp->srom + 19) * 3;
3983 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3984 }
3985 name[8] = '\0';
3986 for (i=0; i<siglen; i++) {
3987 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3988 }
3989 if (i == siglen) {
3990 if (dec_only) {
3991 *name = '\0';
3992 } else { /* Use chip name to avoid confusion */
3993 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3994 ((lp->chipset == DC21041) ? "DC21041" :
3995 ((lp->chipset == DC21140) ? "DC21140" :
3996 ((lp->chipset == DC21142) ? "DC21142" :
3997 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3998 )))))));
3999 }
4000 if (lp->chipset != DC21041) {
4001 lp->useSROM = TRUE; /* card is not recognisably DEC */
4002 }
4003 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4004 lp->useSROM = TRUE;
4005 }
4006
4007 return status;
4008 }
4009
4010 /*
4011 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4012 ** the DC21040, else read the SROM for the other chips.
4013 ** The SROM may not be present in a multi-MAC card, so first read the
4014 ** MAC address and check for a bad address. If there is a bad one then exit
4015 ** immediately with the prior srom contents intact (the h/w address will
4016 ** be fixed up later).
4017 */
4018 static void
4019 DevicePresent(struct net_device *dev, u_long aprom_addr)
4020 {
4021 int i, j=0;
4022 struct de4x5_private *lp = netdev_priv(dev);
4023
4024 if (lp->chipset == DC21040) {
4025 if (lp->bus == EISA) {
4026 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4027 } else {
4028 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4029 }
4030 } else { /* Read new srom */
4031 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4032 for (i=0; i<(ETH_ALEN>>1); i++) {
4033 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4034 *p = le16_to_cpu(tmp);
4035 j += *p++;
4036 }
4037 if ((j == 0) || (j == 0x2fffd)) {
4038 return;
4039 }
4040
4041 p=(short *)&lp->srom;
4042 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4043 tmp = srom_rd(aprom_addr, i);
4044 *p++ = le16_to_cpu(tmp);
4045 }
4046 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4047 }
4048
4049 return;
4050 }
4051
4052 /*
4053 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4054 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4055 ** it...from depca.c.
4056 */
4057 static void
4058 enet_addr_rst(u_long aprom_addr)
4059 {
4060 union {
4061 struct {
4062 u32 a;
4063 u32 b;
4064 } llsig;
4065 char Sig[sizeof(u32) << 1];
4066 } dev;
4067 short sigLength=0;
4068 s8 data;
4069 int i, j;
4070
4071 dev.llsig.a = ETH_PROM_SIG;
4072 dev.llsig.b = ETH_PROM_SIG;
4073 sigLength = sizeof(u32) << 1;
4074
4075 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4076 data = inb(aprom_addr);
4077 if (dev.Sig[j] == data) { /* track signature */
4078 j++;
4079 } else { /* lost signature; begin search again */
4080 if (data == dev.Sig[0]) { /* rare case.... */
4081 j=1;
4082 } else {
4083 j=0;
4084 }
4085 }
4086 }
4087
4088 return;
4089 }
4090
4091 /*
4092 ** For the bad status case and no SROM, then add one to the previous
4093 ** address. However, need to add one backwards in case we have 0xff
4094 ** as one or more of the bytes. Only the last 3 bytes should be checked
4095 ** as the first three are invariant - assigned to an organisation.
4096 */
4097 static int
4098 get_hw_addr(struct net_device *dev)
4099 {
4100 u_long iobase = dev->base_addr;
4101 int broken, i, k, tmp, status = 0;
4102 u_short j,chksum;
4103 struct de4x5_private *lp = netdev_priv(dev);
4104
4105 broken = de4x5_bad_srom(lp);
4106
4107 for (i=0,k=0,j=0;j<3;j++) {
4108 k <<= 1;
4109 if (k > 0xffff) k-=0xffff;
4110
4111 if (lp->bus == PCI) {
4112 if (lp->chipset == DC21040) {
4113 while ((tmp = inl(DE4X5_APROM)) < 0);
4114 k += (u_char) tmp;
4115 dev->dev_addr[i++] = (u_char) tmp;
4116 while ((tmp = inl(DE4X5_APROM)) < 0);
4117 k += (u_short) (tmp << 8);
4118 dev->dev_addr[i++] = (u_char) tmp;
4119 } else if (!broken) {
4120 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4121 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4122 } else if ((broken == SMC) || (broken == ACCTON)) {
4123 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4124 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4125 }
4126 } else {
4127 k += (u_char) (tmp = inb(EISA_APROM));
4128 dev->dev_addr[i++] = (u_char) tmp;
4129 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4130 dev->dev_addr[i++] = (u_char) tmp;
4131 }
4132
4133 if (k > 0xffff) k-=0xffff;
4134 }
4135 if (k == 0xffff) k=0;
4136
4137 if (lp->bus == PCI) {
4138 if (lp->chipset == DC21040) {
4139 while ((tmp = inl(DE4X5_APROM)) < 0);
4140 chksum = (u_char) tmp;
4141 while ((tmp = inl(DE4X5_APROM)) < 0);
4142 chksum |= (u_short) (tmp << 8);
4143 if ((k != chksum) && (dec_only)) status = -1;
4144 }
4145 } else {
4146 chksum = (u_char) inb(EISA_APROM);
4147 chksum |= (u_short) (inb(EISA_APROM) << 8);
4148 if ((k != chksum) && (dec_only)) status = -1;
4149 }
4150
4151 /* If possible, try to fix a broken card - SMC only so far */
4152 srom_repair(dev, broken);
4153
4154 #ifdef CONFIG_PPC_PMAC
4155 /*
4156 ** If the address starts with 00 a0, we have to bit-reverse
4157 ** each byte of the address.
4158 */
4159 if ( machine_is(powermac) &&
4160 (dev->dev_addr[0] == 0) &&
4161 (dev->dev_addr[1] == 0xa0) )
4162 {
4163 for (i = 0; i < ETH_ALEN; ++i)
4164 {
4165 int x = dev->dev_addr[i];
4166 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4167 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4168 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4169 }
4170 }
4171 #endif /* CONFIG_PPC_PMAC */
4172
4173 /* Test for a bad enet address */
4174 status = test_bad_enet(dev, status);
4175
4176 return status;
4177 }
4178
4179 /*
4180 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4181 ** didn't seem to work here...?
4182 */
4183 static int
4184 de4x5_bad_srom(struct de4x5_private *lp)
4185 {
4186 int i, status = 0;
4187
4188 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4189 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4190 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4191 if (i == 0) {
4192 status = SMC;
4193 } else if (i == 1) {
4194 status = ACCTON;
4195 }
4196 break;
4197 }
4198 }
4199
4200 return status;
4201 }
4202
4203 static int
4204 de4x5_strncmp(char *a, char *b, int n)
4205 {
4206 int ret=0;
4207
4208 for (;n && !ret;n--) {
4209 ret = *a++ - *b++;
4210 }
4211
4212 return ret;
4213 }
4214
4215 static void
4216 srom_repair(struct net_device *dev, int card)
4217 {
4218 struct de4x5_private *lp = netdev_priv(dev);
4219
4220 switch(card) {
4221 case SMC:
4222 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4223 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4224 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4225 lp->useSROM = TRUE;
4226 break;
4227 }
4228
4229 return;
4230 }
4231
4232 /*
4233 ** Assume that the irq's do not follow the PCI spec - this is seems
4234 ** to be true so far (2 for 2).
4235 */
4236 static int
4237 test_bad_enet(struct net_device *dev, int status)
4238 {
4239 struct de4x5_private *lp = netdev_priv(dev);
4240 int i, tmp;
4241
4242 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4243 if ((tmp == 0) || (tmp == 0x5fa)) {
4244 if ((lp->chipset == last.chipset) &&
4245 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4246 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4247 for (i=ETH_ALEN-1; i>2; --i) {
4248 dev->dev_addr[i] += 1;
4249 if (dev->dev_addr[i] != 0) break;
4250 }
4251 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4252 if (!an_exception(lp)) {
4253 dev->irq = last.irq;
4254 }
4255
4256 status = 0;
4257 }
4258 } else if (!status) {
4259 last.chipset = lp->chipset;
4260 last.bus = lp->bus_num;
4261 last.irq = dev->irq;
4262 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4263 }
4264
4265 return status;
4266 }
4267
4268 /*
4269 ** List of board exceptions with correctly wired IRQs
4270 */
4271 static int
4272 an_exception(struct de4x5_private *lp)
4273 {
4274 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4275 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4276 return -1;
4277 }
4278
4279 return 0;
4280 }
4281
4282 /*
4283 ** SROM Read
4284 */
4285 static short
4286 srom_rd(u_long addr, u_char offset)
4287 {
4288 sendto_srom(SROM_RD | SROM_SR, addr);
4289
4290 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4291 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4292 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4293
4294 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4295 }
4296
4297 static void
4298 srom_latch(u_int command, u_long addr)
4299 {
4300 sendto_srom(command, addr);
4301 sendto_srom(command | DT_CLK, addr);
4302 sendto_srom(command, addr);
4303
4304 return;
4305 }
4306
4307 static void
4308 srom_command(u_int command, u_long addr)
4309 {
4310 srom_latch(command, addr);
4311 srom_latch(command, addr);
4312 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4313
4314 return;
4315 }
4316
4317 static void
4318 srom_address(u_int command, u_long addr, u_char offset)
4319 {
4320 int i, a;
4321
4322 a = offset << 2;
4323 for (i=0; i<6; i++, a <<= 1) {
4324 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4325 }
4326 udelay(1);
4327
4328 i = (getfrom_srom(addr) >> 3) & 0x01;
4329
4330 return;
4331 }
4332
4333 static short
4334 srom_data(u_int command, u_long addr)
4335 {
4336 int i;
4337 short word = 0;
4338 s32 tmp;
4339
4340 for (i=0; i<16; i++) {
4341 sendto_srom(command | DT_CLK, addr);
4342 tmp = getfrom_srom(addr);
4343 sendto_srom(command, addr);
4344
4345 word = (word << 1) | ((tmp >> 3) & 0x01);
4346 }
4347
4348 sendto_srom(command & 0x0000ff00, addr);
4349
4350 return word;
4351 }
4352
4353 /*
4354 static void
4355 srom_busy(u_int command, u_long addr)
4356 {
4357 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4358
4359 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4360 mdelay(1);
4361 }
4362
4363 sendto_srom(command & 0x0000ff00, addr);
4364
4365 return;
4366 }
4367 */
4368
4369 static void
4370 sendto_srom(u_int command, u_long addr)
4371 {
4372 outl(command, addr);
4373 udelay(1);
4374
4375 return;
4376 }
4377
4378 static int
4379 getfrom_srom(u_long addr)
4380 {
4381 s32 tmp;
4382
4383 tmp = inl(addr);
4384 udelay(1);
4385
4386 return tmp;
4387 }
4388
4389 static int
4390 srom_infoleaf_info(struct net_device *dev)
4391 {
4392 struct de4x5_private *lp = netdev_priv(dev);
4393 int i, count;
4394 u_char *p;
4395
4396 /* Find the infoleaf decoder function that matches this chipset */
4397 for (i=0; i<INFOLEAF_SIZE; i++) {
4398 if (lp->chipset == infoleaf_array[i].chipset) break;
4399 }
4400 if (i == INFOLEAF_SIZE) {
4401 lp->useSROM = FALSE;
4402 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4403 dev->name);
4404 return -ENXIO;
4405 }
4406
4407 lp->infoleaf_fn = infoleaf_array[i].fn;
4408
4409 /* Find the information offset that this function should use */
4410 count = *((u_char *)&lp->srom + 19);
4411 p = (u_char *)&lp->srom + 26;
4412
4413 if (count > 1) {
4414 for (i=count; i; --i, p+=3) {
4415 if (lp->device == *p) break;
4416 }
4417 if (i == 0) {
4418 lp->useSROM = FALSE;
4419 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4420 dev->name, lp->device);
4421 return -ENXIO;
4422 }
4423 }
4424
4425 lp->infoleaf_offset = TWIDDLE(p+1);
4426
4427 return 0;
4428 }
4429
4430 /*
4431 ** This routine loads any type 1 or 3 MII info into the mii device
4432 ** struct and executes any type 5 code to reset PHY devices for this
4433 ** controller.
4434 ** The info for the MII devices will be valid since the index used
4435 ** will follow the discovery process from MII address 1-31 then 0.
4436 */
4437 static void
4438 srom_init(struct net_device *dev)
4439 {
4440 struct de4x5_private *lp = netdev_priv(dev);
4441 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4442 u_char count;
4443
4444 p+=2;
4445 if (lp->chipset == DC21140) {
4446 lp->cache.gepc = (*p++ | GEP_CTRL);
4447 gep_wr(lp->cache.gepc, dev);
4448 }
4449
4450 /* Block count */
4451 count = *p++;
4452
4453 /* Jump the infoblocks to find types */
4454 for (;count; --count) {
4455 if (*p < 128) {
4456 p += COMPACT_LEN;
4457 } else if (*(p+1) == 5) {
4458 type5_infoblock(dev, 1, p);
4459 p += ((*p & BLOCK_LEN) + 1);
4460 } else if (*(p+1) == 4) {
4461 p += ((*p & BLOCK_LEN) + 1);
4462 } else if (*(p+1) == 3) {
4463 type3_infoblock(dev, 1, p);
4464 p += ((*p & BLOCK_LEN) + 1);
4465 } else if (*(p+1) == 2) {
4466 p += ((*p & BLOCK_LEN) + 1);
4467 } else if (*(p+1) == 1) {
4468 type1_infoblock(dev, 1, p);
4469 p += ((*p & BLOCK_LEN) + 1);
4470 } else {
4471 p += ((*p & BLOCK_LEN) + 1);
4472 }
4473 }
4474
4475 return;
4476 }
4477
4478 /*
4479 ** A generic routine that writes GEP control, data and reset information
4480 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4481 */
4482 static void
4483 srom_exec(struct net_device *dev, u_char *p)
4484 {
4485 struct de4x5_private *lp = netdev_priv(dev);
4486 u_long iobase = dev->base_addr;
4487 u_char count = (p ? *p++ : 0);
4488 u_short *w = (u_short *)p;
4489
4490 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4491
4492 if (lp->chipset != DC21140) RESET_SIA;
4493
4494 while (count--) {
4495 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4496 *p++ : TWIDDLE(w++)), dev);
4497 mdelay(2); /* 2ms per action */
4498 }
4499
4500 if (lp->chipset != DC21140) {
4501 outl(lp->cache.csr14, DE4X5_STRR);
4502 outl(lp->cache.csr13, DE4X5_SICR);
4503 }
4504
4505 return;
4506 }
4507
4508 /*
4509 ** Basically this function is a NOP since it will never be called,
4510 ** unless I implement the DC21041 SROM functions. There's no need
4511 ** since the existing code will be satisfactory for all boards.
4512 */
4513 static int
4514 dc21041_infoleaf(struct net_device *dev)
4515 {
4516 return DE4X5_AUTOSENSE_MS;
4517 }
4518
4519 static int
4520 dc21140_infoleaf(struct net_device *dev)
4521 {
4522 struct de4x5_private *lp = netdev_priv(dev);
4523 u_char count = 0;
4524 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4525 int next_tick = DE4X5_AUTOSENSE_MS;
4526
4527 /* Read the connection type */
4528 p+=2;
4529
4530 /* GEP control */
4531 lp->cache.gepc = (*p++ | GEP_CTRL);
4532
4533 /* Block count */
4534 count = *p++;
4535
4536 /* Recursively figure out the info blocks */
4537 if (*p < 128) {
4538 next_tick = dc_infoblock[COMPACT](dev, count, p);
4539 } else {
4540 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4541 }
4542
4543 if (lp->tcount == count) {
4544 lp->media = NC;
4545 if (lp->media != lp->c_media) {
4546 de4x5_dbg_media(dev);
4547 lp->c_media = lp->media;
4548 }
4549 lp->media = INIT;
4550 lp->tcount = 0;
4551 lp->tx_enable = FALSE;
4552 }
4553
4554 return next_tick & ~TIMER_CB;
4555 }
4556
4557 static int
4558 dc21142_infoleaf(struct net_device *dev)
4559 {
4560 struct de4x5_private *lp = netdev_priv(dev);
4561 u_char count = 0;
4562 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4563 int next_tick = DE4X5_AUTOSENSE_MS;
4564
4565 /* Read the connection type */
4566 p+=2;
4567
4568 /* Block count */
4569 count = *p++;
4570
4571 /* Recursively figure out the info blocks */
4572 if (*p < 128) {
4573 next_tick = dc_infoblock[COMPACT](dev, count, p);
4574 } else {
4575 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4576 }
4577
4578 if (lp->tcount == count) {
4579 lp->media = NC;
4580 if (lp->media != lp->c_media) {
4581 de4x5_dbg_media(dev);
4582 lp->c_media = lp->media;
4583 }
4584 lp->media = INIT;
4585 lp->tcount = 0;
4586 lp->tx_enable = FALSE;
4587 }
4588
4589 return next_tick & ~TIMER_CB;
4590 }
4591
4592 static int
4593 dc21143_infoleaf(struct net_device *dev)
4594 {
4595 struct de4x5_private *lp = netdev_priv(dev);
4596 u_char count = 0;
4597 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4598 int next_tick = DE4X5_AUTOSENSE_MS;
4599
4600 /* Read the connection type */
4601 p+=2;
4602
4603 /* Block count */
4604 count = *p++;
4605
4606 /* Recursively figure out the info blocks */
4607 if (*p < 128) {
4608 next_tick = dc_infoblock[COMPACT](dev, count, p);
4609 } else {
4610 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4611 }
4612 if (lp->tcount == count) {
4613 lp->media = NC;
4614 if (lp->media != lp->c_media) {
4615 de4x5_dbg_media(dev);
4616 lp->c_media = lp->media;
4617 }
4618 lp->media = INIT;
4619 lp->tcount = 0;
4620 lp->tx_enable = FALSE;
4621 }
4622
4623 return next_tick & ~TIMER_CB;
4624 }
4625
4626 /*
4627 ** The compact infoblock is only designed for DC21140[A] chips, so
4628 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4629 */
4630 static int
4631 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4632 {
4633 struct de4x5_private *lp = netdev_priv(dev);
4634 u_char flags, csr6;
4635
4636 /* Recursively figure out the info blocks */
4637 if (--count > lp->tcount) {
4638 if (*(p+COMPACT_LEN) < 128) {
4639 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4640 } else {
4641 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4642 }
4643 }
4644
4645 if ((lp->media == INIT) && (lp->timeout < 0)) {
4646 lp->ibn = COMPACT;
4647 lp->active = 0;
4648 gep_wr(lp->cache.gepc, dev);
4649 lp->infoblock_media = (*p++) & COMPACT_MC;
4650 lp->cache.gep = *p++;
4651 csr6 = *p++;
4652 flags = *p++;
4653
4654 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4655 lp->defMedium = (flags & 0x40) ? -1 : 0;
4656 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4657 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4658 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4659 lp->useMII = FALSE;
4660
4661 de4x5_switch_mac_port(dev);
4662 }
4663
4664 return dc21140m_autoconf(dev);
4665 }
4666
4667 /*
4668 ** This block describes non MII media for the DC21140[A] only.
4669 */
4670 static int
4671 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4672 {
4673 struct de4x5_private *lp = netdev_priv(dev);
4674 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4675
4676 /* Recursively figure out the info blocks */
4677 if (--count > lp->tcount) {
4678 if (*(p+len) < 128) {
4679 return dc_infoblock[COMPACT](dev, count, p+len);
4680 } else {
4681 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4682 }
4683 }
4684
4685 if ((lp->media == INIT) && (lp->timeout < 0)) {
4686 lp->ibn = 0;
4687 lp->active = 0;
4688 gep_wr(lp->cache.gepc, dev);
4689 p+=2;
4690 lp->infoblock_media = (*p++) & BLOCK0_MC;
4691 lp->cache.gep = *p++;
4692 csr6 = *p++;
4693 flags = *p++;
4694
4695 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4696 lp->defMedium = (flags & 0x40) ? -1 : 0;
4697 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4698 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4699 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4700 lp->useMII = FALSE;
4701
4702 de4x5_switch_mac_port(dev);
4703 }
4704
4705 return dc21140m_autoconf(dev);
4706 }
4707
4708 /* These functions are under construction! */
4709
4710 static int
4711 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4712 {
4713 struct de4x5_private *lp = netdev_priv(dev);
4714 u_char len = (*p & BLOCK_LEN)+1;
4715
4716 /* Recursively figure out the info blocks */
4717 if (--count > lp->tcount) {
4718 if (*(p+len) < 128) {
4719 return dc_infoblock[COMPACT](dev, count, p+len);
4720 } else {
4721 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4722 }
4723 }
4724
4725 p += 2;
4726 if (lp->state == INITIALISED) {
4727 lp->ibn = 1;
4728 lp->active = *p++;
4729 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4730 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4731 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4732 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4733 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4734 lp->phy[lp->active].ttm = TWIDDLE(p);
4735 return 0;
4736 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4737 lp->ibn = 1;
4738 lp->active = *p;
4739 lp->infoblock_csr6 = OMR_MII_100;
4740 lp->useMII = TRUE;
4741 lp->infoblock_media = ANS;
4742
4743 de4x5_switch_mac_port(dev);
4744 }
4745
4746 return dc21140m_autoconf(dev);
4747 }
4748
4749 static int
4750 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4751 {
4752 struct de4x5_private *lp = netdev_priv(dev);
4753 u_char len = (*p & BLOCK_LEN)+1;
4754
4755 /* Recursively figure out the info blocks */
4756 if (--count > lp->tcount) {
4757 if (*(p+len) < 128) {
4758 return dc_infoblock[COMPACT](dev, count, p+len);
4759 } else {
4760 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4761 }
4762 }
4763
4764 if ((lp->media == INIT) && (lp->timeout < 0)) {
4765 lp->ibn = 2;
4766 lp->active = 0;
4767 p += 2;
4768 lp->infoblock_media = (*p) & MEDIA_CODE;
4769
4770 if ((*p++) & EXT_FIELD) {
4771 lp->cache.csr13 = TWIDDLE(p); p += 2;
4772 lp->cache.csr14 = TWIDDLE(p); p += 2;
4773 lp->cache.csr15 = TWIDDLE(p); p += 2;
4774 } else {
4775 lp->cache.csr13 = CSR13;
4776 lp->cache.csr14 = CSR14;
4777 lp->cache.csr15 = CSR15;
4778 }
4779 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4780 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4781 lp->infoblock_csr6 = OMR_SIA;
4782 lp->useMII = FALSE;
4783
4784 de4x5_switch_mac_port(dev);
4785 }
4786
4787 return dc2114x_autoconf(dev);
4788 }
4789
4790 static int
4791 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4792 {
4793 struct de4x5_private *lp = netdev_priv(dev);
4794 u_char len = (*p & BLOCK_LEN)+1;
4795
4796 /* Recursively figure out the info blocks */
4797 if (--count > lp->tcount) {
4798 if (*(p+len) < 128) {
4799 return dc_infoblock[COMPACT](dev, count, p+len);
4800 } else {
4801 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4802 }
4803 }
4804
4805 p += 2;
4806 if (lp->state == INITIALISED) {
4807 lp->ibn = 3;
4808 lp->active = *p++;
4809 if (MOTO_SROM_BUG) lp->active = 0;
4810 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4811 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4812 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4813 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4814 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4815 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4816 lp->phy[lp->active].mci = *p;
4817 return 0;
4818 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4819 lp->ibn = 3;
4820 lp->active = *p;
4821 if (MOTO_SROM_BUG) lp->active = 0;
4822 lp->infoblock_csr6 = OMR_MII_100;
4823 lp->useMII = TRUE;
4824 lp->infoblock_media = ANS;
4825
4826 de4x5_switch_mac_port(dev);
4827 }
4828
4829 return dc2114x_autoconf(dev);
4830 }
4831
4832 static int
4833 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4834 {
4835 struct de4x5_private *lp = netdev_priv(dev);
4836 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4837
4838 /* Recursively figure out the info blocks */
4839 if (--count > lp->tcount) {
4840 if (*(p+len) < 128) {
4841 return dc_infoblock[COMPACT](dev, count, p+len);
4842 } else {
4843 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4844 }
4845 }
4846
4847 if ((lp->media == INIT) && (lp->timeout < 0)) {
4848 lp->ibn = 4;
4849 lp->active = 0;
4850 p+=2;
4851 lp->infoblock_media = (*p++) & MEDIA_CODE;
4852 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4853 lp->cache.csr14 = CSR14;
4854 lp->cache.csr15 = CSR15;
4855 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4856 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4857 csr6 = *p++;
4858 flags = *p++;
4859
4860 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4861 lp->defMedium = (flags & 0x40) ? -1 : 0;
4862 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4863 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4864 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4865 lp->useMII = FALSE;
4866
4867 de4x5_switch_mac_port(dev);
4868 }
4869
4870 return dc2114x_autoconf(dev);
4871 }
4872
4873 /*
4874 ** This block type provides information for resetting external devices
4875 ** (chips) through the General Purpose Register.
4876 */
4877 static int
4878 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4879 {
4880 struct de4x5_private *lp = netdev_priv(dev);
4881 u_char len = (*p & BLOCK_LEN)+1;
4882
4883 /* Recursively figure out the info blocks */
4884 if (--count > lp->tcount) {
4885 if (*(p+len) < 128) {
4886 return dc_infoblock[COMPACT](dev, count, p+len);
4887 } else {
4888 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4889 }
4890 }
4891
4892 /* Must be initializing to run this code */
4893 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4894 p+=2;
4895 lp->rst = p;
4896 srom_exec(dev, lp->rst);
4897 }
4898
4899 return DE4X5_AUTOSENSE_MS;
4900 }
4901
4902 /*
4903 ** MII Read/Write
4904 */
4905
4906 static int
4907 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4908 {
4909 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4910 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4911 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4912 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4913 mii_address(phyreg, ioaddr); /* PHY Register to read */
4914 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4915
4916 return mii_rdata(ioaddr); /* Read data */
4917 }
4918
4919 static void
4920 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4921 {
4922 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4923 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4924 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4925 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4926 mii_address(phyreg, ioaddr); /* PHY Register to write */
4927 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4928 data = mii_swap(data, 16); /* Swap data bit ordering */
4929 mii_wdata(data, 16, ioaddr); /* Write data */
4930
4931 return;
4932 }
4933
4934 static int
4935 mii_rdata(u_long ioaddr)
4936 {
4937 int i;
4938 s32 tmp = 0;
4939
4940 for (i=0; i<16; i++) {
4941 tmp <<= 1;
4942 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4943 }
4944
4945 return tmp;
4946 }
4947
4948 static void
4949 mii_wdata(int data, int len, u_long ioaddr)
4950 {
4951 int i;
4952
4953 for (i=0; i<len; i++) {
4954 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4955 data >>= 1;
4956 }
4957
4958 return;
4959 }
4960
4961 static void
4962 mii_address(u_char addr, u_long ioaddr)
4963 {
4964 int i;
4965
4966 addr = mii_swap(addr, 5);
4967 for (i=0; i<5; i++) {
4968 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4969 addr >>= 1;
4970 }
4971
4972 return;
4973 }
4974
4975 static void
4976 mii_ta(u_long rw, u_long ioaddr)
4977 {
4978 if (rw == MII_STWR) {
4979 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4980 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4981 } else {
4982 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4983 }
4984
4985 return;
4986 }
4987
4988 static int
4989 mii_swap(int data, int len)
4990 {
4991 int i, tmp = 0;
4992
4993 for (i=0; i<len; i++) {
4994 tmp <<= 1;
4995 tmp |= (data & 1);
4996 data >>= 1;
4997 }
4998
4999 return tmp;
5000 }
5001
5002 static void
5003 sendto_mii(u32 command, int data, u_long ioaddr)
5004 {
5005 u32 j;
5006
5007 j = (data & 1) << 17;
5008 outl(command | j, ioaddr);
5009 udelay(1);
5010 outl(command | MII_MDC | j, ioaddr);
5011 udelay(1);
5012
5013 return;
5014 }
5015
5016 static int
5017 getfrom_mii(u32 command, u_long ioaddr)
5018 {
5019 outl(command, ioaddr);
5020 udelay(1);
5021 outl(command | MII_MDC, ioaddr);
5022 udelay(1);
5023
5024 return ((inl(ioaddr) >> 19) & 1);
5025 }
5026
5027 /*
5028 ** Here's 3 ways to calculate the OUI from the ID registers.
5029 */
5030 static int
5031 mii_get_oui(u_char phyaddr, u_long ioaddr)
5032 {
5033 /*
5034 union {
5035 u_short reg;
5036 u_char breg[2];
5037 } a;
5038 int i, r2, r3, ret=0;*/
5039 int r2, r3;
5040
5041 /* Read r2 and r3 */
5042 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5043 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5044 /* SEEQ and Cypress way * /
5045 / * Shuffle r2 and r3 * /
5046 a.reg=0;
5047 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5048 r2 = ((r2>>2)&0x3fff);
5049
5050 / * Bit reverse r3 * /
5051 for (i=0;i<8;i++) {
5052 ret<<=1;
5053 ret |= (r3&1);
5054 r3>>=1;
5055 }
5056
5057 / * Bit reverse r2 * /
5058 for (i=0;i<16;i++) {
5059 a.reg<<=1;
5060 a.reg |= (r2&1);
5061 r2>>=1;
5062 }
5063
5064 / * Swap r2 bytes * /
5065 i=a.breg[0];
5066 a.breg[0]=a.breg[1];
5067 a.breg[1]=i;
5068
5069 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5070 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5071 return r2; /* (I did it) My way */
5072 }
5073
5074 /*
5075 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5076 */
5077 static int
5078 mii_get_phy(struct net_device *dev)
5079 {
5080 struct de4x5_private *lp = netdev_priv(dev);
5081 u_long iobase = dev->base_addr;
5082 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5083 int id;
5084
5085 lp->active = 0;
5086 lp->useMII = TRUE;
5087
5088 /* Search the MII address space for possible PHY devices */
5089 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5090 lp->phy[lp->active].addr = i;
5091 if (i==0) n++; /* Count cycles */
5092 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5093 id = mii_get_oui(i, DE4X5_MII);
5094 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5095 for (j=0; j<limit; j++) { /* Search PHY table */
5096 if (id != phy_info[j].id) continue; /* ID match? */
5097 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5098 if (k < DE4X5_MAX_PHY) {
5099 memcpy((char *)&lp->phy[k],
5100 (char *)&phy_info[j], sizeof(struct phy_table));
5101 lp->phy[k].addr = i;
5102 lp->mii_cnt++;
5103 lp->active++;
5104 } else {
5105 goto purgatory; /* Stop the search */
5106 }
5107 break;
5108 }
5109 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5110 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5111 lp->phy[k].addr = i;
5112 lp->phy[k].id = id;
5113 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5114 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5115 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5116 lp->mii_cnt++;
5117 lp->active++;
5118 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5119 j = de4x5_debug;
5120 de4x5_debug |= DEBUG_MII;
5121 de4x5_dbg_mii(dev, k);
5122 de4x5_debug = j;
5123 printk("\n");
5124 }
5125 }
5126 purgatory:
5127 lp->active = 0;
5128 if (lp->phy[0].id) { /* Reset the PHY devices */
5129 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5130 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5131 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5132
5133 de4x5_dbg_mii(dev, k);
5134 }
5135 }
5136 if (!lp->mii_cnt) lp->useMII = FALSE;
5137
5138 return lp->mii_cnt;
5139 }
5140
5141 static char *
5142 build_setup_frame(struct net_device *dev, int mode)
5143 {
5144 struct de4x5_private *lp = netdev_priv(dev);
5145 int i;
5146 char *pa = lp->setup_frame;
5147
5148 /* Initialise the setup frame */
5149 if (mode == ALL) {
5150 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5151 }
5152
5153 if (lp->setup_f == HASH_PERF) {
5154 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5155 *(pa + i) = dev->dev_addr[i]; /* Host address */
5156 if (i & 0x01) pa += 2;
5157 }
5158 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5159 } else {
5160 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5161 *(pa + (i&1)) = dev->dev_addr[i];
5162 if (i & 0x01) pa += 4;
5163 }
5164 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5165 *(pa + (i&1)) = (char) 0xff;
5166 if (i & 0x01) pa += 4;
5167 }
5168 }
5169
5170 return pa; /* Points to the next entry */
5171 }
5172
5173 static void
5174 enable_ast(struct net_device *dev, u32 time_out)
5175 {
5176 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5177
5178 return;
5179 }
5180
5181 static void
5182 disable_ast(struct net_device *dev)
5183 {
5184 struct de4x5_private *lp = netdev_priv(dev);
5185
5186 del_timer(&lp->timer);
5187
5188 return;
5189 }
5190
5191 static long
5192 de4x5_switch_mac_port(struct net_device *dev)
5193 {
5194 struct de4x5_private *lp = netdev_priv(dev);
5195 u_long iobase = dev->base_addr;
5196 s32 omr;
5197
5198 STOP_DE4X5;
5199
5200 /* Assert the OMR_PS bit in CSR6 */
5201 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5202 OMR_FDX));
5203 omr |= lp->infoblock_csr6;
5204 if (omr & OMR_PS) omr |= OMR_HBD;
5205 outl(omr, DE4X5_OMR);
5206
5207 /* Soft Reset */
5208 RESET_DE4X5;
5209
5210 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5211 if (lp->chipset == DC21140) {
5212 gep_wr(lp->cache.gepc, dev);
5213 gep_wr(lp->cache.gep, dev);
5214 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5215 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5216 }
5217
5218 /* Restore CSR6 */
5219 outl(omr, DE4X5_OMR);
5220
5221 /* Reset CSR8 */
5222 inl(DE4X5_MFC);
5223
5224 return omr;
5225 }
5226
5227 static void
5228 gep_wr(s32 data, struct net_device *dev)
5229 {
5230 struct de4x5_private *lp = netdev_priv(dev);
5231 u_long iobase = dev->base_addr;
5232
5233 if (lp->chipset == DC21140) {
5234 outl(data, DE4X5_GEP);
5235 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5236 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5237 }
5238
5239 return;
5240 }
5241
5242 static int
5243 gep_rd(struct net_device *dev)
5244 {
5245 struct de4x5_private *lp = netdev_priv(dev);
5246 u_long iobase = dev->base_addr;
5247
5248 if (lp->chipset == DC21140) {
5249 return inl(DE4X5_GEP);
5250 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5251 return (inl(DE4X5_SIGR) & 0x000fffff);
5252 }
5253
5254 return 0;
5255 }
5256
5257 static void
5258 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5259 {
5260 struct de4x5_private *lp = netdev_priv(dev);
5261 int dt;
5262
5263 /* First, cancel any pending timer events */
5264 del_timer(&lp->timer);
5265
5266 /* Convert msec to ticks */
5267 dt = (msec * HZ) / 1000;
5268 if (dt==0) dt=1;
5269
5270 /* Set up timer */
5271 init_timer(&lp->timer);
5272 lp->timer.expires = jiffies + dt;
5273 lp->timer.function = fn;
5274 lp->timer.data = data;
5275 add_timer(&lp->timer);
5276
5277 return;
5278 }
5279
5280 static void
5281 yawn(struct net_device *dev, int state)
5282 {
5283 struct de4x5_private *lp = netdev_priv(dev);
5284 u_long iobase = dev->base_addr;
5285
5286 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5287
5288 if(lp->bus == EISA) {
5289 switch(state) {
5290 case WAKEUP:
5291 outb(WAKEUP, PCI_CFPM);
5292 mdelay(10);
5293 break;
5294
5295 case SNOOZE:
5296 outb(SNOOZE, PCI_CFPM);
5297 break;
5298
5299 case SLEEP:
5300 outl(0, DE4X5_SICR);
5301 outb(SLEEP, PCI_CFPM);
5302 break;
5303 }
5304 } else {
5305 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5306 switch(state) {
5307 case WAKEUP:
5308 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5309 mdelay(10);
5310 break;
5311
5312 case SNOOZE:
5313 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5314 break;
5315
5316 case SLEEP:
5317 outl(0, DE4X5_SICR);
5318 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5319 break;
5320 }
5321 }
5322
5323 return;
5324 }
5325
5326 static void
5327 de4x5_parse_params(struct net_device *dev)
5328 {
5329 struct de4x5_private *lp = netdev_priv(dev);
5330 char *p, *q, t;
5331
5332 lp->params.fdx = 0;
5333 lp->params.autosense = AUTO;
5334
5335 if (args == NULL) return;
5336
5337 if ((p = strstr(args, dev->name))) {
5338 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5339 t = *q;
5340 *q = '\0';
5341
5342 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5343
5344 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5345 if (strstr(p, "TP")) {
5346 lp->params.autosense = TP;
5347 } else if (strstr(p, "TP_NW")) {
5348 lp->params.autosense = TP_NW;
5349 } else if (strstr(p, "BNC")) {
5350 lp->params.autosense = BNC;
5351 } else if (strstr(p, "AUI")) {
5352 lp->params.autosense = AUI;
5353 } else if (strstr(p, "BNC_AUI")) {
5354 lp->params.autosense = BNC;
5355 } else if (strstr(p, "10Mb")) {
5356 lp->params.autosense = _10Mb;
5357 } else if (strstr(p, "100Mb")) {
5358 lp->params.autosense = _100Mb;
5359 } else if (strstr(p, "AUTO")) {
5360 lp->params.autosense = AUTO;
5361 }
5362 }
5363 *q = t;
5364 }
5365
5366 return;
5367 }
5368
5369 static void
5370 de4x5_dbg_open(struct net_device *dev)
5371 {
5372 struct de4x5_private *lp = netdev_priv(dev);
5373 int i;
5374
5375 if (de4x5_debug & DEBUG_OPEN) {
5376 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5377 printk("\tphysical address: ");
5378 for (i=0;i<6;i++) {
5379 printk("%2.2x:",(short)dev->dev_addr[i]);
5380 }
5381 printk("\n");
5382 printk("Descriptor head addresses:\n");
5383 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5384 printk("Descriptor addresses:\nRX: ");
5385 for (i=0;i<lp->rxRingSize-1;i++){
5386 if (i < 3) {
5387 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5388 }
5389 }
5390 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5391 printk("TX: ");
5392 for (i=0;i<lp->txRingSize-1;i++){
5393 if (i < 3) {
5394 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5395 }
5396 }
5397 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5398 printk("Descriptor buffers:\nRX: ");
5399 for (i=0;i<lp->rxRingSize-1;i++){
5400 if (i < 3) {
5401 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5402 }
5403 }
5404 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5405 printk("TX: ");
5406 for (i=0;i<lp->txRingSize-1;i++){
5407 if (i < 3) {
5408 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5409 }
5410 }
5411 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5412 printk("Ring size: \nRX: %d\nTX: %d\n",
5413 (short)lp->rxRingSize,
5414 (short)lp->txRingSize);
5415 }
5416
5417 return;
5418 }
5419
5420 static void
5421 de4x5_dbg_mii(struct net_device *dev, int k)
5422 {
5423 struct de4x5_private *lp = netdev_priv(dev);
5424 u_long iobase = dev->base_addr;
5425
5426 if (de4x5_debug & DEBUG_MII) {
5427 printk("\nMII device address: %d\n", lp->phy[k].addr);
5428 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5429 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5430 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5431 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5432 if (lp->phy[k].id != BROADCOM_T4) {
5433 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5435 }
5436 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5437 if (lp->phy[k].id != BROADCOM_T4) {
5438 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5439 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5440 } else {
5441 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5442 }
5443 }
5444
5445 return;
5446 }
5447
5448 static void
5449 de4x5_dbg_media(struct net_device *dev)
5450 {
5451 struct de4x5_private *lp = netdev_priv(dev);
5452
5453 if (lp->media != lp->c_media) {
5454 if (de4x5_debug & DEBUG_MEDIA) {
5455 printk("%s: media is %s%s\n", dev->name,
5456 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5457 (lp->media == TP ? "TP" :
5458 (lp->media == ANS ? "TP/Nway" :
5459 (lp->media == BNC ? "BNC" :
5460 (lp->media == AUI ? "AUI" :
5461 (lp->media == BNC_AUI ? "BNC/AUI" :
5462 (lp->media == EXT_SIA ? "EXT SIA" :
5463 (lp->media == _100Mb ? "100Mb/s" :
5464 (lp->media == _10Mb ? "10Mb/s" :
5465 "???"
5466 ))))))))), (lp->fdx?" full duplex.":"."));
5467 }
5468 lp->c_media = lp->media;
5469 }
5470
5471 return;
5472 }
5473
5474 static void
5475 de4x5_dbg_srom(struct de4x5_srom *p)
5476 {
5477 int i;
5478
5479 if (de4x5_debug & DEBUG_SROM) {
5480 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5481 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5482 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5483 printk("SROM version: %02x\n", (u_char)(p->version));
5484 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5485
5486 printk("Hardware Address: ");
5487 for (i=0;i<ETH_ALEN-1;i++) {
5488 printk("%02x:", (u_char)*(p->ieee_addr+i));
5489 }
5490 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5491 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5492 for (i=0; i<64; i++) {
5493 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5494 }
5495 }
5496
5497 return;
5498 }
5499
5500 static void
5501 de4x5_dbg_rx(struct sk_buff *skb, int len)
5502 {
5503 int i, j;
5504
5505 if (de4x5_debug & DEBUG_RX) {
5506 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5507 (u_char)skb->data[0],
5508 (u_char)skb->data[1],
5509 (u_char)skb->data[2],
5510 (u_char)skb->data[3],
5511 (u_char)skb->data[4],
5512 (u_char)skb->data[5],
5513 (u_char)skb->data[6],
5514 (u_char)skb->data[7],
5515 (u_char)skb->data[8],
5516 (u_char)skb->data[9],
5517 (u_char)skb->data[10],
5518 (u_char)skb->data[11],
5519 (u_char)skb->data[12],
5520 (u_char)skb->data[13],
5521 len);
5522 for (j=0; len>0;j+=16, len-=16) {
5523 printk(" %03x: ",j);
5524 for (i=0; i<16 && i<len; i++) {
5525 printk("%02x ",(u_char)skb->data[i+j]);
5526 }
5527 printk("\n");
5528 }
5529 }
5530
5531 return;
5532 }
5533
5534 /*
5535 ** Perform IOCTL call functions here. Some are privileged operations and the
5536 ** effective uid is checked in those cases. In the normal course of events
5537 ** this function is only used for my testing.
5538 */
5539 static int
5540 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5541 {
5542 struct de4x5_private *lp = netdev_priv(dev);
5543 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5544 u_long iobase = dev->base_addr;
5545 int i, j, status = 0;
5546 s32 omr;
5547 union {
5548 u8 addr[144];
5549 u16 sval[72];
5550 u32 lval[36];
5551 } tmp;
5552 u_long flags = 0;
5553
5554 switch(ioc->cmd) {
5555 case DE4X5_GET_HWADDR: /* Get the hardware address */
5556 ioc->len = ETH_ALEN;
5557 for (i=0; i<ETH_ALEN; i++) {
5558 tmp.addr[i] = dev->dev_addr[i];
5559 }
5560 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5561 break;
5562
5563 case DE4X5_SET_HWADDR: /* Set the hardware address */
5564 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5565 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5566 if (netif_queue_stopped(dev))
5567 return -EBUSY;
5568 netif_stop_queue(dev);
5569 for (i=0; i<ETH_ALEN; i++) {
5570 dev->dev_addr[i] = tmp.addr[i];
5571 }
5572 build_setup_frame(dev, PHYS_ADDR_ONLY);
5573 /* Set up the descriptor and give ownership to the card */
5574 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5575 SETUP_FRAME_LEN, (struct sk_buff *)1);
5576 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5577 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5578 netif_wake_queue(dev); /* Unlock the TX ring */
5579 break;
5580
5581 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5582 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5583 omr = inl(DE4X5_OMR);
5584 omr |= OMR_PR;
5585 outl(omr, DE4X5_OMR);
5586 dev->flags |= IFF_PROMISC;
5587 break;
5588
5589 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5590 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5591 omr = inl(DE4X5_OMR);
5592 omr &= ~OMR_PR;
5593 outl(omr, DE4X5_OMR);
5594 dev->flags &= ~IFF_PROMISC;
5595 break;
5596
5597 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5598 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5599 printk("%s: Boo!\n", dev->name);
5600 break;
5601
5602 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5603 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5604 omr = inl(DE4X5_OMR);
5605 omr |= OMR_PM;
5606 outl(omr, DE4X5_OMR);
5607 break;
5608
5609 case DE4X5_GET_STATS: /* Get the driver statistics */
5610 {
5611 struct pkt_stats statbuf;
5612 ioc->len = sizeof(statbuf);
5613 spin_lock_irqsave(&lp->lock, flags);
5614 memcpy(&statbuf, &lp->pktStats, ioc->len);
5615 spin_unlock_irqrestore(&lp->lock, flags);
5616 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5617 return -EFAULT;
5618 break;
5619 }
5620 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5621 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5622 spin_lock_irqsave(&lp->lock, flags);
5623 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5624 spin_unlock_irqrestore(&lp->lock, flags);
5625 break;
5626
5627 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5628 tmp.addr[0] = inl(DE4X5_OMR);
5629 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5630 break;
5631
5632 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5633 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5634 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5635 outl(tmp.addr[0], DE4X5_OMR);
5636 break;
5637
5638 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5639 j = 0;
5640 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5641 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5642 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5643 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5644 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5645 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5646 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5647 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5648 ioc->len = j;
5649 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5650 break;
5651
5652 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5653 /*
5654 case DE4X5_DUMP:
5655 j = 0;
5656 tmp.addr[j++] = dev->irq;
5657 for (i=0; i<ETH_ALEN; i++) {
5658 tmp.addr[j++] = dev->dev_addr[i];
5659 }
5660 tmp.addr[j++] = lp->rxRingSize;
5661 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5662 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5663
5664 for (i=0;i<lp->rxRingSize-1;i++){
5665 if (i < 3) {
5666 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5667 }
5668 }
5669 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5670 for (i=0;i<lp->txRingSize-1;i++){
5671 if (i < 3) {
5672 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5673 }
5674 }
5675 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5676
5677 for (i=0;i<lp->rxRingSize-1;i++){
5678 if (i < 3) {
5679 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5680 }
5681 }
5682 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5683 for (i=0;i<lp->txRingSize-1;i++){
5684 if (i < 3) {
5685 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5686 }
5687 }
5688 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5689
5690 for (i=0;i<lp->rxRingSize;i++){
5691 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5692 }
5693 for (i=0;i<lp->txRingSize;i++){
5694 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5695 }
5696
5697 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5699 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5700 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5701 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5703 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5705 tmp.lval[j>>2] = lp->chipset; j+=4;
5706 if (lp->chipset == DC21140) {
5707 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5708 } else {
5709 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5710 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5711 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5712 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5713 }
5714 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5715 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5716 tmp.lval[j>>2] = lp->active; j+=4;
5717 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5719 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5720 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 if (lp->phy[lp->active].id != BROADCOM_T4) {
5722 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 }
5725 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5726 if (lp->phy[lp->active].id != BROADCOM_T4) {
5727 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5728 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5729 } else {
5730 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5731 }
5732 }
5733
5734 tmp.addr[j++] = lp->txRingSize;
5735 tmp.addr[j++] = netif_queue_stopped(dev);
5736
5737 ioc->len = j;
5738 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5739 break;
5740
5741 */
5742 default:
5743 return -EOPNOTSUPP;
5744 }
5745
5746 return status;
5747 }
5748
5749 static int __init de4x5_module_init (void)
5750 {
5751 int err = 0;
5752
5753 #ifdef CONFIG_PCI
5754 err = pci_register_driver(&de4x5_pci_driver);
5755 #endif
5756 #ifdef CONFIG_EISA
5757 err |= eisa_driver_register (&de4x5_eisa_driver);
5758 #endif
5759
5760 return err;
5761 }
5762
5763 static void __exit de4x5_module_exit (void)
5764 {
5765 #ifdef CONFIG_PCI
5766 pci_unregister_driver (&de4x5_pci_driver);
5767 #endif
5768 #ifdef CONFIG_EISA
5769 eisa_driver_unregister (&de4x5_eisa_driver);
5770 #endif
5771 }
5772
5773 module_init (de4x5_module_init);
5774 module_exit (de4x5_module_exit);
linux kernel for loongson