include/asm-blackfin/mach-bf533/bf533.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf533/bf533.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef __MACH_BF533_H__
  31 #define __MACH_BF533_H__
  32
  33 #define SUPPORTED_REVID 2
  34
  35 #define OFFSET_(x) ((x) & 0x0000FFFF)
  36
  37 /*some misc defines*/
  38 #define IMASK_IVG15             0x8000
  39 #define IMASK_IVG14             0x4000
  40 #define IMASK_IVG13             0x2000
  41 #define IMASK_IVG12             0x1000
  42
  43 #define IMASK_IVG11             0x0800
  44 #define IMASK_IVG10             0x0400
  45 #define IMASK_IVG9              0x0200
  46 #define IMASK_IVG8              0x0100
  47
  48 #define IMASK_IVG7              0x0080
  49 #define IMASK_IVGTMR            0x0040
  50 #define IMASK_IVGHW             0x0020
  51
  52 /***************************/
  53
  54
  55 #define BLKFIN_DSUBBANKS        4
  56 #define BLKFIN_DWAYS            2
  57 #define BLKFIN_DLINES           64
  58 #define BLKFIN_ISUBBANKS        4
  59 #define BLKFIN_IWAYS            4
  60 #define BLKFIN_ILINES           32
  61
  62 #define WAY0_L                  0x1
  63 #define WAY1_L                  0x2
  64 #define WAY01_L                 0x3
  65 #define WAY2_L                  0x4
  66 #define WAY02_L                 0x5
  67 #define WAY12_L                 0x6
  68 #define WAY012_L                0x7
  69
  70 #define WAY3_L                  0x8
  71 #define WAY03_L                 0x9
  72 #define WAY13_L                 0xA
  73 #define WAY013_L                0xB
  74
  75 #define WAY32_L                 0xC
  76 #define WAY320_L                0xD
  77 #define WAY321_L                0xE
  78 #define WAYALL_L                0xF
  79
  80 #define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
  81
  82 /* IAR0 BIT FIELDS*/
  83 #define RTC_ERROR_BIT                   0x0FFFFFFF
  84 #define UART_ERROR_BIT                  0xF0FFFFFF
  85 #define SPORT1_ERROR_BIT                0xFF0FFFFF
  86 #define SPI_ERROR_BIT                   0xFFF0FFFF
  87 #define SPORT0_ERROR_BIT                0xFFFF0FFF
  88 #define PPI_ERROR_BIT                   0xFFFFF0FF
  89 #define DMA_ERROR_BIT                   0xFFFFFF0F
  90 #define PLLWAKE_ERROR_BIT               0xFFFFFFFF
  91
  92 /* IAR1 BIT FIELDS*/
  93 #define DMA7_UARTTX_BIT                 0x0FFFFFFF
  94 #define DMA6_UARTRX_BIT                 0xF0FFFFFF
  95 #define DMA5_SPI_BIT                    0xFF0FFFFF
  96 #define DMA4_SPORT1TX_BIT               0xFFF0FFFF
  97 #define DMA3_SPORT1RX_BIT               0xFFFF0FFF
  98 #define DMA2_SPORT0TX_BIT               0xFFFFF0FF
  99 #define DMA1_SPORT0RX_BIT               0xFFFFFF0F
 100 #define DMA0_PPI_BIT                    0xFFFFFFFF
 101
 102 /* IAR2 BIT FIELDS*/
 103 #define WDTIMER_BIT                     0x0FFFFFFF
 104 #define MEMDMA1_BIT                     0xF0FFFFFF
 105 #define MEMDMA0_BIT                     0xFF0FFFFF
 106 #define PFB_BIT                         0xFFF0FFFF
 107 #define PFA_BIT                         0xFFFF0FFF
 108 #define TIMER2_BIT                      0xFFFFF0FF
 109 #define TIMER1_BIT                      0xFFFFFF0F
 110 #define TIMER0_BIT                      0xFFFFFFFF
 111
 112 /********************************* EBIU Settings ************************************/
 113 #define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
 114 #define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
 115
 116 #ifdef CONFIG_C_AMBEN_ALL
 117 #define V_AMBEN AMBEN_ALL
 118 #endif
 119 #ifdef CONFIG_C_AMBEN
 120 #define V_AMBEN 0x0
 121 #endif
 122 #ifdef CONFIG_C_AMBEN_B0
 123 #define V_AMBEN AMBEN_B0
 124 #endif
 125 #ifdef CONFIG_C_AMBEN_B0_B1
 126 #define V_AMBEN AMBEN_B0_B1
 127 #endif
 128 #ifdef CONFIG_C_AMBEN_B0_B1_B2
 129 #define V_AMBEN AMBEN_B0_B1_B2
 130 #endif
 131 #ifdef CONFIG_C_AMCKEN
 132 #define V_AMCKEN AMCKEN
 133 #else
 134 #define V_AMCKEN 0x0
 135 #endif
 136 #ifdef CONFIG_C_CDPRIO
 137 #define V_CDPRIO 0x100
 138 #else
 139 #define V_CDPRIO 0x0
 140 #endif
 141
 142 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
 143
 144 #ifdef CONFIG_BF533
 145 #define CPU "BF533"
 146 #define CPUID 0x027a5000
 147 #endif
 148 #ifdef CONFIG_BF532
 149 #define CPU "BF532"
 150 #define CPUID 0x0275A000
 151 #endif
 152 #ifdef CONFIG_BF531
 153 #define CPU "BF531"
 154 #define CPUID 0x027a5000
 155 #endif
 156 #ifndef CPU
 157 #define CPU "UNKNOWN"
 158 #define CPUID 0x0
 159 #endif
 160
 161 #if (CONFIG_MEM_SIZE % 4)
 162 #error "SDRAM mem size must be multible of 4MB"
 163 #endif
 164
 165 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
 166 #define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
 167 #define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 168 #define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
 169
 170 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
 171
 172 #define ANOMALY_05000158_WORKAROUND             0x200
 173 #ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
 174 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
 175                         | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 176 #else                           /*Write Through */
 177 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_DIRTY \
 178                         | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 179 #endif
 180
 181 #define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
 182 #define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
 183 #define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
 184 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
 185
 186 #define SIZE_1K 0x00000400      /* 1K */
 187 #define SIZE_4K 0x00001000      /* 4K */
 188 #define SIZE_1M 0x00100000      /* 1M */
 189 #define SIZE_4M 0x00400000      /* 4M */
 190
 191 #define MAX_CPLBS (16 * 2)
 192
 193 /*
 194 * Number of required data CPLB switchtable entries
 195 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 196 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
 197 * 1 for L1 Data Memory
 198 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 199 * 1 for ASYNC Memory
 200 */
 201
 202
 203 #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
 204
 205 /*
 206 * Number of required instruction CPLB switchtable entries
 207 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 208 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
 209 * 1 for L1 Instruction Memory
 210 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 211 */
 212
 213 #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
 214
 215 #endif                          /* __MACH_BF533_H__  */