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[ALSA] Add snd_pcm_group_for_each_entry() for code cleanup
[linux-2.6/linux-loongson.git] / sound / sparc / cs4231.c
blob96d51abcb73ac333b304f278c8d31334665164af
1 /*
2 * Driver for CS4231 sound chips found on Sparcs.
3 * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4 *
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
7 * and also sound/isa/cs423x/cs4231_lib.c which is:
8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/moduleparam.h>
18
19 #include <sound/driver.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/info.h>
23 #include <sound/control.h>
24 #include <sound/timer.h>
25 #include <sound/initval.h>
26 #include <sound/pcm_params.h>
27
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #ifdef CONFIG_SBUS
32 #define SBUS_SUPPORT
33 #endif
34
35 #ifdef SBUS_SUPPORT
36 #include <asm/sbus.h>
37 #endif
38
39 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
40 #define EBUS_SUPPORT
41 #endif
42
43 #ifdef EBUS_SUPPORT
44 #include <linux/pci.h>
45 #include <asm/ebus.h>
46 #endif
47
48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
51
52 module_param_array(index, int, NULL, 0444);
53 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
54 module_param_array(id, charp, NULL, 0444);
55 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
56 module_param_array(enable, bool, NULL, 0444);
57 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
58 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
59 MODULE_DESCRIPTION("Sun CS4231");
60 MODULE_LICENSE("GPL");
61 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
62
63 #ifdef SBUS_SUPPORT
64 struct sbus_dma_info {
65 spinlock_t lock;
66 int dir;
67 void __iomem *regs;
68 };
69 #endif
70
71 struct snd_cs4231;
72 struct cs4231_dma_control {
73 void (*prepare)(struct cs4231_dma_control *dma_cont, int dir);
74 void (*enable)(struct cs4231_dma_control *dma_cont, int on);
75 int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len);
76 unsigned int (*address)(struct cs4231_dma_control *dma_cont);
77 void (*reset)(struct snd_cs4231 *chip);
78 void (*preallocate)(struct snd_cs4231 *chip, struct snd_pcm *pcm);
79 #ifdef EBUS_SUPPORT
80 struct ebus_dma_info ebus_info;
81 #endif
82 #ifdef SBUS_SUPPORT
83 struct sbus_dma_info sbus_info;
84 #endif
85 };
86
87 struct snd_cs4231 {
88 spinlock_t lock;
89 void __iomem *port;
90
91 struct cs4231_dma_control p_dma;
92 struct cs4231_dma_control c_dma;
93
94 u32 flags;
95 #define CS4231_FLAG_EBUS 0x00000001
96 #define CS4231_FLAG_PLAYBACK 0x00000002
97 #define CS4231_FLAG_CAPTURE 0x00000004
98
99 struct snd_card *card;
100 struct snd_pcm *pcm;
101 struct snd_pcm_substream *playback_substream;
102 unsigned int p_periods_sent;
103 struct snd_pcm_substream *capture_substream;
104 unsigned int c_periods_sent;
105 struct snd_timer *timer;
106
107 unsigned short mode;
108 #define CS4231_MODE_NONE 0x0000
109 #define CS4231_MODE_PLAY 0x0001
110 #define CS4231_MODE_RECORD 0x0002
111 #define CS4231_MODE_TIMER 0x0004
112 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
113
114 unsigned char image[32]; /* registers image */
115 int mce_bit;
116 int calibrate_mute;
117 struct mutex mce_mutex;
118 struct mutex open_mutex;
119
120 union {
121 #ifdef SBUS_SUPPORT
122 struct sbus_dev *sdev;
123 #endif
124 #ifdef EBUS_SUPPORT
125 struct pci_dev *pdev;
126 #endif
127 } dev_u;
128 unsigned int irq[2];
129 unsigned int regs_size;
130 struct snd_cs4231 *next;
131 };
132
133 static struct snd_cs4231 *cs4231_list;
134
135 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
136 * now.... -DaveM
137 */
138
139 /* IO ports */
140
141 #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
142
143 /* XXX offsets are different than PC ISA chips... */
144 #define c_d_c_CS4231REGSEL 0x0
145 #define c_d_c_CS4231REG 0x4
146 #define c_d_c_CS4231STATUS 0x8
147 #define c_d_c_CS4231PIO 0xc
148
149 /* codec registers */
150
151 #define CS4231_LEFT_INPUT 0x00 /* left input control */
152 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
153 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
154 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
155 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
156 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
157 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
158 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
159 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
160 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
161 #define CS4231_PIN_CTRL 0x0a /* pin control */
162 #define CS4231_TEST_INIT 0x0b /* test and initialization */
163 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
164 #define CS4231_LOOPBACK 0x0d /* loopback control */
165 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
166 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
167 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
168 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
169 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
170 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
171 #define CS4231_TIMER_LOW 0x14 /* timer low byte */
172 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
173 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
174 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
175 #define CS4236_EXT_REG 0x17 /* extended register access */
176 #define CS4231_IRQ_STATUS 0x18 /* irq status register */
177 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
178 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
179 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
180 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
181 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
182 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
183 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
184 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
185 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
186 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
187
188 /* definitions for codec register select port - CODECP( REGSEL ) */
189
190 #define CS4231_INIT 0x80 /* CODEC is initializing */
191 #define CS4231_MCE 0x40 /* mode change enable */
192 #define CS4231_TRD 0x20 /* transfer request disable */
193
194 /* definitions for codec status register - CODECP( STATUS ) */
195
196 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
197
198 /* definitions for codec irq status - CS4231_IRQ_STATUS */
199
200 #define CS4231_PLAYBACK_IRQ 0x10
201 #define CS4231_RECORD_IRQ 0x20
202 #define CS4231_TIMER_IRQ 0x40
203 #define CS4231_ALL_IRQS 0x70
204 #define CS4231_REC_UNDERRUN 0x08
205 #define CS4231_REC_OVERRUN 0x04
206 #define CS4231_PLY_OVERRUN 0x02
207 #define CS4231_PLY_UNDERRUN 0x01
208
209 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
210
211 #define CS4231_ENABLE_MIC_GAIN 0x20
212
213 #define CS4231_MIXS_LINE 0x00
214 #define CS4231_MIXS_AUX1 0x40
215 #define CS4231_MIXS_MIC 0x80
216 #define CS4231_MIXS_ALL 0xc0
217
218 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
219
220 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
221 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
222 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
223 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
224 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
225 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
226 #define CS4231_STEREO 0x10 /* stereo mode */
227 /* bits 3-1 define frequency divisor */
228 #define CS4231_XTAL1 0x00 /* 24.576 crystal */
229 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
230
231 /* definitions for interface control register - CS4231_IFACE_CTRL */
232
233 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
234 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
235 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
236 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
237 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
238 #define CS4231_RECORD_ENABLE 0x02 /* record enable */
239 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
240
241 /* definitions for pin control register - CS4231_PIN_CTRL */
242
243 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
244 #define CS4231_XCTL1 0x40 /* external control #1 */
245 #define CS4231_XCTL0 0x80 /* external control #0 */
246
247 /* definitions for test and init register - CS4231_TEST_INIT */
248
249 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
250 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
251
252 /* definitions for misc control register - CS4231_MISC_INFO */
253
254 #define CS4231_MODE2 0x40 /* MODE 2 */
255 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
256 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
257
258 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
259
260 #define CS4231_DACZ 0x01 /* zero DAC when underrun */
261 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
262 #define CS4231_OLB 0x80 /* output level bit */
263
264 /* SBUS DMA register defines. */
265
266 #define APCCSR 0x10UL /* APC DMA CSR */
267 #define APCCVA 0x20UL /* APC Capture DMA Address */
268 #define APCCC 0x24UL /* APC Capture Count */
269 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
270 #define APCCNC 0x2cUL /* APC Capture Next Count */
271 #define APCPVA 0x30UL /* APC Play DMA Address */
272 #define APCPC 0x34UL /* APC Play Count */
273 #define APCPNVA 0x38UL /* APC Play DMA Next Address */
274 #define APCPNC 0x3cUL /* APC Play Next Count */
275
276 /* Defines for SBUS DMA-routines */
277
278 #define APCVA 0x0UL /* APC DMA Address */
279 #define APCC 0x4UL /* APC Count */
280 #define APCNVA 0x8UL /* APC DMA Next Address */
281 #define APCNC 0xcUL /* APC Next Count */
282 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
283 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
284
285 /* APCCSR bits */
286
287 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
288 #define APC_PLAY_INT 0x400000 /* Playback interrupt */
289 #define APC_CAPT_INT 0x200000 /* Capture interrupt */
290 #define APC_GENL_INT 0x100000 /* General interrupt */
291 #define APC_XINT_ENA 0x80000 /* General ext int. enable */
292 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
293 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
294 #define APC_XINT_GENL 0x10000 /* Error ext intr */
295 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
296 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
297 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
298 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
299 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
300 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
301 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
302 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
303 #define APC_PPAUSE 0x80 /* Pause the play DMA */
304 #define APC_CPAUSE 0x40 /* Pause the capture DMA */
305 #define APC_CDC_RESET 0x20 /* CODEC RESET */
306 #define APC_PDMA_READY 0x08 /* Play DMA Go */
307 #define APC_CDMA_READY 0x04 /* Capture DMA Go */
308 #define APC_CHIP_RESET 0x01 /* Reset the chip */
309
310 /* EBUS DMA register offsets */
311
312 #define EBDMA_CSR 0x00UL /* Control/Status */
313 #define EBDMA_ADDR 0x04UL /* DMA Address */
314 #define EBDMA_COUNT 0x08UL /* DMA Count */
315
316 /*
317 * Some variables
318 */
319
320 static unsigned char freq_bits[14] = {
321 /* 5510 */ 0x00 | CS4231_XTAL2,
322 /* 6620 */ 0x0E | CS4231_XTAL2,
323 /* 8000 */ 0x00 | CS4231_XTAL1,
324 /* 9600 */ 0x0E | CS4231_XTAL1,
325 /* 11025 */ 0x02 | CS4231_XTAL2,
326 /* 16000 */ 0x02 | CS4231_XTAL1,
327 /* 18900 */ 0x04 | CS4231_XTAL2,
328 /* 22050 */ 0x06 | CS4231_XTAL2,
329 /* 27042 */ 0x04 | CS4231_XTAL1,
330 /* 32000 */ 0x06 | CS4231_XTAL1,
331 /* 33075 */ 0x0C | CS4231_XTAL2,
332 /* 37800 */ 0x08 | CS4231_XTAL2,
333 /* 44100 */ 0x0A | CS4231_XTAL2,
334 /* 48000 */ 0x0C | CS4231_XTAL1
335 };
336
337 static unsigned int rates[14] = {
338 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
339 27042, 32000, 33075, 37800, 44100, 48000
340 };
341
342 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
343 .count = 14,
344 .list = rates,
345 };
346
347 static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
348 {
349 return snd_pcm_hw_constraint_list(runtime, 0,
350 SNDRV_PCM_HW_PARAM_RATE,
351 &hw_constraints_rates);
352 }
353
354 static unsigned char snd_cs4231_original_image[32] =
355 {
356 0x00, /* 00/00 - lic */
357 0x00, /* 01/01 - ric */
358 0x9f, /* 02/02 - la1ic */
359 0x9f, /* 03/03 - ra1ic */
360 0x9f, /* 04/04 - la2ic */
361 0x9f, /* 05/05 - ra2ic */
362 0xbf, /* 06/06 - loc */
363 0xbf, /* 07/07 - roc */
364 0x20, /* 08/08 - pdfr */
365 CS4231_AUTOCALIB, /* 09/09 - ic */
366 0x00, /* 0a/10 - pc */
367 0x00, /* 0b/11 - ti */
368 CS4231_MODE2, /* 0c/12 - mi */
369 0x00, /* 0d/13 - lbc */
370 0x00, /* 0e/14 - pbru */
371 0x00, /* 0f/15 - pbrl */
372 0x80, /* 10/16 - afei */
373 0x01, /* 11/17 - afeii */
374 0x9f, /* 12/18 - llic */
375 0x9f, /* 13/19 - rlic */
376 0x00, /* 14/20 - tlb */
377 0x00, /* 15/21 - thb */
378 0x00, /* 16/22 - la3mic/reserved */
379 0x00, /* 17/23 - ra3mic/reserved */
380 0x00, /* 18/24 - afs */
381 0x00, /* 19/25 - lamoc/version */
382 0x00, /* 1a/26 - mioc */
383 0x00, /* 1b/27 - ramoc/reserved */
384 0x20, /* 1c/28 - cdfr */
385 0x00, /* 1d/29 - res4 */
386 0x00, /* 1e/30 - cbru */
387 0x00, /* 1f/31 - cbrl */
388 };
389
390 static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
391 {
392 #ifdef EBUS_SUPPORT
393 if (cp->flags & CS4231_FLAG_EBUS) {
394 return readb(reg_addr);
395 } else {
396 #endif
397 #ifdef SBUS_SUPPORT
398 return sbus_readb(reg_addr);
399 #endif
400 #ifdef EBUS_SUPPORT
401 }
402 #endif
403 }
404
405 static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, void __iomem *reg_addr)
406 {
407 #ifdef EBUS_SUPPORT
408 if (cp->flags & CS4231_FLAG_EBUS) {
409 return writeb(val, reg_addr);
410 } else {
411 #endif
412 #ifdef SBUS_SUPPORT
413 return sbus_writeb(val, reg_addr);
414 #endif
415 #ifdef EBUS_SUPPORT
416 }
417 #endif
418 }
419
420 /*
421 * Basic I/O functions
422 */
423
424 static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
425 unsigned char mask, unsigned char value)
426 {
427 int timeout;
428 unsigned char tmp;
429
430 for (timeout = 250;
431 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
432 timeout--)
433 udelay(100);
434 #ifdef CONFIG_SND_DEBUG
435 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
436 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
437 #endif
438 if (chip->calibrate_mute) {
439 chip->image[reg] &= mask;
440 chip->image[reg] |= value;
441 } else {
442 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
443 mb();
444 tmp = (chip->image[reg] & mask) | value;
445 __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
446 chip->image[reg] = tmp;
447 mb();
448 }
449 }
450
451 static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
452 {
453 int timeout;
454
455 for (timeout = 250;
456 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
457 timeout--)
458 udelay(100);
459 #ifdef CONFIG_SND_DEBUG
460 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
461 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
462 #endif
463 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
464 __cs4231_writeb(chip, value, CS4231P(chip, REG));
465 mb();
466 }
467
468 static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
469 {
470 int timeout;
471
472 for (timeout = 250;
473 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
474 timeout--)
475 udelay(100);
476 #ifdef CONFIG_SND_DEBUG
477 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
478 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
479 #endif
480 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
481 __cs4231_writeb(chip, value, CS4231P(chip, REG));
482 chip->image[reg] = value;
483 mb();
484 }
485
486 static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
487 {
488 int timeout;
489 unsigned char ret;
490
491 for (timeout = 250;
492 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
493 timeout--)
494 udelay(100);
495 #ifdef CONFIG_SND_DEBUG
496 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
497 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg);
498 #endif
499 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
500 mb();
501 ret = __cs4231_readb(chip, CS4231P(chip, REG));
502 return ret;
503 }
504
505 /*
506 * CS4231 detection / MCE routines
507 */
508
509 static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
510 {
511 int timeout;
512
513 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
514 for (timeout = 5; timeout > 0; timeout--)
515 __cs4231_readb(chip, CS4231P(chip, REGSEL));
516
517 /* end of cleanup sequence */
518 for (timeout = 500;
519 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
520 timeout--)
521 udelay(1000);
522 }
523
524 static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
525 {
526 unsigned long flags;
527 int timeout;
528
529 spin_lock_irqsave(&chip->lock, flags);
530 for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
531 udelay(100);
532 #ifdef CONFIG_SND_DEBUG
533 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
534 snd_printdd("mce_up - auto calibration time out (0)\n");
535 #endif
536 chip->mce_bit |= CS4231_MCE;
537 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
538 if (timeout == 0x80)
539 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
540 if (!(timeout & CS4231_MCE))
541 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
542 spin_unlock_irqrestore(&chip->lock, flags);
543 }
544
545 static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
546 {
547 unsigned long flags;
548 int timeout;
549
550 spin_lock_irqsave(&chip->lock, flags);
551 snd_cs4231_busy_wait(chip);
552 #ifdef CONFIG_SND_DEBUG
553 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
554 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
555 #endif
556 chip->mce_bit &= ~CS4231_MCE;
557 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
558 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
559 if (timeout == 0x80)
560 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
561 if ((timeout & CS4231_MCE) == 0) {
562 spin_unlock_irqrestore(&chip->lock, flags);
563 return;
564 }
565 snd_cs4231_busy_wait(chip);
566
567 /* calibration process */
568
569 for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
570 udelay(100);
571 if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
572 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
573 spin_unlock_irqrestore(&chip->lock, flags);
574 return;
575 }
576
577 /* in 10ms increments, check condition, up to 250ms */
578 timeout = 25;
579 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
580 spin_unlock_irqrestore(&chip->lock, flags);
581 if (--timeout < 0) {
582 snd_printk("mce_down - auto calibration time out (2)\n");
583 return;
584 }
585 msleep(10);
586 spin_lock_irqsave(&chip->lock, flags);
587 }
588
589 /* in 10ms increments, check condition, up to 100ms */
590 timeout = 10;
591 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
592 spin_unlock_irqrestore(&chip->lock, flags);
593 if (--timeout < 0) {
594 snd_printk("mce_down - auto calibration time out (3)\n");
595 return;
596 }
597 msleep(10);
598 spin_lock_irqsave(&chip->lock, flags);
599 }
600 spin_unlock_irqrestore(&chip->lock, flags);
601 }
602
603 static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
604 struct snd_pcm_substream *substream,
605 unsigned int *periods_sent)
606 {
607 struct snd_pcm_runtime *runtime = substream->runtime;
608
609 while (1) {
610 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
611 unsigned int offset = period_size * (*periods_sent);
612
613 BUG_ON(period_size >= (1 << 24));
614
615 if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size))
616 return;
617 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
618 }
619 }
620
621 static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
622 unsigned int what, int on)
623 {
624 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
625 struct cs4231_dma_control *dma_cont;
626
627 if (what & CS4231_PLAYBACK_ENABLE) {
628 dma_cont = &chip->p_dma;
629 if (on) {
630 dma_cont->prepare(dma_cont, 0);
631 dma_cont->enable(dma_cont, 1);
632 snd_cs4231_advance_dma(dma_cont,
633 chip->playback_substream,
634 &chip->p_periods_sent);
635 } else {
636 dma_cont->enable(dma_cont, 0);
637 }
638 }
639 if (what & CS4231_RECORD_ENABLE) {
640 dma_cont = &chip->c_dma;
641 if (on) {
642 dma_cont->prepare(dma_cont, 1);
643 dma_cont->enable(dma_cont, 1);
644 snd_cs4231_advance_dma(dma_cont,
645 chip->capture_substream,
646 &chip->c_periods_sent);
647 } else {
648 dma_cont->enable(dma_cont, 0);
649 }
650 }
651 }
652
653 static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
654 {
655 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
656 int result = 0;
657
658 switch (cmd) {
659 case SNDRV_PCM_TRIGGER_START:
660 case SNDRV_PCM_TRIGGER_STOP:
661 {
662 unsigned int what = 0;
663 struct snd_pcm_substream *s;
664 unsigned long flags;
665
666 snd_pcm_group_for_each_entry(s, substream) {
667 s = snd_pcm_group_substream_entry(pos);
668 if (s == chip->playback_substream) {
669 what |= CS4231_PLAYBACK_ENABLE;
670 snd_pcm_trigger_done(s, substream);
671 } else if (s == chip->capture_substream) {
672 what |= CS4231_RECORD_ENABLE;
673 snd_pcm_trigger_done(s, substream);
674 }
675 }
676
677 spin_lock_irqsave(&chip->lock, flags);
678 if (cmd == SNDRV_PCM_TRIGGER_START) {
679 cs4231_dma_trigger(substream, what, 1);
680 chip->image[CS4231_IFACE_CTRL] |= what;
681 } else {
682 cs4231_dma_trigger(substream, what, 0);
683 chip->image[CS4231_IFACE_CTRL] &= ~what;
684 }
685 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
686 chip->image[CS4231_IFACE_CTRL]);
687 spin_unlock_irqrestore(&chip->lock, flags);
688 break;
689 }
690 default:
691 result = -EINVAL;
692 break;
693 }
694
695 return result;
696 }
697
698 /*
699 * CODEC I/O
700 */
701
702 static unsigned char snd_cs4231_get_rate(unsigned int rate)
703 {
704 int i;
705
706 for (i = 0; i < 14; i++)
707 if (rate == rates[i])
708 return freq_bits[i];
709 // snd_BUG();
710 return freq_bits[13];
711 }
712
713 static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, int channels)
714 {
715 unsigned char rformat;
716
717 rformat = CS4231_LINEAR_8;
718 switch (format) {
719 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
720 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
721 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
722 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
723 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
724 }
725 if (channels > 1)
726 rformat |= CS4231_STEREO;
727 return rformat;
728 }
729
730 static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
731 {
732 unsigned long flags;
733
734 mute = mute ? 1 : 0;
735 spin_lock_irqsave(&chip->lock, flags);
736 if (chip->calibrate_mute == mute) {
737 spin_unlock_irqrestore(&chip->lock, flags);
738 return;
739 }
740 if (!mute) {
741 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
742 chip->image[CS4231_LEFT_INPUT]);
743 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
744 chip->image[CS4231_RIGHT_INPUT]);
745 snd_cs4231_dout(chip, CS4231_LOOPBACK,
746 chip->image[CS4231_LOOPBACK]);
747 }
748 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
749 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
750 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
751 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
752 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
753 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
754 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
755 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
756 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
757 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
758 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
759 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
760 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
761 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
762 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
763 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
764 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
765 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
766 chip->calibrate_mute = mute;
767 spin_unlock_irqrestore(&chip->lock, flags);
768 }
769
770 static void snd_cs4231_playback_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
771 unsigned char pdfr)
772 {
773 unsigned long flags;
774
775 mutex_lock(&chip->mce_mutex);
776 snd_cs4231_calibrate_mute(chip, 1);
777
778 snd_cs4231_mce_up(chip);
779
780 spin_lock_irqsave(&chip->lock, flags);
781 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
782 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
783 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
784 pdfr);
785 spin_unlock_irqrestore(&chip->lock, flags);
786
787 snd_cs4231_mce_down(chip);
788
789 snd_cs4231_calibrate_mute(chip, 0);
790 mutex_unlock(&chip->mce_mutex);
791 }
792
793 static void snd_cs4231_capture_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
794 unsigned char cdfr)
795 {
796 unsigned long flags;
797
798 mutex_lock(&chip->mce_mutex);
799 snd_cs4231_calibrate_mute(chip, 1);
800
801 snd_cs4231_mce_up(chip);
802
803 spin_lock_irqsave(&chip->lock, flags);
804 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
805 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
806 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
807 (cdfr & 0x0f));
808 spin_unlock_irqrestore(&chip->lock, flags);
809 snd_cs4231_mce_down(chip);
810 snd_cs4231_mce_up(chip);
811 spin_lock_irqsave(&chip->lock, flags);
812 }
813 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
814 spin_unlock_irqrestore(&chip->lock, flags);
815
816 snd_cs4231_mce_down(chip);
817
818 snd_cs4231_calibrate_mute(chip, 0);
819 mutex_unlock(&chip->mce_mutex);
820 }
821
822 /*
823 * Timer interface
824 */
825
826 static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
827 {
828 struct snd_cs4231 *chip = snd_timer_chip(timer);
829
830 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
831 }
832
833 static int snd_cs4231_timer_start(struct snd_timer *timer)
834 {
835 unsigned long flags;
836 unsigned int ticks;
837 struct snd_cs4231 *chip = snd_timer_chip(timer);
838
839 spin_lock_irqsave(&chip->lock, flags);
840 ticks = timer->sticks;
841 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
842 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
843 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
844 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
845 chip->image[CS4231_TIMER_HIGH] =
846 (unsigned char) (ticks >> 8));
847 snd_cs4231_out(chip, CS4231_TIMER_LOW,
848 chip->image[CS4231_TIMER_LOW] =
849 (unsigned char) ticks);
850 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
851 chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
852 }
853 spin_unlock_irqrestore(&chip->lock, flags);
854
855 return 0;
856 }
857
858 static int snd_cs4231_timer_stop(struct snd_timer *timer)
859 {
860 unsigned long flags;
861 struct snd_cs4231 *chip = snd_timer_chip(timer);
862
863 spin_lock_irqsave(&chip->lock, flags);
864 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
865 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
866 spin_unlock_irqrestore(&chip->lock, flags);
867
868 return 0;
869 }
870
871 static void __init snd_cs4231_init(struct snd_cs4231 *chip)
872 {
873 unsigned long flags;
874
875 snd_cs4231_mce_down(chip);
876
877 #ifdef SNDRV_DEBUG_MCE
878 snd_printdd("init: (1)\n");
879 #endif
880 snd_cs4231_mce_up(chip);
881 spin_lock_irqsave(&chip->lock, flags);
882 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
883 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
884 CS4231_CALIB_MODE);
885 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
886 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
887 spin_unlock_irqrestore(&chip->lock, flags);
888 snd_cs4231_mce_down(chip);
889
890 #ifdef SNDRV_DEBUG_MCE
891 snd_printdd("init: (2)\n");
892 #endif
893
894 snd_cs4231_mce_up(chip);
895 spin_lock_irqsave(&chip->lock, flags);
896 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
897 spin_unlock_irqrestore(&chip->lock, flags);
898 snd_cs4231_mce_down(chip);
899
900 #ifdef SNDRV_DEBUG_MCE
901 snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
902 #endif
903
904 spin_lock_irqsave(&chip->lock, flags);
905 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
906 spin_unlock_irqrestore(&chip->lock, flags);
907
908 snd_cs4231_mce_up(chip);
909 spin_lock_irqsave(&chip->lock, flags);
910 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
911 spin_unlock_irqrestore(&chip->lock, flags);
912 snd_cs4231_mce_down(chip);
913
914 #ifdef SNDRV_DEBUG_MCE
915 snd_printdd("init: (4)\n");
916 #endif
917
918 snd_cs4231_mce_up(chip);
919 spin_lock_irqsave(&chip->lock, flags);
920 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
921 spin_unlock_irqrestore(&chip->lock, flags);
922 snd_cs4231_mce_down(chip);
923
924 #ifdef SNDRV_DEBUG_MCE
925 snd_printdd("init: (5)\n");
926 #endif
927 }
928
929 static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
930 {
931 unsigned long flags;
932
933 mutex_lock(&chip->open_mutex);
934 if ((chip->mode & mode)) {
935 mutex_unlock(&chip->open_mutex);
936 return -EAGAIN;
937 }
938 if (chip->mode & CS4231_MODE_OPEN) {
939 chip->mode |= mode;
940 mutex_unlock(&chip->open_mutex);
941 return 0;
942 }
943 /* ok. now enable and ack CODEC IRQ */
944 spin_lock_irqsave(&chip->lock, flags);
945 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
946 CS4231_RECORD_IRQ |
947 CS4231_TIMER_IRQ);
948 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
949 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
950 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
951
952 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
953 CS4231_RECORD_IRQ |
954 CS4231_TIMER_IRQ);
955 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
956
957 spin_unlock_irqrestore(&chip->lock, flags);
958
959 chip->mode = mode;
960 mutex_unlock(&chip->open_mutex);
961 return 0;
962 }
963
964 static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
965 {
966 unsigned long flags;
967
968 mutex_lock(&chip->open_mutex);
969 chip->mode &= ~mode;
970 if (chip->mode & CS4231_MODE_OPEN) {
971 mutex_unlock(&chip->open_mutex);
972 return;
973 }
974 snd_cs4231_calibrate_mute(chip, 1);
975
976 /* disable IRQ */
977 spin_lock_irqsave(&chip->lock, flags);
978 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
979 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
980 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
981
982 /* now disable record & playback */
983
984 if (chip->image[CS4231_IFACE_CTRL] &
985 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
986 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
987 spin_unlock_irqrestore(&chip->lock, flags);
988 snd_cs4231_mce_up(chip);
989 spin_lock_irqsave(&chip->lock, flags);
990 chip->image[CS4231_IFACE_CTRL] &=
991 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
992 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
993 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
994 spin_unlock_irqrestore(&chip->lock, flags);
995 snd_cs4231_mce_down(chip);
996 spin_lock_irqsave(&chip->lock, flags);
997 }
998
999 /* clear IRQ again */
1000 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1001 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1002 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1003 spin_unlock_irqrestore(&chip->lock, flags);
1004
1005 snd_cs4231_calibrate_mute(chip, 0);
1006
1007 chip->mode = 0;
1008 mutex_unlock(&chip->open_mutex);
1009 }
1010
1011 /*
1012 * timer open/close
1013 */
1014
1015 static int snd_cs4231_timer_open(struct snd_timer *timer)
1016 {
1017 struct snd_cs4231 *chip = snd_timer_chip(timer);
1018 snd_cs4231_open(chip, CS4231_MODE_TIMER);
1019 return 0;
1020 }
1021
1022 static int snd_cs4231_timer_close(struct snd_timer * timer)
1023 {
1024 struct snd_cs4231 *chip = snd_timer_chip(timer);
1025 snd_cs4231_close(chip, CS4231_MODE_TIMER);
1026 return 0;
1027 }
1028
1029 static struct snd_timer_hardware snd_cs4231_timer_table =
1030 {
1031 .flags = SNDRV_TIMER_HW_AUTO,
1032 .resolution = 9945,
1033 .ticks = 65535,
1034 .open = snd_cs4231_timer_open,
1035 .close = snd_cs4231_timer_close,
1036 .c_resolution = snd_cs4231_timer_resolution,
1037 .start = snd_cs4231_timer_start,
1038 .stop = snd_cs4231_timer_stop,
1039 };
1040
1041 /*
1042 * ok.. exported functions..
1043 */
1044
1045 static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
1046 struct snd_pcm_hw_params *hw_params)
1047 {
1048 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1049 unsigned char new_pdfr;
1050 int err;
1051
1052 if ((err = snd_pcm_lib_malloc_pages(substream,
1053 params_buffer_bytes(hw_params))) < 0)
1054 return err;
1055 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1056 params_channels(hw_params)) |
1057 snd_cs4231_get_rate(params_rate(hw_params));
1058 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1059
1060 return 0;
1061 }
1062
1063 static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
1064 {
1065 return snd_pcm_lib_free_pages(substream);
1066 }
1067
1068 static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1069 {
1070 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1071 struct snd_pcm_runtime *runtime = substream->runtime;
1072 unsigned long flags;
1073
1074 spin_lock_irqsave(&chip->lock, flags);
1075
1076 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1077 CS4231_PLAYBACK_PIO);
1078
1079 BUG_ON(runtime->period_size > 0xffff + 1);
1080
1081 chip->p_periods_sent = 0;
1082 spin_unlock_irqrestore(&chip->lock, flags);
1083
1084 return 0;
1085 }
1086
1087 static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
1088 struct snd_pcm_hw_params *hw_params)
1089 {
1090 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1091 unsigned char new_cdfr;
1092 int err;
1093
1094 if ((err = snd_pcm_lib_malloc_pages(substream,
1095 params_buffer_bytes(hw_params))) < 0)
1096 return err;
1097 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1098 params_channels(hw_params)) |
1099 snd_cs4231_get_rate(params_rate(hw_params));
1100 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1101
1102 return 0;
1103 }
1104
1105 static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
1106 {
1107 return snd_pcm_lib_free_pages(substream);
1108 }
1109
1110 static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1111 {
1112 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1113 unsigned long flags;
1114
1115 spin_lock_irqsave(&chip->lock, flags);
1116 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1117 CS4231_RECORD_PIO);
1118
1119
1120 chip->c_periods_sent = 0;
1121 spin_unlock_irqrestore(&chip->lock, flags);
1122
1123 return 0;
1124 }
1125
1126 static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1127 {
1128 unsigned long flags;
1129 unsigned char res;
1130
1131 spin_lock_irqsave(&chip->lock, flags);
1132 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1133 spin_unlock_irqrestore(&chip->lock, flags);
1134
1135 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1136 chip->capture_substream->runtime->overrange++;
1137 }
1138
1139 static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
1140 {
1141 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1142 snd_pcm_period_elapsed(chip->playback_substream);
1143 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1144 &chip->p_periods_sent);
1145 }
1146 }
1147
1148 static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
1149 {
1150 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1151 snd_pcm_period_elapsed(chip->capture_substream);
1152 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1153 &chip->c_periods_sent);
1154 }
1155 }
1156
1157 static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
1158 {
1159 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1160 struct cs4231_dma_control *dma_cont = &chip->p_dma;
1161 size_t ptr;
1162
1163 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1164 return 0;
1165 ptr = dma_cont->address(dma_cont);
1166 if (ptr != 0)
1167 ptr -= substream->runtime->dma_addr;
1168
1169 return bytes_to_frames(substream->runtime, ptr);
1170 }
1171
1172 static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
1173 {
1174 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1175 struct cs4231_dma_control *dma_cont = &chip->c_dma;
1176 size_t ptr;
1177
1178 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1179 return 0;
1180 ptr = dma_cont->address(dma_cont);
1181 if (ptr != 0)
1182 ptr -= substream->runtime->dma_addr;
1183
1184 return bytes_to_frames(substream->runtime, ptr);
1185 }
1186
1187 /*
1188
1189 */
1190
1191 static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
1192 {
1193 unsigned long flags;
1194 int i, id, vers;
1195 unsigned char *ptr;
1196
1197 id = vers = 0;
1198 for (i = 0; i < 50; i++) {
1199 mb();
1200 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
1201 udelay(2000);
1202 else {
1203 spin_lock_irqsave(&chip->lock, flags);
1204 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1205 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1206 vers = snd_cs4231_in(chip, CS4231_VERSION);
1207 spin_unlock_irqrestore(&chip->lock, flags);
1208 if (id == 0x0a)
1209 break; /* this is valid value */
1210 }
1211 }
1212 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1213 if (id != 0x0a)
1214 return -ENODEV; /* no valid device found */
1215
1216 spin_lock_irqsave(&chip->lock, flags);
1217
1218
1219 /* Reset DMA engine (sbus only). */
1220 chip->p_dma.reset(chip);
1221
1222 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
1223 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1224 mb();
1225
1226 spin_unlock_irqrestore(&chip->lock, flags);
1227
1228 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1229 chip->image[CS4231_IFACE_CTRL] =
1230 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1231 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1232 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1233 if (vers & 0x20)
1234 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1235
1236 ptr = (unsigned char *) &chip->image;
1237
1238 snd_cs4231_mce_down(chip);
1239
1240 spin_lock_irqsave(&chip->lock, flags);
1241
1242 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1243 snd_cs4231_out(chip, i, *ptr++);
1244
1245 spin_unlock_irqrestore(&chip->lock, flags);
1246
1247 snd_cs4231_mce_up(chip);
1248
1249 snd_cs4231_mce_down(chip);
1250
1251 mdelay(2);
1252
1253 return 0; /* all things are ok.. */
1254 }
1255
1256 static struct snd_pcm_hardware snd_cs4231_playback =
1257 {
1258 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1259 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1260 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1261 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1262 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1263 SNDRV_PCM_FMTBIT_S16_BE),
1264 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1265 .rate_min = 5510,
1266 .rate_max = 48000,
1267 .channels_min = 1,
1268 .channels_max = 2,
1269 .buffer_bytes_max = (32*1024),
1270 .period_bytes_min = 64,
1271 .period_bytes_max = (32*1024),
1272 .periods_min = 1,
1273 .periods_max = 1024,
1274 };
1275
1276 static struct snd_pcm_hardware snd_cs4231_capture =
1277 {
1278 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1279 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1280 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1281 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1282 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1283 SNDRV_PCM_FMTBIT_S16_BE),
1284 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1285 .rate_min = 5510,
1286 .rate_max = 48000,
1287 .channels_min = 1,
1288 .channels_max = 2,
1289 .buffer_bytes_max = (32*1024),
1290 .period_bytes_min = 64,
1291 .period_bytes_max = (32*1024),
1292 .periods_min = 1,
1293 .periods_max = 1024,
1294 };
1295
1296 static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1297 {
1298 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1299 struct snd_pcm_runtime *runtime = substream->runtime;
1300 int err;
1301
1302 runtime->hw = snd_cs4231_playback;
1303
1304 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1305 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1306 return err;
1307 }
1308 chip->playback_substream = substream;
1309 chip->p_periods_sent = 0;
1310 snd_pcm_set_sync(substream);
1311 snd_cs4231_xrate(runtime);
1312
1313 return 0;
1314 }
1315
1316 static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1317 {
1318 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1319 struct snd_pcm_runtime *runtime = substream->runtime;
1320 int err;
1321
1322 runtime->hw = snd_cs4231_capture;
1323
1324 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1325 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1326 return err;
1327 }
1328 chip->capture_substream = substream;
1329 chip->c_periods_sent = 0;
1330 snd_pcm_set_sync(substream);
1331 snd_cs4231_xrate(runtime);
1332
1333 return 0;
1334 }
1335
1336 static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1337 {
1338 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1339
1340 snd_cs4231_close(chip, CS4231_MODE_PLAY);
1341 chip->playback_substream = NULL;
1342
1343 return 0;
1344 }
1345
1346 static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1347 {
1348 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1349
1350 snd_cs4231_close(chip, CS4231_MODE_RECORD);
1351 chip->capture_substream = NULL;
1352
1353 return 0;
1354 }
1355
1356 /* XXX We can do some power-management, in particular on EBUS using
1357 * XXX the audio AUXIO register...
1358 */
1359
1360 static struct snd_pcm_ops snd_cs4231_playback_ops = {
1361 .open = snd_cs4231_playback_open,
1362 .close = snd_cs4231_playback_close,
1363 .ioctl = snd_pcm_lib_ioctl,
1364 .hw_params = snd_cs4231_playback_hw_params,
1365 .hw_free = snd_cs4231_playback_hw_free,
1366 .prepare = snd_cs4231_playback_prepare,
1367 .trigger = snd_cs4231_trigger,
1368 .pointer = snd_cs4231_playback_pointer,
1369 };
1370
1371 static struct snd_pcm_ops snd_cs4231_capture_ops = {
1372 .open = snd_cs4231_capture_open,
1373 .close = snd_cs4231_capture_close,
1374 .ioctl = snd_pcm_lib_ioctl,
1375 .hw_params = snd_cs4231_capture_hw_params,
1376 .hw_free = snd_cs4231_capture_hw_free,
1377 .prepare = snd_cs4231_capture_prepare,
1378 .trigger = snd_cs4231_trigger,
1379 .pointer = snd_cs4231_capture_pointer,
1380 };
1381
1382 static int __init snd_cs4231_pcm(struct snd_cs4231 *chip)
1383 {
1384 struct snd_pcm *pcm;
1385 int err;
1386
1387 if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
1388 return err;
1389
1390 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1391 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1392
1393 /* global setup */
1394 pcm->private_data = chip;
1395 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1396 strcpy(pcm->name, "CS4231");
1397
1398 chip->p_dma.preallocate(chip, pcm);
1399
1400 chip->pcm = pcm;
1401
1402 return 0;
1403 }
1404
1405 static int __init snd_cs4231_timer(struct snd_cs4231 *chip)
1406 {
1407 struct snd_timer *timer;
1408 struct snd_timer_id tid;
1409 int err;
1410
1411 /* Timer initialization */
1412 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1413 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1414 tid.card = chip->card->number;
1415 tid.device = 0;
1416 tid.subdevice = 0;
1417 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1418 return err;
1419 strcpy(timer->name, "CS4231");
1420 timer->private_data = chip;
1421 timer->hw = snd_cs4231_timer_table;
1422 chip->timer = timer;
1423
1424 return 0;
1425 }
1426
1427 /*
1428 * MIXER part
1429 */
1430
1431 static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
1432 struct snd_ctl_elem_info *uinfo)
1433 {
1434 static char *texts[4] = {
1435 "Line", "CD", "Mic", "Mix"
1436 };
1437 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1438
1439 snd_assert(chip->card != NULL, return -EINVAL);
1440 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1441 uinfo->count = 2;
1442 uinfo->value.enumerated.items = 4;
1443 if (uinfo->value.enumerated.item > 3)
1444 uinfo->value.enumerated.item = 3;
1445 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1446
1447 return 0;
1448 }
1449
1450 static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
1451 struct snd_ctl_elem_value *ucontrol)
1452 {
1453 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1454 unsigned long flags;
1455
1456 spin_lock_irqsave(&chip->lock, flags);
1457 ucontrol->value.enumerated.item[0] =
1458 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1459 ucontrol->value.enumerated.item[1] =
1460 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1461 spin_unlock_irqrestore(&chip->lock, flags);
1462
1463 return 0;
1464 }
1465
1466 static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
1467 struct snd_ctl_elem_value *ucontrol)
1468 {
1469 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1470 unsigned long flags;
1471 unsigned short left, right;
1472 int change;
1473
1474 if (ucontrol->value.enumerated.item[0] > 3 ||
1475 ucontrol->value.enumerated.item[1] > 3)
1476 return -EINVAL;
1477 left = ucontrol->value.enumerated.item[0] << 6;
1478 right = ucontrol->value.enumerated.item[1] << 6;
1479
1480 spin_lock_irqsave(&chip->lock, flags);
1481
1482 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1483 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1484 change = left != chip->image[CS4231_LEFT_INPUT] ||
1485 right != chip->image[CS4231_RIGHT_INPUT];
1486 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1487 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1488
1489 spin_unlock_irqrestore(&chip->lock, flags);
1490
1491 return change;
1492 }
1493
1494 static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
1495 struct snd_ctl_elem_info *uinfo)
1496 {
1497 int mask = (kcontrol->private_value >> 16) & 0xff;
1498
1499 uinfo->type = (mask == 1) ?
1500 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1501 uinfo->count = 1;
1502 uinfo->value.integer.min = 0;
1503 uinfo->value.integer.max = mask;
1504
1505 return 0;
1506 }
1507
1508 static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
1509 struct snd_ctl_elem_value *ucontrol)
1510 {
1511 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1512 unsigned long flags;
1513 int reg = kcontrol->private_value & 0xff;
1514 int shift = (kcontrol->private_value >> 8) & 0xff;
1515 int mask = (kcontrol->private_value >> 16) & 0xff;
1516 int invert = (kcontrol->private_value >> 24) & 0xff;
1517
1518 spin_lock_irqsave(&chip->lock, flags);
1519
1520 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1521
1522 spin_unlock_irqrestore(&chip->lock, flags);
1523
1524 if (invert)
1525 ucontrol->value.integer.value[0] =
1526 (mask - ucontrol->value.integer.value[0]);
1527
1528 return 0;
1529 }
1530
1531 static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
1532 struct snd_ctl_elem_value *ucontrol)
1533 {
1534 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1535 unsigned long flags;
1536 int reg = kcontrol->private_value & 0xff;
1537 int shift = (kcontrol->private_value >> 8) & 0xff;
1538 int mask = (kcontrol->private_value >> 16) & 0xff;
1539 int invert = (kcontrol->private_value >> 24) & 0xff;
1540 int change;
1541 unsigned short val;
1542
1543 val = (ucontrol->value.integer.value[0] & mask);
1544 if (invert)
1545 val = mask - val;
1546 val <<= shift;
1547
1548 spin_lock_irqsave(&chip->lock, flags);
1549
1550 val = (chip->image[reg] & ~(mask << shift)) | val;
1551 change = val != chip->image[reg];
1552 snd_cs4231_out(chip, reg, val);
1553
1554 spin_unlock_irqrestore(&chip->lock, flags);
1555
1556 return change;
1557 }
1558
1559 static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
1560 struct snd_ctl_elem_info *uinfo)
1561 {
1562 int mask = (kcontrol->private_value >> 24) & 0xff;
1563
1564 uinfo->type = mask == 1 ?
1565 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1566 uinfo->count = 2;
1567 uinfo->value.integer.min = 0;
1568 uinfo->value.integer.max = mask;
1569
1570 return 0;
1571 }
1572
1573 static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
1574 struct snd_ctl_elem_value *ucontrol)
1575 {
1576 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1577 unsigned long flags;
1578 int left_reg = kcontrol->private_value & 0xff;
1579 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1580 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1581 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1582 int mask = (kcontrol->private_value >> 24) & 0xff;
1583 int invert = (kcontrol->private_value >> 22) & 1;
1584
1585 spin_lock_irqsave(&chip->lock, flags);
1586
1587 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1588 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1589
1590 spin_unlock_irqrestore(&chip->lock, flags);
1591
1592 if (invert) {
1593 ucontrol->value.integer.value[0] =
1594 (mask - ucontrol->value.integer.value[0]);
1595 ucontrol->value.integer.value[1] =
1596 (mask - ucontrol->value.integer.value[1]);
1597 }
1598
1599 return 0;
1600 }
1601
1602 static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
1603 struct snd_ctl_elem_value *ucontrol)
1604 {
1605 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1606 unsigned long flags;
1607 int left_reg = kcontrol->private_value & 0xff;
1608 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1609 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1610 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1611 int mask = (kcontrol->private_value >> 24) & 0xff;
1612 int invert = (kcontrol->private_value >> 22) & 1;
1613 int change;
1614 unsigned short val1, val2;
1615
1616 val1 = ucontrol->value.integer.value[0] & mask;
1617 val2 = ucontrol->value.integer.value[1] & mask;
1618 if (invert) {
1619 val1 = mask - val1;
1620 val2 = mask - val2;
1621 }
1622 val1 <<= shift_left;
1623 val2 <<= shift_right;
1624
1625 spin_lock_irqsave(&chip->lock, flags);
1626
1627 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1628 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1629 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1630 snd_cs4231_out(chip, left_reg, val1);
1631 snd_cs4231_out(chip, right_reg, val2);
1632
1633 spin_unlock_irqrestore(&chip->lock, flags);
1634
1635 return change;
1636 }
1637
1638 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1639 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1640 .info = snd_cs4231_info_single, \
1641 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1642 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1643
1644 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1645 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1646 .info = snd_cs4231_info_double, \
1647 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1648 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1649
1650 static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = {
1651 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1652 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1653 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1654 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1655 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1656 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1657 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1658 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1659 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1660 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1661 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1662 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1663 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1664 {
1665 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1666 .name = "Capture Source",
1667 .info = snd_cs4231_info_mux,
1668 .get = snd_cs4231_get_mux,
1669 .put = snd_cs4231_put_mux,
1670 },
1671 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1672 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1673 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1674 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1675 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1676 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1677 };
1678
1679 static int __init snd_cs4231_mixer(struct snd_cs4231 *chip)
1680 {
1681 struct snd_card *card;
1682 int err, idx;
1683
1684 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1685
1686 card = chip->card;
1687
1688 strcpy(card->mixername, chip->pcm->name);
1689
1690 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1691 if ((err = snd_ctl_add(card,
1692 snd_ctl_new1(&snd_cs4231_controls[idx],
1693 chip))) < 0)
1694 return err;
1695 }
1696 return 0;
1697 }
1698
1699 static int dev;
1700
1701 static int __init cs4231_attach_begin(struct snd_card **rcard)
1702 {
1703 struct snd_card *card;
1704
1705 *rcard = NULL;
1706
1707 if (dev >= SNDRV_CARDS)
1708 return -ENODEV;
1709
1710 if (!enable[dev]) {
1711 dev++;
1712 return -ENOENT;
1713 }
1714
1715 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1716 if (card == NULL)
1717 return -ENOMEM;
1718
1719 strcpy(card->driver, "CS4231");
1720 strcpy(card->shortname, "Sun CS4231");
1721
1722 *rcard = card;
1723 return 0;
1724 }
1725
1726 static int __init cs4231_attach_finish(struct snd_card *card, struct snd_cs4231 *chip)
1727 {
1728 int err;
1729
1730 if ((err = snd_cs4231_pcm(chip)) < 0)
1731 goto out_err;
1732
1733 if ((err = snd_cs4231_mixer(chip)) < 0)
1734 goto out_err;
1735
1736 if ((err = snd_cs4231_timer(chip)) < 0)
1737 goto out_err;
1738
1739 if ((err = snd_card_register(card)) < 0)
1740 goto out_err;
1741
1742 chip->next = cs4231_list;
1743 cs4231_list = chip;
1744
1745 dev++;
1746 return 0;
1747
1748 out_err:
1749 snd_card_free(card);
1750 return err;
1751 }
1752
1753 #ifdef SBUS_SUPPORT
1754
1755 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
1756 {
1757 unsigned long flags;
1758 unsigned char status;
1759 u32 csr;
1760 struct snd_cs4231 *chip = dev_id;
1761
1762 /*This is IRQ is not raised by the cs4231*/
1763 if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
1764 return IRQ_NONE;
1765
1766 /* ACK the APC interrupt. */
1767 csr = sbus_readl(chip->port + APCCSR);
1768
1769 sbus_writel(csr, chip->port + APCCSR);
1770
1771 if ((csr & APC_PDMA_READY) &&
1772 (csr & APC_PLAY_INT) &&
1773 (csr & APC_XINT_PNVA) &&
1774 !(csr & APC_XINT_EMPT))
1775 snd_cs4231_play_callback(chip);
1776
1777 if ((csr & APC_CDMA_READY) &&
1778 (csr & APC_CAPT_INT) &&
1779 (csr & APC_XINT_CNVA) &&
1780 !(csr & APC_XINT_EMPT))
1781 snd_cs4231_capture_callback(chip);
1782
1783 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1784
1785 if (status & CS4231_TIMER_IRQ) {
1786 if (chip->timer)
1787 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1788 }
1789
1790 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1791 snd_cs4231_overrange(chip);
1792
1793 /* ACK the CS4231 interrupt. */
1794 spin_lock_irqsave(&chip->lock, flags);
1795 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1796 spin_unlock_irqrestore(&chip->lock, flags);
1797
1798 return IRQ_HANDLED;
1799 }
1800
1801 /*
1802 * SBUS DMA routines
1803 */
1804
1805 static int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
1806 {
1807 unsigned long flags;
1808 u32 test, csr;
1809 int err;
1810 struct sbus_dma_info *base = &dma_cont->sbus_info;
1811
1812 if (len >= (1 << 24))
1813 return -EINVAL;
1814 spin_lock_irqsave(&base->lock, flags);
1815 csr = sbus_readl(base->regs + APCCSR);
1816 err = -EINVAL;
1817 test = APC_CDMA_READY;
1818 if ( base->dir == APC_PLAY )
1819 test = APC_PDMA_READY;
1820 if (!(csr & test))
1821 goto out;
1822 err = -EBUSY;
1823 test = APC_XINT_CNVA;
1824 if ( base->dir == APC_PLAY )
1825 test = APC_XINT_PNVA;
1826 if (!(csr & test))
1827 goto out;
1828 err = 0;
1829 sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1830 sbus_writel(len, base->regs + base->dir + APCNC);
1831 out:
1832 spin_unlock_irqrestore(&base->lock, flags);
1833 return err;
1834 }
1835
1836 static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
1837 {
1838 unsigned long flags;
1839 u32 csr, test;
1840 struct sbus_dma_info *base = &dma_cont->sbus_info;
1841
1842 spin_lock_irqsave(&base->lock, flags);
1843 csr = sbus_readl(base->regs + APCCSR);
1844 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1845 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1846 APC_XINT_PENA;
1847 if ( base->dir == APC_RECORD )
1848 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1849 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1850 csr |= test;
1851 sbus_writel(csr, base->regs + APCCSR);
1852 spin_unlock_irqrestore(&base->lock, flags);
1853 }
1854
1855 static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
1856 {
1857 unsigned long flags;
1858 u32 csr, shift;
1859 struct sbus_dma_info *base = &dma_cont->sbus_info;
1860
1861 spin_lock_irqsave(&base->lock, flags);
1862 if (!on) {
1863 sbus_writel(0, base->regs + base->dir + APCNC);
1864 sbus_writel(0, base->regs + base->dir + APCNVA);
1865 sbus_writel(0, base->regs + base->dir + APCC);
1866 sbus_writel(0, base->regs + base->dir + APCVA);
1867
1868 /* ACK any APC interrupts. */
1869 csr = sbus_readl(base->regs + APCCSR);
1870 sbus_writel(csr, base->regs + APCCSR);
1871 }
1872 udelay(1000);
1873 csr = sbus_readl(base->regs + APCCSR);
1874 shift = 0;
1875 if ( base->dir == APC_PLAY )
1876 shift = 1;
1877 if (on)
1878 csr &= ~(APC_CPAUSE << shift);
1879 else
1880 csr |= (APC_CPAUSE << shift);
1881 sbus_writel(csr, base->regs + APCCSR);
1882 if (on)
1883 csr |= (APC_CDMA_READY << shift);
1884 else
1885 csr &= ~(APC_CDMA_READY << shift);
1886 sbus_writel(csr, base->regs + APCCSR);
1887
1888 spin_unlock_irqrestore(&base->lock, flags);
1889 }
1890
1891 static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
1892 {
1893 struct sbus_dma_info *base = &dma_cont->sbus_info;
1894
1895 return sbus_readl(base->regs + base->dir + APCVA);
1896 }
1897
1898 static void sbus_dma_reset(struct snd_cs4231 *chip)
1899 {
1900 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
1901 sbus_writel(0x00, chip->port + APCCSR);
1902 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
1903 chip->port + APCCSR);
1904
1905 udelay(20);
1906
1907 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
1908 chip->port + APCCSR);
1909 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
1910 APC_XINT_PENA |
1911 APC_XINT_CENA),
1912 chip->port + APCCSR);
1913 }
1914
1915 static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
1916 {
1917 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
1918 snd_dma_sbus_data(chip->dev_u.sdev),
1919 64*1024, 128*1024);
1920 }
1921
1922 /*
1923 * Init and exit routines
1924 */
1925
1926 static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
1927 {
1928 if (chip->irq[0])
1929 free_irq(chip->irq[0], chip);
1930
1931 if (chip->port)
1932 sbus_iounmap(chip->port, chip->regs_size);
1933
1934 kfree(chip);
1935
1936 return 0;
1937 }
1938
1939 static int snd_cs4231_sbus_dev_free(struct snd_device *device)
1940 {
1941 struct snd_cs4231 *cp = device->device_data;
1942
1943 return snd_cs4231_sbus_free(cp);
1944 }
1945
1946 static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
1947 .dev_free = snd_cs4231_sbus_dev_free,
1948 };
1949
1950 static int __init snd_cs4231_sbus_create(struct snd_card *card,
1951 struct sbus_dev *sdev,
1952 int dev,
1953 struct snd_cs4231 **rchip)
1954 {
1955 struct snd_cs4231 *chip;
1956 int err;
1957
1958 *rchip = NULL;
1959 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1960 if (chip == NULL)
1961 return -ENOMEM;
1962
1963 spin_lock_init(&chip->lock);
1964 spin_lock_init(&chip->c_dma.sbus_info.lock);
1965 spin_lock_init(&chip->p_dma.sbus_info.lock);
1966 mutex_init(&chip->mce_mutex);
1967 mutex_init(&chip->open_mutex);
1968 chip->card = card;
1969 chip->dev_u.sdev = sdev;
1970 chip->regs_size = sdev->reg_addrs[0].reg_size;
1971 memcpy(&chip->image, &snd_cs4231_original_image,
1972 sizeof(snd_cs4231_original_image));
1973
1974 chip->port = sbus_ioremap(&sdev->resource[0], 0,
1975 chip->regs_size, "cs4231");
1976 if (!chip->port) {
1977 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1978 return -EIO;
1979 }
1980
1981 chip->c_dma.sbus_info.regs = chip->port;
1982 chip->p_dma.sbus_info.regs = chip->port;
1983 chip->c_dma.sbus_info.dir = APC_RECORD;
1984 chip->p_dma.sbus_info.dir = APC_PLAY;
1985
1986 chip->p_dma.prepare = sbus_dma_prepare;
1987 chip->p_dma.enable = sbus_dma_enable;
1988 chip->p_dma.request = sbus_dma_request;
1989 chip->p_dma.address = sbus_dma_addr;
1990 chip->p_dma.reset = sbus_dma_reset;
1991 chip->p_dma.preallocate = sbus_dma_preallocate;
1992
1993 chip->c_dma.prepare = sbus_dma_prepare;
1994 chip->c_dma.enable = sbus_dma_enable;
1995 chip->c_dma.request = sbus_dma_request;
1996 chip->c_dma.address = sbus_dma_addr;
1997 chip->c_dma.reset = sbus_dma_reset;
1998 chip->c_dma.preallocate = sbus_dma_preallocate;
1999
2000 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
2001 IRQF_SHARED, "cs4231", chip)) {
2002 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
2003 dev, sdev->irqs[0]);
2004 snd_cs4231_sbus_free(chip);
2005 return -EBUSY;
2006 }
2007 chip->irq[0] = sdev->irqs[0];
2008
2009 if (snd_cs4231_probe(chip) < 0) {
2010 snd_cs4231_sbus_free(chip);
2011 return -ENODEV;
2012 }
2013 snd_cs4231_init(chip);
2014
2015 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2016 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2017 snd_cs4231_sbus_free(chip);
2018 return err;
2019 }
2020
2021 *rchip = chip;
2022 return 0;
2023 }
2024
2025 static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
2026 {
2027 struct resource *rp = &sdev->resource[0];
2028 struct snd_cs4231 *cp;
2029 struct snd_card *card;
2030 int err;
2031
2032 err = cs4231_attach_begin(&card);
2033 if (err)
2034 return err;
2035
2036 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2037 card->shortname,
2038 rp->flags & 0xffL,
2039 (unsigned long long)rp->start,
2040 sdev->irqs[0]);
2041
2042 if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
2043 snd_card_free(card);
2044 return err;
2045 }
2046
2047 return cs4231_attach_finish(card, cp);
2048 }
2049 #endif
2050
2051 #ifdef EBUS_SUPPORT
2052
2053 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
2054 {
2055 struct snd_cs4231 *chip = cookie;
2056
2057 snd_cs4231_play_callback(chip);
2058 }
2059
2060 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
2061 {
2062 struct snd_cs4231 *chip = cookie;
2063
2064 snd_cs4231_capture_callback(chip);
2065 }
2066
2067 /*
2068 * EBUS DMA wrappers
2069 */
2070
2071 static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
2072 {
2073 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
2074 }
2075
2076 static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
2077 {
2078 ebus_dma_enable(&dma_cont->ebus_info, on);
2079 }
2080
2081 static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
2082 {
2083 ebus_dma_prepare(&dma_cont->ebus_info, dir);
2084 }
2085
2086 static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
2087 {
2088 return ebus_dma_addr(&dma_cont->ebus_info);
2089 }
2090
2091 static void _ebus_dma_reset(struct snd_cs4231 *chip)
2092 {
2093 return;
2094 }
2095
2096 static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
2097 {
2098 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2099 snd_dma_pci_data(chip->dev_u.pdev),
2100 64*1024, 128*1024);
2101 }
2102
2103 /*
2104 * Init and exit routines
2105 */
2106
2107 static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
2108 {
2109 if (chip->c_dma.ebus_info.regs) {
2110 ebus_dma_unregister(&chip->c_dma.ebus_info);
2111 iounmap(chip->c_dma.ebus_info.regs);
2112 }
2113 if (chip->p_dma.ebus_info.regs) {
2114 ebus_dma_unregister(&chip->p_dma.ebus_info);
2115 iounmap(chip->p_dma.ebus_info.regs);
2116 }
2117
2118 if (chip->port)
2119 iounmap(chip->port);
2120
2121 kfree(chip);
2122
2123 return 0;
2124 }
2125
2126 static int snd_cs4231_ebus_dev_free(struct snd_device *device)
2127 {
2128 struct snd_cs4231 *cp = device->device_data;
2129
2130 return snd_cs4231_ebus_free(cp);
2131 }
2132
2133 static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
2134 .dev_free = snd_cs4231_ebus_dev_free,
2135 };
2136
2137 static int __init snd_cs4231_ebus_create(struct snd_card *card,
2138 struct linux_ebus_device *edev,
2139 int dev,
2140 struct snd_cs4231 **rchip)
2141 {
2142 struct snd_cs4231 *chip;
2143 int err;
2144
2145 *rchip = NULL;
2146 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2147 if (chip == NULL)
2148 return -ENOMEM;
2149
2150 spin_lock_init(&chip->lock);
2151 spin_lock_init(&chip->c_dma.ebus_info.lock);
2152 spin_lock_init(&chip->p_dma.ebus_info.lock);
2153 mutex_init(&chip->mce_mutex);
2154 mutex_init(&chip->open_mutex);
2155 chip->flags |= CS4231_FLAG_EBUS;
2156 chip->card = card;
2157 chip->dev_u.pdev = edev->bus->self;
2158 memcpy(&chip->image, &snd_cs4231_original_image,
2159 sizeof(snd_cs4231_original_image));
2160 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
2161 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2162 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
2163 chip->c_dma.ebus_info.client_cookie = chip;
2164 chip->c_dma.ebus_info.irq = edev->irqs[0];
2165 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
2166 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2167 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
2168 chip->p_dma.ebus_info.client_cookie = chip;
2169 chip->p_dma.ebus_info.irq = edev->irqs[1];
2170
2171 chip->p_dma.prepare = _ebus_dma_prepare;
2172 chip->p_dma.enable = _ebus_dma_enable;
2173 chip->p_dma.request = _ebus_dma_request;
2174 chip->p_dma.address = _ebus_dma_addr;
2175 chip->p_dma.reset = _ebus_dma_reset;
2176 chip->p_dma.preallocate = _ebus_dma_preallocate;
2177
2178 chip->c_dma.prepare = _ebus_dma_prepare;
2179 chip->c_dma.enable = _ebus_dma_enable;
2180 chip->c_dma.request = _ebus_dma_request;
2181 chip->c_dma.address = _ebus_dma_addr;
2182 chip->c_dma.reset = _ebus_dma_reset;
2183 chip->c_dma.preallocate = _ebus_dma_preallocate;
2184
2185 chip->port = ioremap(edev->resource[0].start, 0x10);
2186 chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
2187 chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
2188 if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) {
2189 snd_cs4231_ebus_free(chip);
2190 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
2191 return -EIO;
2192 }
2193
2194 if (ebus_dma_register(&chip->c_dma.ebus_info)) {
2195 snd_cs4231_ebus_free(chip);
2196 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
2197 return -EBUSY;
2198 }
2199 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
2200 snd_cs4231_ebus_free(chip);
2201 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
2202 return -EBUSY;
2203 }
2204
2205 if (ebus_dma_register(&chip->p_dma.ebus_info)) {
2206 snd_cs4231_ebus_free(chip);
2207 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
2208 return -EBUSY;
2209 }
2210 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
2211 snd_cs4231_ebus_free(chip);
2212 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
2213 return -EBUSY;
2214 }
2215
2216 if (snd_cs4231_probe(chip) < 0) {
2217 snd_cs4231_ebus_free(chip);
2218 return -ENODEV;
2219 }
2220 snd_cs4231_init(chip);
2221
2222 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2223 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2224 snd_cs4231_ebus_free(chip);
2225 return err;
2226 }
2227
2228 *rchip = chip;
2229 return 0;
2230 }
2231
2232 static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
2233 {
2234 struct snd_card *card;
2235 struct snd_cs4231 *chip;
2236 int err;
2237
2238 err = cs4231_attach_begin(&card);
2239 if (err)
2240 return err;
2241
2242 sprintf(card->longname, "%s at 0x%lx, irq %d",
2243 card->shortname,
2244 edev->resource[0].start,
2245 edev->irqs[0]);
2246
2247 if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
2248 snd_card_free(card);
2249 return err;
2250 }
2251
2252 return cs4231_attach_finish(card, chip);
2253 }
2254 #endif
2255
2256 static int __init cs4231_init(void)
2257 {
2258 #ifdef SBUS_SUPPORT
2259 struct sbus_bus *sbus;
2260 struct sbus_dev *sdev;
2261 #endif
2262 #ifdef EBUS_SUPPORT
2263 struct linux_ebus *ebus;
2264 struct linux_ebus_device *edev;
2265 #endif
2266 int found;
2267
2268 found = 0;
2269
2270 #ifdef SBUS_SUPPORT
2271 for_all_sbusdev(sdev, sbus) {
2272 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2273 if (cs4231_sbus_attach(sdev) == 0)
2274 found++;
2275 }
2276 }
2277 #endif
2278 #ifdef EBUS_SUPPORT
2279 for_each_ebus(ebus) {
2280 for_each_ebusdev(edev, ebus) {
2281 int match = 0;
2282
2283 if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) {
2284 match = 1;
2285 } else if (!strcmp(edev->prom_node->name, "audio")) {
2286 const char *compat;
2287
2288 compat = of_get_property(edev->prom_node,
2289 "compatible", NULL);
2290 if (compat && !strcmp(compat, "SUNW,CS4231"))
2291 match = 1;
2292 }
2293
2294 if (match &&
2295 cs4231_ebus_attach(edev) == 0)
2296 found++;
2297 }
2298 }
2299 #endif
2300
2301
2302 return (found > 0) ? 0 : -EIO;
2303 }
2304
2305 static void __exit cs4231_exit(void)
2306 {
2307 struct snd_cs4231 *p = cs4231_list;
2308
2309 while (p != NULL) {
2310 struct snd_cs4231 *next = p->next;
2311
2312 snd_card_free(p->card);
2313
2314 p = next;
2315 }
2316
2317 cs4231_list = NULL;
2318 }
2319
2320 module_init(cs4231_init);
2321 module_exit(cs4231_exit);
linux kernel for loongson