2 * pata_efar.c - EFAR PIIX clone controller driver
4 * (C) 2005 Red Hat <alan@redhat.com>
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
9 * Intel ICH controllers the EFAR widened the UDMA mode register bits
10 * and doesn't require the funky clock selection.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/blkdev.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <scsi/scsi_host.h>
21 #include <linux/libata.h>
22 #include <linux/ata.h>
24 #define DRV_NAME "pata_efar"
25 #define DRV_VERSION "0.4.1"
28 * efar_pre_reset - check for 40/80 pin
31 * Perform cable detection for the EFAR ATA interface. This is
32 * different to the PIIX arrangement
35 static int efar_pre_reset(struct ata_port
*ap
)
37 static const struct pci_bits efar_enable_bits
[] = {
38 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
39 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
42 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
45 if (!pci_test_config_bits(pdev
, &efar_enable_bits
[ap
->port_no
])) {
47 printk(KERN_INFO
"ata%u: port disabled. ignoring.\n", ap
->id
);
50 pci_read_config_byte(pdev
, 0x47, &tmp
);
51 if (tmp
& (2 >> ap
->port_no
))
52 ap
->cbl
= ATA_CBL_PATA40
;
54 ap
->cbl
= ATA_CBL_PATA80
;
55 return ata_std_prereset(ap
);
59 * efar_probe_reset - Probe specified port on PATA host controller
63 * None (inherited from caller).
66 static void efar_error_handler(struct ata_port
*ap
)
68 ata_bmdma_drive_eh(ap
, efar_pre_reset
, ata_std_softreset
, NULL
, ata_std_postreset
);
72 * efar_set_piomode - Initialize host controller PATA PIO timings
73 * @ap: Port whose timings we are configuring
76 * Set PIO mode for device, in host controller PCI config space.
79 * None (inherited from caller).
82 static void efar_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
84 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
85 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
86 unsigned int idetm_port
= ap
->port_no
? 0x42 : 0x40;
91 * See Intel Document 298600-004 for the timing programing rules
92 * for PIIX/ICH. The EFAR is a clone so very similar
95 static const /* ISP RTC */
96 u8 timings
[][2] = { { 0, 0 },
103 control
|= 1; /* TIME1 enable */
104 if (ata_pio_need_iordy(adev
)) /* PIO 3/4 require IORDY */
105 control
|= 2; /* IE enable */
106 /* Intel specifies that the PPE functionality is for disk only */
107 if (adev
->class == ATA_DEV_ATA
)
108 control
|= 4; /* PPE enable */
110 pci_read_config_word(dev
, idetm_port
, &idetm_data
);
112 /* Enable PPE, IE and TIME as appropriate */
114 if (adev
->devno
== 0) {
115 idetm_data
&= 0xCCF0;
116 idetm_data
|= control
;
117 idetm_data
|= (timings
[pio
][0] << 12) |
118 (timings
[pio
][1] << 8);
120 int shift
= 4 * ap
->port_no
;
123 idetm_data
&= 0xCC0F;
124 idetm_data
|= (control
<< 4);
126 /* Slave timing in seperate register */
127 pci_read_config_byte(dev
, 0x44, &slave_data
);
128 slave_data
&= 0x0F << shift
;
129 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << shift
;
130 pci_write_config_byte(dev
, 0x44, slave_data
);
133 idetm_data
|= 0x4000; /* Ensure SITRE is enabled */
134 pci_write_config_word(dev
, idetm_port
, idetm_data
);
138 * efar_set_dmamode - Initialize host controller PATA DMA timings
139 * @ap: Port whose timings we are configuring
140 * @adev: Device to program
142 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
145 * None (inherited from caller).
148 static void efar_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
150 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
151 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
153 u8 speed
= adev
->dma_mode
;
154 int devid
= adev
->devno
+ 2 * ap
->port_no
;
157 static const /* ISP RTC */
158 u8 timings
[][2] = { { 0, 0 },
164 pci_read_config_word(dev
, master_port
, &master_data
);
165 pci_read_config_byte(dev
, 0x48, &udma_enable
);
167 if (speed
>= XFER_UDMA_0
) {
168 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
171 udma_enable
|= (1 << devid
);
173 /* Load the UDMA mode number */
174 pci_read_config_word(dev
, 0x4A, &udma_timing
);
175 udma_timing
&= ~(7 << (4 * devid
));
176 udma_timing
|= udma
<< (4 * devid
);
177 pci_write_config_word(dev
, 0x4A, udma_timing
);
180 * MWDMA is driven by the PIO timings. We must also enable
181 * IORDY unconditionally along with TIME1. PPE has already
182 * been set when the PIO timing was set.
184 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
185 unsigned int control
;
187 const unsigned int needed_pio
[3] = {
188 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
190 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
192 control
= 3; /* IORDY|TIME1 */
194 /* If the drive MWDMA is faster than it can do PIO then
195 we must force PIO into PIO0 */
197 if (adev
->pio_mode
< needed_pio
[mwdma
])
198 /* Enable DMA timing only */
199 control
|= 8; /* PIO cycles in PIO0 */
201 if (adev
->devno
) { /* Slave */
202 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
203 master_data
|= control
<< 4;
204 pci_read_config_byte(dev
, 0x44, &slave_data
);
205 slave_data
&= (0x0F + 0xE1 * ap
->port_no
);
206 /* Load the matching timing */
207 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
208 pci_write_config_byte(dev
, 0x44, slave_data
);
209 } else { /* Master */
210 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
211 and master timing bits */
212 master_data
|= control
;
214 (timings
[pio
][0] << 12) |
215 (timings
[pio
][1] << 8);
217 udma_enable
&= ~(1 << devid
);
218 pci_write_config_word(dev
, master_port
, master_data
);
220 pci_write_config_byte(dev
, 0x48, udma_enable
);
223 static struct scsi_host_template efar_sht
= {
224 .module
= THIS_MODULE
,
226 .ioctl
= ata_scsi_ioctl
,
227 .queuecommand
= ata_scsi_queuecmd
,
228 .can_queue
= ATA_DEF_QUEUE
,
229 .this_id
= ATA_SHT_THIS_ID
,
230 .sg_tablesize
= LIBATA_MAX_PRD
,
231 .max_sectors
= ATA_MAX_SECTORS
,
232 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
233 .emulated
= ATA_SHT_EMULATED
,
234 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
235 .proc_name
= DRV_NAME
,
236 .dma_boundary
= ATA_DMA_BOUNDARY
,
237 .slave_configure
= ata_scsi_slave_config
,
238 .bios_param
= ata_std_bios_param
,
241 static const struct ata_port_operations efar_ops
= {
242 .port_disable
= ata_port_disable
,
243 .set_piomode
= efar_set_piomode
,
244 .set_dmamode
= efar_set_dmamode
,
245 .mode_filter
= ata_pci_default_filter
,
247 .tf_load
= ata_tf_load
,
248 .tf_read
= ata_tf_read
,
249 .check_status
= ata_check_status
,
250 .exec_command
= ata_exec_command
,
251 .dev_select
= ata_std_dev_select
,
253 .freeze
= ata_bmdma_freeze
,
254 .thaw
= ata_bmdma_thaw
,
255 .error_handler
= efar_error_handler
,
256 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
258 .bmdma_setup
= ata_bmdma_setup
,
259 .bmdma_start
= ata_bmdma_start
,
260 .bmdma_stop
= ata_bmdma_stop
,
261 .bmdma_status
= ata_bmdma_status
,
262 .qc_prep
= ata_qc_prep
,
263 .qc_issue
= ata_qc_issue_prot
,
264 .data_xfer
= ata_pio_data_xfer
,
266 .eng_timeout
= ata_eng_timeout
,
268 .irq_handler
= ata_interrupt
,
269 .irq_clear
= ata_bmdma_irq_clear
,
271 .port_start
= ata_port_start
,
272 .port_stop
= ata_port_stop
,
273 .host_stop
= ata_host_stop
,
278 * efar_init_one - Register EFAR ATA PCI device with kernel services
279 * @pdev: PCI device to register
280 * @ent: Entry in efar_pci_tbl matching with @pdev
282 * Called from kernel PCI layer.
285 * Inherited from PCI layer (may sleep).
288 * Zero on success, or -ERRNO value.
291 static int efar_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
293 static int printed_version
;
294 static struct ata_port_info info
= {
296 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
297 .pio_mask
= 0x1f, /* pio0-4 */
298 .mwdma_mask
= 0x07, /* mwdma1-2 */
299 .udma_mask
= 0x0f, /* UDMA 66 */
300 .port_ops
= &efar_ops
,
302 static struct ata_port_info
*port_info
[2] = { &info
, &info
};
304 if (!printed_version
++)
305 dev_printk(KERN_DEBUG
, &pdev
->dev
,
306 "version " DRV_VERSION
"\n");
308 return ata_pci_init_one(pdev
, port_info
, 2);
311 static const struct pci_device_id efar_pci_tbl
[] = {
312 { 0x1055, 0x9130, PCI_ANY_ID
, PCI_ANY_ID
, },
313 { } /* terminate list */
316 static struct pci_driver efar_pci_driver
= {
318 .id_table
= efar_pci_tbl
,
319 .probe
= efar_init_one
,
320 .remove
= ata_pci_remove_one
,
323 static int __init
efar_init(void)
325 return pci_register_driver(&efar_pci_driver
);
328 static void __exit
efar_exit(void)
330 pci_unregister_driver(&efar_pci_driver
);
334 module_init(efar_init
);
335 module_exit(efar_exit
);
337 MODULE_AUTHOR("Alan Cox");
338 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
339 MODULE_LICENSE("GPL");
340 MODULE_DEVICE_TABLE(pci
, efar_pci_tbl
);
341 MODULE_VERSION(DRV_VERSION
);