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Merge branch 'master'
[linux-2.6/linux-loongson.git] / arch / ppc / platforms / radstone_ppc7d.c
blob872c0a3ba3c798b2e1297da971d517ee30ed023a
1 /*
2 * arch/ppc/platforms/radstone_ppc7d.c
3 *
4 * Board setup routines for the Radstone PPC7D boards.
5 *
6 * Author: James Chapman <jchapman@katalix.com>
7 *
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17 /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
18 * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
19 * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
20 * SCSI / VGA.
21 */
22
23 #include <linux/config.h>
24 #include <linux/stddef.h>
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/errno.h>
28 #include <linux/reboot.h>
29 #include <linux/pci.h>
30 #include <linux/kdev_t.h>
31 #include <linux/major.h>
32 #include <linux/initrd.h>
33 #include <linux/console.h>
34 #include <linux/delay.h>
35 #include <linux/ide.h>
36 #include <linux/seq_file.h>
37 #include <linux/root_dev.h>
38 #include <linux/serial.h>
39 #include <linux/tty.h> /* for linux/serial_core.h */
40 #include <linux/serial_core.h>
41 #include <linux/mv643xx.h>
42 #include <linux/netdevice.h>
43 #include <linux/platform_device.h>
44
45 #include <asm/system.h>
46 #include <asm/pgtable.h>
47 #include <asm/page.h>
48 #include <asm/time.h>
49 #include <asm/dma.h>
50 #include <asm/io.h>
51 #include <asm/machdep.h>
52 #include <asm/prom.h>
53 #include <asm/smp.h>
54 #include <asm/vga.h>
55 #include <asm/open_pic.h>
56 #include <asm/i8259.h>
57 #include <asm/todc.h>
58 #include <asm/bootinfo.h>
59 #include <asm/mpc10x.h>
60 #include <asm/pci-bridge.h>
61 #include <asm/mv64x60.h>
62
63 #include "radstone_ppc7d.h"
64
65 #undef DEBUG
66
67 #define PPC7D_RST_PIN 17 /* GPP17 */
68
69 extern u32 mv64360_irq_base;
70 extern spinlock_t rtc_lock;
71
72 static struct mv64x60_handle bh;
73 static int ppc7d_has_alma;
74
75 extern void gen550_progress(char *, unsigned short);
76 extern void gen550_init(int, struct uart_port *);
77
78 /* FIXME - move to h file */
79 extern int ds1337_do_command(int id, int cmd, void *arg);
80 #define DS1337_GET_DATE 0
81 #define DS1337_SET_DATE 1
82
83 /* residual data */
84 unsigned char __res[sizeof(bd_t)];
85
86 /*****************************************************************************
87 * Serial port code
88 *****************************************************************************/
89
90 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
91 static void __init ppc7d_early_serial_map(void)
92 {
93 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
94 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
95 #elif defined(CONFIG_SERIAL_8250)
96 struct uart_port serial_req;
97
98 /* Setup serial port access */
99 memset(&serial_req, 0, sizeof(serial_req));
100 serial_req.uartclk = UART_CLK;
101 serial_req.irq = 4;
102 serial_req.flags = STD_COM_FLAGS;
103 serial_req.iotype = UPIO_MEM;
104 serial_req.membase = (u_char *) PPC7D_SERIAL_0;
105
106 gen550_init(0, &serial_req);
107 if (early_serial_setup(&serial_req) != 0)
108 printk(KERN_ERR "Early serial init of port 0 failed\n");
109
110 /* Assume early_serial_setup() doesn't modify serial_req */
111 serial_req.line = 1;
112 serial_req.irq = 3;
113 serial_req.membase = (u_char *) PPC7D_SERIAL_1;
114
115 gen550_init(1, &serial_req);
116 if (early_serial_setup(&serial_req) != 0)
117 printk(KERN_ERR "Early serial init of port 1 failed\n");
118 #else
119 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
120 #endif
121 }
122 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
123
124 /*****************************************************************************
125 * Low-level board support code
126 *****************************************************************************/
127
128 static unsigned long __init ppc7d_find_end_of_memory(void)
129 {
130 bd_t *bp = (bd_t *) __res;
131
132 if (bp->bi_memsize)
133 return bp->bi_memsize;
134
135 return (256 * 1024 * 1024);
136 }
137
138 static void __init ppc7d_map_io(void)
139 {
140 /* remove temporary mapping */
141 mtspr(SPRN_DBAT3U, 0x00000000);
142 mtspr(SPRN_DBAT3L, 0x00000000);
143
144 io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
145 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
146 }
147
148 static void ppc7d_restart(char *cmd)
149 {
150 u32 data;
151
152 /* Disable GPP17 interrupt */
153 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
154 data &= ~(1 << PPC7D_RST_PIN);
155 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
156
157 /* Configure MPP17 as GPP */
158 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
159 data &= ~(0x0000000f << 4);
160 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
161
162 /* Enable pin GPP17 for output */
163 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
164 data |= (1 << PPC7D_RST_PIN);
165 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
166
167 /* Toggle GPP9 pin to reset the board */
168 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
169 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
170
171 for (;;) ; /* Spin until reset happens */
172 /* NOTREACHED */
173 }
174
175 static void ppc7d_power_off(void)
176 {
177 u32 data;
178
179 local_irq_disable();
180
181 /* Ensure that internal MV643XX watchdog is disabled.
182 * The Disco watchdog uses MPP17 on this hardware.
183 */
184 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
185 data &= ~(0x0000000f << 4);
186 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
187
188 data = mv64x60_read(&bh, MV64x60_WDT_WDC);
189 if (data & 0x80000000) {
190 mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
191 mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
192 }
193
194 for (;;) ; /* No way to shut power off with software */
195 /* NOTREACHED */
196 }
197
198 static void ppc7d_halt(void)
199 {
200 ppc7d_power_off();
201 /* NOTREACHED */
202 }
203
204 static unsigned long ppc7d_led_no_pulse;
205
206 static int __init ppc7d_led_pulse_disable(char *str)
207 {
208 ppc7d_led_no_pulse = 1;
209 return 1;
210 }
211
212 /* This kernel option disables the heartbeat pulsing of a board LED */
213 __setup("ledoff", ppc7d_led_pulse_disable);
214
215 static void ppc7d_heartbeat(void)
216 {
217 u32 data32;
218 u8 data8;
219 static int max706_wdog = 0;
220
221 /* Unfortunately we can't access the LED control registers
222 * during early init because they're on the CPLD which is the
223 * other side of a PCI bridge which goes unreachable during
224 * PCI scan. So write the LEDs only if the MV64360 watchdog is
225 * enabled (i.e. userspace apps are running so kernel is up)..
226 */
227 data32 = mv64x60_read(&bh, MV64x60_WDT_WDC);
228 if (data32 & 0x80000000) {
229 /* Enable MAX706 watchdog if not done already */
230 if (!max706_wdog) {
231 outb(3, PPC7D_CPLD_RESET);
232 max706_wdog = 1;
233 }
234
235 /* Hit the MAX706 watchdog */
236 outb(0, PPC7D_CPLD_WATCHDOG_TRIG);
237
238 /* Pulse LED DS219 if not disabled */
239 if (!ppc7d_led_no_pulse) {
240 static int led_on = 0;
241
242 data8 = inb(PPC7D_CPLD_LEDS);
243 if (led_on)
244 data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK;
245 else
246 data8 |= PPC7D_CPLD_LEDS_DS219_MASK;
247
248 outb(data8, PPC7D_CPLD_LEDS);
249 led_on = !led_on;
250 }
251 }
252 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
253 }
254
255 static int ppc7d_show_cpuinfo(struct seq_file *m)
256 {
257 u8 val;
258 u8 val1, val2;
259 static int flash_sizes[4] = { 64, 32, 0, 16 };
260 static int flash_banks[4] = { 4, 3, 2, 1 };
261 static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
262 int sdram_num_banks = 2;
263 static char *pci_modes[] = { "PCI33", "PCI66",
264 "Unknown", "Unknown",
265 "PCIX33", "PCIX66",
266 "PCIX100", "PCIX133"
267 };
268
269 seq_printf(m, "vendor\t\t: Radstone Technology\n");
270 seq_printf(m, "machine\t\t: PPC7D\n");
271
272 val = inb(PPC7D_CPLD_BOARD_REVISION);
273 val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
274 val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK);
275 seq_printf(m, "revision\t: %hd%c%c\n",
276 val1,
277 (val2 <= 0x18) ? 'A' + val2 : 'Y',
278 (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' ');
279
280 val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE);
281 val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK;
282 val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK |
283 PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK);
284 seq_printf(m, "bus speed\t: %dMHz\n",
285 (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 :
286 (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
287 (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
288
289 val = inb(PPC7D_CPLD_MEM_CONFIG);
290 if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
291
292 val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
293 val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
294 seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
295 sdram_num_banks,
296 sdram_bank_sizes[val1],
297 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
298 sdram_num_banks * sdram_bank_sizes[val1],
299 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
300 if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
301 seq_printf(m, " [ECC %sabled]",
302 (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
303 "dis");
304 }
305 seq_printf(m, "\n");
306
307 val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK);
308 val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2;
309 seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n",
310 flash_banks[val2], flash_sizes[val1],
311 flash_banks[val2] * flash_sizes[val1]);
312
313 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL);
314 val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
315 seq_printf(m, " write links\t: %s%s%s%s\n",
316 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "",
317 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "",
318 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "",
319 (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
320 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
321 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) ==
322 0 ? "NONE" : "");
323 seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n",
324 (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " :
325 "",
326 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "",
327 (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "",
328 (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " :
329 "",
330 (((val &
331 (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK |
332 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK |
333 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0)
334 && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ==
335 0)) ? "NONE" : "");
336 val1 =
337 inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) &
338 (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK |
339 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK);
340 seq_printf(m, " software sector enables: %s%s%s\n",
341 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT "
342 : "",
343 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "",
344 (val1 == 0) ? "NONE " : "");
345
346 seq_printf(m, "Boot options\t: %s%s%s%s\n",
347 (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ?
348 "ALTERNATE " : "",
349 (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " :
350 "",
351 (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY "
352 : "",
353 ((val &
354 (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK |
355 PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK |
356 PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) ==
357 0) ? "NONE" : "");
358
359 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1);
360 seq_printf(m, "Fitted modules\t: %s%s%s%s\n",
361 (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ",
362 (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ",
363 (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "",
364 ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
365 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK |
366 PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) ==
367 (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
368 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : "");
369
370 if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) {
371 static const char *ids[] = {
372 "unknown",
373 "1553 (Dual Channel)",
374 "1553 (Single Channel)",
375 "8-bit SCSI + VGA",
376 "16-bit SCSI + VGA",
377 "1553 (Single Channel with sideband)",
378 "1553 (Dual Channel with sideband)",
379 NULL
380 };
381 u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
382 seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
383 id < 7 ? ids[id] : "unknown");
384 }
385
386 val = inb(PPC7D_CPLD_PCI_CONFIG);
387 val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
388 val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
389 seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
390 pci_modes[val1], pci_modes[val2]);
391
392 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
393 seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
394 (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
395 (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
396 seq_printf(m, "PMC power source: %s\n",
397 (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
398 "internal");
399
400 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
401 val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
402 seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
403 (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
404 (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
405 (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
406 (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
407 (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
408 (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
409 (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
410 "");
411
412 val = inb(PPC7D_CPLD_ID_LINK);
413 val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
414 PPC7D_CPLD_ID_LINK_E7_MASK |
415 PPC7D_CPLD_ID_LINK_E12_MASK |
416 PPC7D_CPLD_ID_LINK_E13_MASK);
417
418 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
419 (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
420 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
421 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);
422
423 seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
424 (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
425 (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
426 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
427 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
428 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
429 (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
430 (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
431 ((val == 0) && (val1 == 0)) ? "NONE" : "");
432
433 val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
434 seq_printf(m, "Front panel reset switch: %sabled\n",
435 (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");
436
437 return 0;
438 }
439
440 static void __init ppc7d_calibrate_decr(void)
441 {
442 ulong freq;
443
444 freq = 100000000 / 4;
445
446 pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
447 freq / 1000000, freq % 1000000);
448
449 tb_ticks_per_jiffy = freq / HZ;
450 tb_to_us = mulhwu_scale_factor(freq, 1000000);
451 }
452
453 /*****************************************************************************
454 * Interrupt stuff
455 *****************************************************************************/
456
457 static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs)
458 {
459 u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
460 if (temp & (1 << 28)) {
461 i8259_irq(regs);
462 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
463 return IRQ_HANDLED;
464 }
465
466 return IRQ_NONE;
467 }
468
469 /*
470 * Each interrupt cause is assigned an IRQ number.
471 * Southbridge has 16*2 (two 8259's) interrupts.
472 * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
473 * If multiple interrupts are pending, get_irq() returns the
474 * lowest pending irq number first.
475 *
476 *
477 * IRQ # Source Trig Active
478 * =============================================================
479 *
480 * Southbridge
481 * -----------
482 * IRQ # Source Trig
483 * =============================================================
484 * 0 ISA High Resolution Counter Edge
485 * 1 Keyboard Edge
486 * 2 Cascade From (IRQ 8-15) Edge
487 * 3 Com 2 (Uart 2) Edge
488 * 4 Com 1 (Uart 1) Edge
489 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
490 * 6 GPIO Level
491 * 7 LPT Edge
492 * 8 RTC Alarm Edge
493 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
494 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
495 * 11 USB2 Level
496 * 12 Mouse Edge
497 * 13 Reserved internally by Ali M1535+
498 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
499 * 15 COM 5/6 Level
500 *
501 * 16..112 Discovery-II...
502 *
503 * MPP28 Southbridge Edge High
504 *
505 *
506 * Interrupts are cascaded through to the Discovery-II.
507 *
508 * PCI ---
509 * \
510 * CPLD --> ALI1535 -------> DISCOVERY-II
511 * INTF MPP28
512 */
513 static void __init ppc7d_init_irq(void)
514 {
515 int irq;
516
517 pr_debug("%s\n", __FUNCTION__);
518 i8259_init(0, 0);
519 mv64360_init_irq();
520
521 /* IRQs 5,6,9,10,11,14,15 are level sensitive */
522 irq_desc[5].status |= IRQ_LEVEL;
523 irq_desc[6].status |= IRQ_LEVEL;
524 irq_desc[9].status |= IRQ_LEVEL;
525 irq_desc[10].status |= IRQ_LEVEL;
526 irq_desc[11].status |= IRQ_LEVEL;
527 irq_desc[14].status |= IRQ_LEVEL;
528 irq_desc[15].status |= IRQ_LEVEL;
529
530 /* GPP28 is edge triggered */
531 irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
532 }
533
534 static u32 ppc7d_irq_canonicalize(u32 irq)
535 {
536 if ((irq >= 16) && (irq < (16 + 96)))
537 irq -= 16;
538
539 return irq;
540 }
541
542 static int ppc7d_get_irq(struct pt_regs *regs)
543 {
544 int irq;
545
546 irq = mv64360_get_irq(regs);
547 if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
548 irq = i8259_irq(regs);
549 return irq;
550 }
551
552 /*
553 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
554 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
555 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
556 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
557 */
558 static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
559 unsigned char pin)
560 {
561 static const char pci_irq_table[][4] =
562 /*
563 * PCI IDSEL/INTPIN->INTLINE
564 * A B C D
565 */
566 {
567 {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */
568 {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */
569 {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */
570 {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */
571 };
572 const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
573
574 pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
575 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
576
577 return PCI_IRQ_TABLE_LOOKUP;
578 }
579
580 void __init ppc7d_intr_setup(void)
581 {
582 u32 data;
583
584 /*
585 * Define GPP 28 interrupt polarity as active high
586 * input signal and level triggered
587 */
588 data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
589 data &= ~(1 << 28);
590 mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
591 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
592 data &= ~(1 << 28);
593 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
594
595 /* Config GPP intr ctlr to respond to level trigger */
596 data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
597 data |= (1 << 10);
598 mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
599
600 /* XXXX Erranum FEr PCI-#8 */
601 data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
602 data &= ~((1 << 5) | (1 << 9));
603 mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
604 data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
605 data &= ~((1 << 5) | (1 << 9));
606 mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
607
608 /*
609 * Dismiss and then enable interrupt on GPP interrupt cause
610 * for CPU #0
611 */
612 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
613 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
614 data |= (1 << 28);
615 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
616
617 /*
618 * Dismiss and then enable interrupt on CPU #0 high cause reg
619 * BIT27 summarizes GPP interrupts 23-31
620 */
621 mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
622 data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
623 data |= (1 << 27);
624 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
625 }
626
627 /*****************************************************************************
628 * Platform device data fixup routines.
629 *****************************************************************************/
630
631 #if defined(CONFIG_SERIAL_MPSC)
632 static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
633 {
634 struct mpsc_pdata *pdata;
635
636 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
637
638 pdata->max_idle = 40;
639 pdata->default_baud = PPC7D_DEFAULT_BAUD;
640 pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
641 pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;
642
643 return;
644 }
645 #endif
646
647 #if defined(CONFIG_MV643XX_ETH)
648 static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
649 {
650 struct mv643xx_eth_platform_data *eth_pd;
651 static u16 phy_addr[] = {
652 PPC7D_ETH0_PHY_ADDR,
653 PPC7D_ETH1_PHY_ADDR,
654 PPC7D_ETH2_PHY_ADDR,
655 };
656 int i;
657
658 eth_pd = pdev->dev.platform_data;
659 eth_pd->force_phy_addr = 1;
660 eth_pd->phy_addr = phy_addr[pdev->id];
661 eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
662 eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;
663
664 /* Adjust IRQ by mv64360_irq_base */
665 for (i = 0; i < pdev->num_resources; i++) {
666 struct resource *r = &pdev->resource[i];
667
668 if (r->flags & IORESOURCE_IRQ) {
669 r->start += mv64360_irq_base;
670 r->end += mv64360_irq_base;
671 pr_debug("%s, uses IRQ %d\n", pdev->name,
672 (int)r->start);
673 }
674 }
675
676 }
677 #endif
678
679 #if defined(CONFIG_I2C_MV64XXX)
680 static void __init
681 ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
682 {
683 struct mv64xxx_i2c_pdata *pdata;
684 int i;
685
686 pdata = pdev->dev.platform_data;
687 if (pdata == NULL) {
688 pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
689 if (pdata == NULL)
690 return;
691
692 memset(pdata, 0, sizeof(*pdata));
693 pdev->dev.platform_data = pdata;
694 }
695
696 /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
697 pdata->freq_m = 8;
698 pdata->freq_n = 3;
699 pdata->timeout = 500;
700 pdata->retries = 3;
701
702 /* Adjust IRQ by mv64360_irq_base */
703 for (i = 0; i < pdev->num_resources; i++) {
704 struct resource *r = &pdev->resource[i];
705
706 if (r->flags & IORESOURCE_IRQ) {
707 r->start += mv64360_irq_base;
708 r->end += mv64360_irq_base;
709 pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
710 }
711 }
712 }
713 #endif
714
715 static int __init ppc7d_platform_notify(struct device *dev)
716 {
717 static struct {
718 char *bus_id;
719 void ((*rtn) (struct platform_device * pdev));
720 } dev_map[] = {
721 #if defined(CONFIG_SERIAL_MPSC)
722 { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
723 { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
724 #endif
725 #if defined(CONFIG_MV643XX_ETH)
726 { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
727 { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
728 { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
729 #endif
730 #if defined(CONFIG_I2C_MV64XXX)
731 { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
732 #endif
733 };
734 struct platform_device *pdev;
735 int i;
736
737 if (dev && dev->bus_id)
738 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
739 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
740 BUS_ID_SIZE)) {
741
742 pdev = container_of(dev,
743 struct platform_device,
744 dev);
745 dev_map[i].rtn(pdev);
746 }
747
748 return 0;
749 }
750
751 /*****************************************************************************
752 * PCI device fixups.
753 * These aren't really fixups per se. They are used to init devices as they
754 * are found during PCI scan.
755 *
756 * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
757 * scan in order to find other devices on its secondary side.
758 *****************************************************************************/
759
760 static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
761 {
762 u16 val16;
763
764 if (dev->bus->number == 0) {
765 pr_debug("PCI: HB8 init\n");
766
767 pci_write_config_byte(dev, 0x1c,
768 ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
769 >> 8) | 0x01);
770 pci_write_config_byte(dev, 0x1d,
771 (((PPC7D_PCI0_IO_START_PCI_ADDR +
772 PPC7D_PCI0_IO_SIZE -
773 1) & 0xf000) >> 8) | 0x01);
774 pci_write_config_word(dev, 0x30,
775 PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
776 pci_write_config_word(dev, 0x32,
777 ((PPC7D_PCI0_IO_START_PCI_ADDR +
778 PPC7D_PCI0_IO_SIZE -
779 1) >> 16) & 0xffff);
780
781 pci_write_config_word(dev, 0x20,
782 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
783 pci_write_config_word(dev, 0x22,
784 ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
785 PPC7D_PCI0_MEM0_SIZE -
786 1) >> 16) & 0xffff);
787 pci_write_config_word(dev, 0x24, 0);
788 pci_write_config_word(dev, 0x26, 0);
789 pci_write_config_dword(dev, 0x28, 0);
790 pci_write_config_dword(dev, 0x2c, 0);
791
792 pci_read_config_word(dev, 0x3e, &val16);
793 val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and
794 * SERR to primary
795 */
796 val16 &= ~(1 << 2); /* ISA disable, so all ISA
797 * ports forwarded to secondary
798 */
799 pci_write_config_word(dev, 0x3e, val16);
800 }
801 }
802
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);
804
805 /* This should perhaps be a separate driver as we're actually initializing
806 * the chip for this board here. It's hardly a fixup...
807 */
808 static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
809 {
810 pr_debug("PCI: ALI1535 init\n");
811
812 if (dev->bus->number == 1) {
813 /* Configure the ISA Port Settings */
814 pci_write_config_byte(dev, 0x43, 0x00);
815
816 /* Disable PCI Interrupt polling mode */
817 pci_write_config_byte(dev, 0x45, 0x00);
818
819 /* Multifunction pin select INTFJ -> INTF */
820 pci_write_config_byte(dev, 0x78, 0x00);
821
822 /* Set PCI INT -> IRQ Routing control in for external
823 * pins south bridge.
824 */
825 pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10
826 * [3-0] INT A -> IRQ9
827 */
828 pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5
829 * [3-0] INT C -> IRQ14
830 */
831
832 /* PPC7D setup */
833 /* NEC USB device on IRQ 11 (INTE) - INTF disabled */
834 pci_write_config_byte(dev, 0x4A, 0x09);
835
836 /* GPIO on IRQ 6 */
837 pci_write_config_byte(dev, 0x76, 0x07);
838
839 /* SIRQ I (COMS 5/6) use IRQ line 15.
840 * Positive (not subtractive) address decode.
841 */
842 pci_write_config_byte(dev, 0x44, 0x0f);
843
844 /* SIRQ II disabled */
845 pci_write_config_byte(dev, 0x75, 0x0);
846
847 /* On board USB and RTC disabled */
848 pci_write_config_word(dev, 0x52, (1 << 14));
849 pci_write_config_byte(dev, 0x74, 0x00);
850
851 /* On board IDE disabled */
852 pci_write_config_byte(dev, 0x58, 0x00);
853
854 /* Decode 32-bit addresses */
855 pci_write_config_byte(dev, 0x5b, 0);
856
857 /* Disable docking IO */
858 pci_write_config_word(dev, 0x5c, 0x0000);
859
860 /* Disable modem, enable sound */
861 pci_write_config_byte(dev, 0x77, (1 << 6));
862
863 /* Disable hot-docking mode */
864 pci_write_config_byte(dev, 0x7d, 0x00);
865 }
866 }
867
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);
869
870 static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
871 {
872 /* Early versions of this board were fitted with IBM ALMA
873 * PCI-VME bridge chips. The PCI config space of these devices
874 * was not set up correctly and causes PCI scan problems.
875 */
876 if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
877 return PCIBIOS_DEVICE_NOT_FOUND;
878
879 return mv64x60_pci_exclude_device(bus, devfn);
880 }
881
882 /* This hook is called when each PCI bus is probed.
883 */
884 static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
885 {
886 pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
887 bus->number,
888 bus->resource[0] ? bus->resource[0]->start : 0,
889 bus->resource[0] ? bus->resource[0]->end : 0,
890 bus->resource[1] ? bus->resource[1]->start : 0,
891 bus->resource[1] ? bus->resource[1]->end : 0,
892 bus->resource[2] ? bus->resource[2]->start : 0,
893 bus->resource[2] ? bus->resource[2]->end : 0,
894 bus->resource[3] ? bus->resource[3]->start : 0,
895 bus->resource[3] ? bus->resource[3]->end : 0);
896
897 if ((bus->number == 1) && (bus->resource[2] != NULL)) {
898 /* Hide PCI window 2 of Bus 1 which is used only to
899 * map legacy ISA memory space.
900 */
901 bus->resource[2]->start = 0;
902 bus->resource[2]->end = 0;
903 bus->resource[2]->flags = 0;
904 }
905 }
906
907 /*****************************************************************************
908 * Board device setup code
909 *****************************************************************************/
910
911 void __init ppc7d_setup_peripherals(void)
912 {
913 u32 val32;
914
915 /* Set up windows for boot CS */
916 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
917 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
918 0);
919 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
920
921 /* Boot firmware configures the following DevCS addresses.
922 * DevCS0 - board control/status
923 * DevCS1 - test registers
924 * DevCS2 - AFIX port/address registers (for identifying)
925 * DevCS3 - FLASH
926 *
927 * We don't use DevCS0, DevCS1.
928 */
929 val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
930 val32 |= ((1 << 4) | (1 << 5));
931 mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
932 mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
933 mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
934 mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
935 mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);
936
937 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
938 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
939 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
940
941 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
942 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
943 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
944
945 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
946 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
947 0);
948 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
949
950 /* Set up Enet->SRAM window */
951 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
952 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
953 0x2);
954 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
955
956 /* Give enet r/w access to memory region */
957 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
958 val32 |= (0x3 << (4 << 1));
959 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
960 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
961 val32 |= (0x3 << (4 << 1));
962 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
963 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
964 val32 |= (0x3 << (4 << 1));
965 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);
966
967 val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
968 val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
969 mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);
970
971 /* Enumerate pci bus.
972 *
973 * We scan PCI#0 first (the bus with the HB8 and other
974 * on-board peripherals). We must configure the 64360 before
975 * each scan, according to the bus number assignments. Busses
976 * are assigned incrementally, starting at 0. PCI#0 is
977 * usually assigned bus#0, the secondary side of the HB8 gets
978 * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if
979 * any PMC card has a PCI bridge, these bus assignments will
980 * change.
981 */
982
983 /* Turn off PCI retries */
984 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
985 val32 |= (1 << 17);
986 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
987
988 /* Scan PCI#0 */
989 mv64x60_set_bus(&bh, 0, 0);
990 bh.hose_a->first_busno = 0;
991 bh.hose_a->last_busno = 0xff;
992 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
993 printk(KERN_INFO "PCI#0: first=%d last=%d\n",
994 bh.hose_a->first_busno, bh.hose_a->last_busno);
995
996 /* Scan PCI#1 */
997 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
998 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
999 bh.hose_b->last_busno = 0xff;
1000 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
1001 bh.hose_b->first_busno);
1002 printk(KERN_INFO "PCI#1: first=%d last=%d\n",
1003 bh.hose_b->first_busno, bh.hose_b->last_busno);
1004
1005 /* Turn on PCI retries */
1006 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1007 val32 &= ~(1 << 17);
1008 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
1009
1010 /* Setup interrupts */
1011 ppc7d_intr_setup();
1012 }
1013
1014 static void __init ppc7d_setup_bridge(void)
1015 {
1016 struct mv64x60_setup_info si;
1017 int i;
1018 u32 temp;
1019
1020 mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */
1021
1022 memset(&si, 0, sizeof(si));
1023
1024 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
1025
1026 si.pci_0.enable_bus = 1;
1027 si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
1028 si.pci_0.pci_io.pci_base_hi = 0;
1029 si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
1030 si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
1031 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1032 si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
1033 si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
1034 si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1035 si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
1036 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1037 si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
1038 si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
1039 si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
1040 si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
1041 si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1042 si.pci_0.pci_cmd_bits = 0;
1043 si.pci_0.latency_timer = 0x80;
1044
1045 si.pci_1.enable_bus = 1;
1046 si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
1047 si.pci_1.pci_io.pci_base_hi = 0;
1048 si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
1049 si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
1050 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1051 si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
1052 si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
1053 si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1054 si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
1055 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1056 si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
1057 si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
1058 si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
1059 si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
1060 si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1061 si.pci_1.pci_cmd_bits = 0;
1062 si.pci_1.latency_timer = 0x80;
1063
1064 /* Don't clear the SRAM window since we use it for debug */
1065 si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);
1066
1067 printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
1068 si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
1069 printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
1070 si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);
1071
1072 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
1073 #if defined(CONFIG_NOT_COHERENT_CACHE)
1074 si.cpu_prot_options[i] = 0;
1075 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
1076 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
1077 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
1078
1079 si.pci_0.acc_cntl_options[i] =
1080 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1081 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1082 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1083 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1084
1085 si.pci_1.acc_cntl_options[i] =
1086 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1087 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1088 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1089 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1090 #else
1091 si.cpu_prot_options[i] = 0;
1092 /* All PPC7D hardware uses B0 or newer MV64360 silicon which
1093 * does not have snoop bugs.
1094 */
1095 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
1096 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
1097 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
1098
1099 si.pci_0.acc_cntl_options[i] =
1100 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1101 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1102 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1103 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1104
1105 si.pci_1.acc_cntl_options[i] =
1106 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1107 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1108 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1109 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1110 #endif
1111 }
1112
1113 /* Lookup PCI host bridges */
1114 if (mv64x60_init(&bh, &si))
1115 printk(KERN_ERR "MV64360 initialization failed.\n");
1116
1117 pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);
1118
1119 /* Enable WB Cache coherency on SRAM */
1120 temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
1121 pr_debug("SRAM_CONFIG: %x\n", temp);
1122 #if defined(CONFIG_NOT_COHERENT_CACHE)
1123 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
1124 #else
1125 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);
1126 #endif
1127 /* If system operates with internal bus arbiter (CPU master
1128 * control bit8) clear AACK Delay bit [25] in CPU
1129 * configuration register.
1130 */
1131 temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
1132 if (temp & (1 << 8)) {
1133 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1134 mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
1135 }
1136
1137 /* Data and address parity is enabled */
1138 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1139 mv64x60_write(&bh, MV64x60_CPU_CONFIG,
1140 (temp | (1 << 26) | (1 << 19)));
1141
1142 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
1143 ppc_md.pci_swizzle = common_swizzle;
1144 ppc_md.pci_map_irq = ppc7d_map_irq;
1145 ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;
1146
1147 mv64x60_set_bus(&bh, 0, 0);
1148 bh.hose_a->first_busno = 0;
1149 bh.hose_a->last_busno = 0xff;
1150 bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1151 bh.hose_a->mem_space.end =
1152 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;
1153
1154 /* These will be set later, as a result of PCI0 scan */
1155 bh.hose_b->first_busno = 0;
1156 bh.hose_b->last_busno = 0xff;
1157 bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1158 bh.hose_b->mem_space.end =
1159 PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;
1160
1161 pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
1162 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
1163 mv64x60_read(&bh, 0xf0));
1164 }
1165
1166 static void __init ppc7d_setup_arch(void)
1167 {
1168 int port;
1169
1170 loops_per_jiffy = 100000000 / HZ;
1171
1172 #ifdef CONFIG_BLK_DEV_INITRD
1173 if (initrd_start)
1174 ROOT_DEV = Root_RAM0;
1175 else
1176 #endif
1177 #ifdef CONFIG_ROOT_NFS
1178 ROOT_DEV = Root_NFS;
1179 #else
1180 ROOT_DEV = Root_HDA1;
1181 #endif
1182
1183 if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
1184 (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
1185 /* 745x is different. We only want to pass along enable. */
1186 _set_L2CR(L2CR_L2E);
1187 else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
1188 /* All modules have 1MB of L2. We also assume that an
1189 * L2 divisor of 3 will work.
1190 */
1191 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
1192 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
1193
1194 if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
1195 /* No L3 cache */
1196 _set_L3CR(0);
1197
1198 #ifdef CONFIG_DUMMY_CONSOLE
1199 conswitchp = &dummy_con;
1200 #endif
1201
1202 /* Lookup PCI host bridges */
1203 if (ppc_md.progress)
1204 ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);
1205
1206 ppc7d_setup_bridge();
1207 ppc7d_setup_peripherals();
1208
1209 /* Disable ethernet. It might have been setup by the bootrom */
1210 for (port = 0; port < 3; port++)
1211 mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
1212 0x0000ff00);
1213
1214 /* Clear queue pointers to ensure they are all initialized,
1215 * otherwise since queues 1-7 are unused, they have random
1216 * pointers which look strange in register dumps. Don't bother
1217 * with queue 0 since it will be initialized later.
1218 */
1219 for (port = 0; port < 3; port++) {
1220 mv64x60_write(&bh,
1221 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
1222 0x00000000);
1223 mv64x60_write(&bh,
1224 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
1225 0x00000000);
1226 mv64x60_write(&bh,
1227 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
1228 0x00000000);
1229 mv64x60_write(&bh,
1230 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
1231 0x00000000);
1232 mv64x60_write(&bh,
1233 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
1234 0x00000000);
1235 mv64x60_write(&bh,
1236 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
1237 0x00000000);
1238 mv64x60_write(&bh,
1239 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
1240 0x00000000);
1241 }
1242
1243 printk(KERN_INFO "Radstone Technology PPC7D\n");
1244 if (ppc_md.progress)
1245 ppc_md.progress("ppc7d_setup_arch: exit", 0);
1246
1247 }
1248
1249 /* Real Time Clock support.
1250 * PPC7D has a DS1337 accessed by I2C.
1251 */
1252 static ulong ppc7d_get_rtc_time(void)
1253 {
1254 struct rtc_time tm;
1255 int result;
1256
1257 spin_lock(&rtc_lock);
1258 result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
1259 spin_unlock(&rtc_lock);
1260
1261 if (result == 0)
1262 result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
1263
1264 return result;
1265 }
1266
1267 static int ppc7d_set_rtc_time(unsigned long nowtime)
1268 {
1269 struct rtc_time tm;
1270 int result;
1271
1272 spin_lock(&rtc_lock);
1273 to_tm(nowtime, &tm);
1274 result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
1275 spin_unlock(&rtc_lock);
1276
1277 return result;
1278 }
1279
1280 /* This kernel command line parameter can be used to have the target
1281 * wait for a JTAG debugger to attach. Of course, a JTAG debugger
1282 * with hardware breakpoint support can have the target stop at any
1283 * location during init, but this is a convenience feature that makes
1284 * it easier in the common case of loading the code using the ppcboot
1285 * bootloader..
1286 */
1287 static unsigned long ppc7d_wait_debugger;
1288
1289 static int __init ppc7d_waitdbg(char *str)
1290 {
1291 ppc7d_wait_debugger = 1;
1292 return 1;
1293 }
1294
1295 __setup("waitdbg", ppc7d_waitdbg);
1296
1297 /* Second phase board init, called after other (architecture common)
1298 * low-level services have been initialized.
1299 */
1300 static void ppc7d_init2(void)
1301 {
1302 unsigned long flags;
1303 u32 data;
1304 u8 data8;
1305
1306 pr_debug("%s: enter\n", __FUNCTION__);
1307
1308 /* Wait for debugger? */
1309 if (ppc7d_wait_debugger) {
1310 printk("Waiting for debugger...\n");
1311
1312 while (readl(&ppc7d_wait_debugger)) ;
1313 }
1314
1315 /* Hook up i8259 interrupt which is connected to GPP28 */
1316 request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
1317 SA_INTERRUPT, "I8259 (GPP28) interrupt", (void *)0);
1318
1319 /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
1320 spin_lock_irqsave(&mv64x60_lock, flags);
1321 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
1322 data &= ~(0x0000000f << 0);
1323 data |= (0x00000004 << 0);
1324 data &= ~(0x0000000f << 4);
1325 data |= (0x00000004 << 4);
1326 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
1327 spin_unlock_irqrestore(&mv64x60_lock, flags);
1328
1329 /* All LEDs off */
1330 data8 = inb(PPC7D_CPLD_LEDS);
1331 data8 &= ~0x08;
1332 data8 |= 0x07;
1333 outb(data8, PPC7D_CPLD_LEDS);
1334
1335 /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
1336 ppc_md.set_rtc_time = ppc7d_set_rtc_time;
1337 ppc_md.get_rtc_time = ppc7d_get_rtc_time;
1338
1339 pr_debug("%s: exit\n", __FUNCTION__);
1340 }
1341
1342 /* Called from machine_init(), early, before any of the __init functions
1343 * have run. We must init software-configurable pins before other functions
1344 * such as interrupt controllers are initialised.
1345 */
1346 void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
1347 unsigned long r6, unsigned long r7)
1348 {
1349 u8 val8;
1350 u8 rev_num;
1351
1352 /* Map 0xe0000000-0xffffffff early because we need access to SRAM
1353 * and the ISA memory space (for serial port) here. This mapping
1354 * is redone properly in ppc7d_map_io() later.
1355 */
1356 mtspr(SPRN_DBAT3U, 0xe0003fff);
1357 mtspr(SPRN_DBAT3L, 0xe000002a);
1358
1359 /*
1360 * Zero SRAM. Note that this generates parity errors on
1361 * internal data path in SRAM if it's first time accessing it
1362 * after reset.
1363 *
1364 * We do this ASAP to avoid parity errors when reading
1365 * uninitialized SRAM.
1366 */
1367 memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);
1368
1369 pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
1370 r3, r4, r5, r6, r7);
1371
1372 parse_bootinfo(find_bootinfo());
1373
1374 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
1375 * are non-zero, then we should use the board info from the bd_t
1376 * structure and the cmdline pointed to by r6 instead of the
1377 * information from birecs, if any. Otherwise, use the information
1378 * from birecs as discovered by the preceeding call to
1379 * parse_bootinfo(). This rule should work with both PPCBoot, which
1380 * uses a bd_t board info structure, and the kernel boot wrapper,
1381 * which uses birecs.
1382 */
1383 if (r3 && r6) {
1384 bd_t *bp = (bd_t *) __res;
1385
1386 /* copy board info structure */
1387 memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
1388 /* copy command line */
1389 *(char *)(r7 + KERNELBASE) = 0;
1390 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
1391
1392 printk(KERN_INFO "Board info data:-\n");
1393 printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n",
1394 bp->bi_intfreq, bp->bi_busfreq);
1395 printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart,
1396 bp->bi_memsize);
1397 printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate);
1398 printk(KERN_INFO " Ethernet address: "
1399 "%02x:%02x:%02x:%02x:%02x:%02x\n",
1400 bp->bi_enetaddr[0], bp->bi_enetaddr[1],
1401 bp->bi_enetaddr[2], bp->bi_enetaddr[3],
1402 bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
1403 }
1404 #ifdef CONFIG_BLK_DEV_INITRD
1405 /* take care of initrd if we have one */
1406 if (r4) {
1407 initrd_start = r4 + KERNELBASE;
1408 initrd_end = r5 + KERNELBASE;
1409 printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
1410 }
1411 #endif /* CONFIG_BLK_DEV_INITRD */
1412
1413 /* Map in board regs, etc. */
1414 isa_io_base = 0xe8000000;
1415 isa_mem_base = 0xe8000000;
1416 pci_dram_offset = 0x00000000;
1417 ISA_DMA_THRESHOLD = 0x00ffffff;
1418 DMA_MODE_READ = 0x44;
1419 DMA_MODE_WRITE = 0x48;
1420
1421 ppc_md.setup_arch = ppc7d_setup_arch;
1422 ppc_md.init = ppc7d_init2;
1423 ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
1424 /* XXX this is broken... */
1425 ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
1426 ppc_md.init_IRQ = ppc7d_init_irq;
1427 ppc_md.get_irq = ppc7d_get_irq;
1428
1429 ppc_md.restart = ppc7d_restart;
1430 ppc_md.power_off = ppc7d_power_off;
1431 ppc_md.halt = ppc7d_halt;
1432
1433 ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
1434 ppc_md.setup_io_mappings = ppc7d_map_io;
1435
1436 ppc_md.time_init = NULL;
1437 ppc_md.set_rtc_time = NULL;
1438 ppc_md.get_rtc_time = NULL;
1439 ppc_md.calibrate_decr = ppc7d_calibrate_decr;
1440 ppc_md.nvram_read_val = NULL;
1441 ppc_md.nvram_write_val = NULL;
1442
1443 ppc_md.heartbeat = ppc7d_heartbeat;
1444 ppc_md.heartbeat_reset = HZ;
1445 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
1446
1447 ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
1448
1449 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
1450 defined(CONFIG_I2C_MV64XXX)
1451 platform_notify = ppc7d_platform_notify;
1452 #endif
1453
1454 #ifdef CONFIG_SERIAL_MPSC
1455 /* On PPC7D, we must configure MPSC support via CPLD control
1456 * registers.
1457 */
1458 outb(PPC7D_CPLD_RTS_COM4_SCLK |
1459 PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
1460 outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
1461 PPC7D_CPLD_COMS_COM3_TXEN |
1462 PPC7D_CPLD_COMS_COM4_TCLKEN |
1463 PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
1464 #endif /* CONFIG_SERIAL_MPSC */
1465
1466 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
1467 ppc7d_early_serial_map();
1468 #ifdef CONFIG_SERIAL_TEXT_DEBUG
1469 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
1470 ppc_md.progress = mv64x60_mpsc_progress;
1471 #elif defined(CONFIG_SERIAL_8250)
1472 ppc_md.progress = gen550_progress;
1473 #else
1474 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
1475 #endif /* CONFIG_SERIAL_8250 */
1476 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
1477 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
1478
1479 /* Enable write access to user flash. This is necessary for
1480 * flash probe.
1481 */
1482 val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1483 writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
1484 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
1485 (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1486
1487 /* Determine if this board has IBM ALMA VME devices */
1488 val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
1489 rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
1490 if (rev_num <= 1)
1491 ppc7d_has_alma = 1;
1492
1493 #ifdef DEBUG
1494 console_printk[0] = 8;
1495 #endif
1496 }
linux kernel for loongson