arch/ppc/platforms/85xx/stx_gp3.c

   1 /*
   2  * arch/ppc/platforms/85xx/stx_gp3.c
   3  *
   4  * STx GP3 board specific routines
   5  *
   6  * Dan Malek <dan@embeddededge.com>
   7  * Copyright 2004 Embedded Edge, LLC
   8  *
   9  * Copied from mpc8560_ads.c
  10  * Copyright 2002, 2003 Motorola Inc.
  11  *
  12  * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
  13  * Copyright 2004-2005 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  */
  20
  21 #include <linux/config.h>
  22 #include <linux/stddef.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/errno.h>
  26 #include <linux/reboot.h>
  27 #include <linux/pci.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/major.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/console.h>
  32 #include <linux/delay.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/serial.h>
  36 #include <linux/initrd.h>
  37 #include <linux/module.h>
  38 #include <linux/fsl_devices.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/rio.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/page.h>
  45 #include <asm/atomic.h>
  46 #include <asm/time.h>
  47 #include <asm/io.h>
  48 #include <asm/machdep.h>
  49 #include <asm/open_pic.h>
  50 #include <asm/bootinfo.h>
  51 #include <asm/pci-bridge.h>
  52 #include <asm/mpc85xx.h>
  53 #include <asm/irq.h>
  54 #include <asm/immap_85xx.h>
  55 #include <asm/cpm2.h>
  56 #include <asm/mpc85xx.h>
  57 #include <asm/ppc_sys.h>
  58
  59 #include <syslib/cpm2_pic.h>
  60 #include <syslib/ppc85xx_common.h>
  61 #include <syslib/ppc85xx_rio.h>
  62
  63
  64 unsigned char __res[sizeof(bd_t)];
  65
  66 #ifndef CONFIG_PCI
  67 unsigned long isa_io_base = 0;
  68 unsigned long isa_mem_base = 0;
  69 unsigned long pci_dram_offset = 0;
  70 #endif
  71
  72 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  73 static u8 gp3_openpic_initsenses[] __initdata = {
  74         MPC85XX_INTERNAL_IRQ_SENSES,
  75         0x0,                                            /* External  0: */
  76 #if defined(CONFIG_PCI)
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
  81 #else
  82         0x0,                            /* External  1: */
  83         0x0,                            /* External  2: */
  84         0x0,                            /* External  3: */
  85         0x0,                            /* External  4: */
  86 #endif
  87         0x0,                            /* External  5: */
  88         0x0,                            /* External  6: */
  89         0x0,                            /* External  7: */
  90         0x0,                            /* External  8: */
  91         0x0,                            /* External  9: */
  92         0x0,                            /* External 10: */
  93         0x0,                            /* External 11: */
  94 };
  95
  96 /*
  97  * Setup the architecture
  98  */
  99 static void __init
 100 gp3_setup_arch(void)
 101 {
 102         bd_t *binfo = (bd_t *) __res;
 103         unsigned int freq;
 104         struct gianfar_platform_data *pdata;
 105         struct gianfar_mdio_data *mdata;
 106
 107         cpm2_reset();
 108
 109         /* get the core frequency */
 110         freq = binfo->bi_intfreq;
 111
 112         if (ppc_md.progress)
 113                 ppc_md.progress("gp3_setup_arch()", 0);
 114
 115         /* Set loops_per_jiffy to a half-way reasonable value,
 116            for use until calibrate_delay gets called. */
 117         loops_per_jiffy = freq / HZ;
 118
 119 #ifdef CONFIG_PCI
 120         /* setup PCI host bridges */
 121         mpc85xx_setup_hose();
 122 #endif
 123
 124         /* setup the board related info for the MDIO bus */
 125         mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
 126
 127         mdata->irq[2] = MPC85xx_IRQ_EXT5;
 128         mdata->irq[4] = MPC85xx_IRQ_EXT5;
 129         mdata->irq[31] = -1;
 130
 131         /* setup the board related information for the enet controllers */
 132         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 133         if (pdata) {
 134         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 135                 pdata->bus_id = 0;
 136                 pdata->phy_id = 2;
 137                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 138         }
 139
 140         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 141         if (pdata) {
 142         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 143                 pdata->bus_id = 0;
 144                 pdata->phy_id = 4;
 145                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 146         }
 147
 148 #ifdef CONFIG_BLK_DEV_INITRD
 149         if (initrd_start)
 150                 ROOT_DEV = Root_RAM0;
 151         else
 152 #endif
 153 #ifdef  CONFIG_ROOT_NFS
 154                 ROOT_DEV = Root_NFS;
 155 #else
 156                 ROOT_DEV = Root_HDA1;
 157 #endif
 158
 159         printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
 160 }
 161
 162 static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
 163 {
 164         while ((irq = cpm2_get_irq(regs)) >= 0)
 165                 __do_IRQ(irq, regs);
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 static struct irqaction cpm2_irqaction = {
 171         .handler        = cpm2_cascade,
 172         .flags          = SA_INTERRUPT,
 173         .mask           = CPU_MASK_NONE,
 174         .name           = "cpm2_cascade",
 175 };
 176
 177 static void __init
 178 gp3_init_IRQ(void)
 179 {
 180         bd_t *binfo = (bd_t *) __res;
 181
 182         /*
 183          * Setup OpenPIC
 184          */
 185
 186         /* Determine the Physical Address of the OpenPIC regs */
 187         phys_addr_t OpenPIC_PAddr =
 188             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 189         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 190         OpenPIC_InitSenses = gp3_openpic_initsenses;
 191         OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
 192
 193         /* Skip reserved space and internal sources */
 194         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 195
 196         /* Map PIC IRQs 0-11 */
 197         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 198
 199         /*
 200          * Let openpic interrupts starting from an offset, to
 201          * leave space for cascading interrupts underneath.
 202          */
 203         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 204
 205         /* Setup CPM2 PIC */
 206         cpm2_init_IRQ();
 207
 208         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 209
 210         return;
 211 }
 212
 213 static int
 214 gp3_show_cpuinfo(struct seq_file *m)
 215 {
 216         uint pvid, svid, phid1;
 217         bd_t *binfo = (bd_t *) __res;
 218         uint    memsize;
 219         unsigned int freq;
 220         extern unsigned long total_memory;      /* in mm/init */
 221
 222         /* get the core frequency */
 223         freq = binfo->bi_intfreq;
 224
 225         pvid = mfspr(SPRN_PVR);
 226         svid = mfspr(SPRN_SVR);
 227
 228         memsize = total_memory;
 229
 230         seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
 231         seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
 232         seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
 233                    freq % 1000000);
 234         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 235         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 236
 237         /* Display cpu Pll setting */
 238         phid1 = mfspr(SPRN_HID1);
 239         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 240
 241         /* Display the amount of memory */
 242         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 243
 244         return 0;
 245 }
 246
 247 #ifdef CONFIG_PCI
 248 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 249                     unsigned char pin)
 250 {
 251         static char pci_irq_table[][4] =
 252             /*
 253              *      PCI IDSEL/INTPIN->INTLINE
 254              *        A      B      C      D
 255              */
 256         {
 257                 {PIRQA, PIRQB, PIRQC, PIRQD},
 258                 {PIRQD, PIRQA, PIRQB, PIRQC},
 259                 {PIRQC, PIRQD, PIRQA, PIRQB},
 260                 {PIRQB, PIRQC, PIRQD, PIRQA},
 261         };
 262
 263         const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
 264         return PCI_IRQ_TABLE_LOOKUP;
 265 }
 266
 267 int mpc85xx_exclude_device(u_char bus, u_char devfn)
 268 {
 269         if (bus == 0 && PCI_SLOT(devfn) == 0)
 270                 return PCIBIOS_DEVICE_NOT_FOUND;
 271         else
 272                 return PCIBIOS_SUCCESSFUL;
 273 }
 274 #endif /* CONFIG_PCI */
 275
 276 #ifdef CONFIG_RAPIDIO
 277 void
 278 platform_rio_init(void)
 279 {
 280         /*
 281          * The STx firmware configures the RapidIO Local Access Window
 282          * at 0xc0000000 with a size of 512MB.
 283          */
 284         mpc85xx_rio_setup(0xc0000000, 0x20000000);
 285 }
 286 #endif /* CONFIG_RAPIDIO */
 287
 288 void __init
 289 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 290               unsigned long r6, unsigned long r7)
 291 {
 292         /* parse_bootinfo must always be called first */
 293         parse_bootinfo(find_bootinfo());
 294
 295         /*
 296          * If we were passed in a board information, copy it into the
 297          * residual data area.
 298          */
 299         if (r3) {
 300                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 301                        sizeof (bd_t));
 302
 303         }
 304 #if defined(CONFIG_BLK_DEV_INITRD)
 305         /*
 306          * If the init RAM disk has been configured in, and there's a valid
 307          * starting address for it, set it up.
 308          */
 309         if (r4) {
 310                 initrd_start = r4 + KERNELBASE;
 311                 initrd_end = r5 + KERNELBASE;
 312         }
 313 #endif                          /* CONFIG_BLK_DEV_INITRD */
 314
 315         /* Copy the kernel command line arguments to a safe place. */
 316
 317         if (r6) {
 318                 *(char *) (r7 + KERNELBASE) = 0;
 319                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 320         }
 321
 322         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 323
 324         /* setup the PowerPC module struct */
 325         ppc_md.setup_arch = gp3_setup_arch;
 326         ppc_md.show_cpuinfo = gp3_show_cpuinfo;
 327
 328         ppc_md.init_IRQ = gp3_init_IRQ;
 329         ppc_md.get_irq = openpic_get_irq;
 330
 331         ppc_md.restart = mpc85xx_restart;
 332         ppc_md.power_off = mpc85xx_power_off;
 333         ppc_md.halt = mpc85xx_halt;
 334
 335         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 336
 337         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 338
 339         if (ppc_md.progress)
 340                 ppc_md.progress("platform_init(): exit", 0);
 341
 342         return;
 343 }