2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
31 #include "radeon_drm.h"
32 #include "radeon_drv.h"
34 #include "r600_microcode.h"
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
39 #define R600_PTE_VALID (1 << 0)
40 #define R600_PTE_SYSTEM (1 << 1)
41 #define R600_PTE_SNOOPED (1 << 2)
42 #define R600_PTE_READABLE (1 << 5)
43 #define R600_PTE_WRITEABLE (1 << 6)
45 /* MAX values used for gfx init */
46 #define R6XX_MAX_SH_GPRS 256
47 #define R6XX_MAX_TEMP_GPRS 16
48 #define R6XX_MAX_SH_THREADS 256
49 #define R6XX_MAX_SH_STACK_ENTRIES 4096
50 #define R6XX_MAX_BACKENDS 8
51 #define R6XX_MAX_BACKENDS_MASK 0xff
52 #define R6XX_MAX_SIMDS 8
53 #define R6XX_MAX_SIMDS_MASK 0xff
54 #define R6XX_MAX_PIPES 8
55 #define R6XX_MAX_PIPES_MASK 0xff
57 #define R7XX_MAX_SH_GPRS 256
58 #define R7XX_MAX_TEMP_GPRS 16
59 #define R7XX_MAX_SH_THREADS 256
60 #define R7XX_MAX_SH_STACK_ENTRIES 4096
61 #define R7XX_MAX_BACKENDS 8
62 #define R7XX_MAX_BACKENDS_MASK 0xff
63 #define R7XX_MAX_SIMDS 16
64 #define R7XX_MAX_SIMDS_MASK 0xffff
65 #define R7XX_MAX_PIPES 8
66 #define R7XX_MAX_PIPES_MASK 0xff
68 static int r600_do_wait_for_fifo(drm_radeon_private_t
*dev_priv
, int entries
)
72 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
74 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
76 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
77 slots
= (RADEON_READ(R600_GRBM_STATUS
)
78 & R700_CMDFIFO_AVAIL_MASK
);
80 slots
= (RADEON_READ(R600_GRBM_STATUS
)
81 & R600_CMDFIFO_AVAIL_MASK
);
86 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
87 RADEON_READ(R600_GRBM_STATUS
),
88 RADEON_READ(R600_GRBM_STATUS2
));
93 static int r600_do_wait_for_idle(drm_radeon_private_t
*dev_priv
)
97 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
99 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
100 ret
= r600_do_wait_for_fifo(dev_priv
, 8);
102 ret
= r600_do_wait_for_fifo(dev_priv
, 16);
105 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
106 if (!(RADEON_READ(R600_GRBM_STATUS
) & R600_GUI_ACTIVE
))
110 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
111 RADEON_READ(R600_GRBM_STATUS
),
112 RADEON_READ(R600_GRBM_STATUS2
));
117 void r600_page_table_cleanup(struct drm_device
*dev
, struct drm_ati_pcigart_info
*gart_info
)
119 struct drm_sg_mem
*entry
= dev
->sg
;
124 if (gart_info
->bus_addr
) {
125 max_pages
= (gart_info
->table_size
/ sizeof(u32
));
126 pages
= (entry
->pages
<= max_pages
)
127 ? entry
->pages
: max_pages
;
129 for (i
= 0; i
< pages
; i
++) {
130 if (!entry
->busaddr
[i
])
132 pci_unmap_single(dev
->pdev
, entry
->busaddr
[i
],
133 PAGE_SIZE
, PCI_DMA_TODEVICE
);
135 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
)
136 gart_info
->bus_addr
= 0;
140 /* R600 has page table setup */
141 int r600_page_table_init(struct drm_device
*dev
)
143 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
144 struct drm_ati_pcigart_info
*gart_info
= &dev_priv
->gart_info
;
145 struct drm_local_map
*map
= &gart_info
->mapping
;
146 struct drm_sg_mem
*entry
= dev
->sg
;
151 dma_addr_t entry_addr
;
152 int max_ati_pages
, max_real_pages
, gart_idx
;
154 /* okay page table is available - lets rock */
155 max_ati_pages
= (gart_info
->table_size
/ sizeof(u64
));
156 max_real_pages
= max_ati_pages
/ (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
);
158 pages
= (entry
->pages
<= max_real_pages
) ?
159 entry
->pages
: max_real_pages
;
161 memset_io((void __iomem
*)map
->handle
, 0, max_ati_pages
* sizeof(u64
));
164 for (i
= 0; i
< pages
; i
++) {
165 entry
->busaddr
[i
] = pci_map_single(dev
->pdev
,
168 PAGE_SIZE
, PCI_DMA_TODEVICE
);
169 if (entry
->busaddr
[i
] == 0) {
170 DRM_ERROR("unable to map PCIGART pages!\n");
171 r600_page_table_cleanup(dev
, gart_info
);
175 entry_addr
= entry
->busaddr
[i
];
176 for (j
= 0; j
< (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
); j
++) {
177 page_base
= (u64
) entry_addr
& ATI_PCIGART_PAGE_MASK
;
178 page_base
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
179 page_base
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
181 DRM_WRITE64(map
, gart_idx
* sizeof(u64
), page_base
);
186 DRM_DEBUG("page entry %d: 0x%016llx\n",
187 i
, (unsigned long long)page_base
);
188 entry_addr
+= ATI_PCIGART_PAGE_SIZE
;
195 static void r600_vm_flush_gart_range(struct drm_device
*dev
)
197 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
198 u32 resp
, countdown
= 1000;
199 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
200 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
201 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE
, 2);
204 resp
= RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE
);
207 } while (((resp
& 0xf0) == 0) && countdown
);
210 static void r600_vm_init(struct drm_device
*dev
)
212 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
213 /* initialise the VM to use the page table we constructed up there */
216 u32 vm_l2_cntl
, vm_l2_cntl3
;
217 /* okay set up the PCIE aperture type thingo */
218 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
219 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
220 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
223 mc_rd_a
= R600_MCD_L1_TLB
| R600_MCD_L1_FRAG_PROC
| R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS
|
224 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
| R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
225 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY
;
227 RADEON_WRITE(R600_MCD_RD_A_CNTL
, mc_rd_a
);
228 RADEON_WRITE(R600_MCD_RD_B_CNTL
, mc_rd_a
);
230 RADEON_WRITE(R600_MCD_WR_A_CNTL
, mc_rd_a
);
231 RADEON_WRITE(R600_MCD_WR_B_CNTL
, mc_rd_a
);
233 RADEON_WRITE(R600_MCD_RD_GFX_CNTL
, mc_rd_a
);
234 RADEON_WRITE(R600_MCD_WR_GFX_CNTL
, mc_rd_a
);
236 RADEON_WRITE(R600_MCD_RD_SYS_CNTL
, mc_rd_a
);
237 RADEON_WRITE(R600_MCD_WR_SYS_CNTL
, mc_rd_a
);
239 RADEON_WRITE(R600_MCD_RD_HDP_CNTL
, mc_rd_a
| R600_MCD_L1_STRICT_ORDERING
);
240 RADEON_WRITE(R600_MCD_WR_HDP_CNTL
, mc_rd_a
/*| R600_MCD_L1_STRICT_ORDERING*/);
242 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL
, mc_rd_a
);
243 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL
, mc_rd_a
);
245 RADEON_WRITE(R600_MCD_RD_SEM_CNTL
, mc_rd_a
| R600_MCD_SEMAPHORE_MODE
);
246 RADEON_WRITE(R600_MCD_WR_SEM_CNTL
, mc_rd_a
);
248 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
249 vm_l2_cntl
|= R600_VM_L2_CNTL_QUEUE_SIZE(7);
250 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
252 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
253 vm_l2_cntl3
= (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
254 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
255 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
256 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
258 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
260 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
262 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
264 /* disable all other contexts */
265 for (i
= 1; i
< 8; i
++)
266 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
268 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
269 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
270 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
272 r600_vm_flush_gart_range(dev
);
275 /* load r600 microcode */
276 static void r600_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
280 r600_do_cp_stop(dev_priv
);
282 RADEON_WRITE(R600_CP_RB_CNTL
,
287 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
288 RADEON_READ(R600_GRBM_SOFT_RESET
);
290 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
292 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
294 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
)) {
295 DRM_INFO("Loading R600 CP Microcode\n");
296 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
297 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
298 R600_cp_microcode
[i
][0]);
299 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
300 R600_cp_microcode
[i
][1]);
301 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
302 R600_cp_microcode
[i
][2]);
305 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
306 DRM_INFO("Loading R600 PFP Microcode\n");
307 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
308 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, R600_pfp_microcode
[i
]);
309 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
)) {
310 DRM_INFO("Loading RV610 CP Microcode\n");
311 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
312 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
313 RV610_cp_microcode
[i
][0]);
314 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
315 RV610_cp_microcode
[i
][1]);
316 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
317 RV610_cp_microcode
[i
][2]);
320 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
321 DRM_INFO("Loading RV610 PFP Microcode\n");
322 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
323 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV610_pfp_microcode
[i
]);
324 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
)) {
325 DRM_INFO("Loading RV630 CP Microcode\n");
326 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
327 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
328 RV630_cp_microcode
[i
][0]);
329 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
330 RV630_cp_microcode
[i
][1]);
331 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
332 RV630_cp_microcode
[i
][2]);
335 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
336 DRM_INFO("Loading RV630 PFP Microcode\n");
337 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
338 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV630_pfp_microcode
[i
]);
339 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
)) {
340 DRM_INFO("Loading RV620 CP Microcode\n");
341 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
342 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
343 RV620_cp_microcode
[i
][0]);
344 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
345 RV620_cp_microcode
[i
][1]);
346 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
347 RV620_cp_microcode
[i
][2]);
350 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
351 DRM_INFO("Loading RV620 PFP Microcode\n");
352 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
353 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV620_pfp_microcode
[i
]);
354 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV635
)) {
355 DRM_INFO("Loading RV635 CP Microcode\n");
356 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
357 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
358 RV635_cp_microcode
[i
][0]);
359 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
360 RV635_cp_microcode
[i
][1]);
361 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
362 RV635_cp_microcode
[i
][2]);
365 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
366 DRM_INFO("Loading RV635 PFP Microcode\n");
367 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
368 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV635_pfp_microcode
[i
]);
369 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
)) {
370 DRM_INFO("Loading RV670 CP Microcode\n");
371 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
372 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
373 RV670_cp_microcode
[i
][0]);
374 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
375 RV670_cp_microcode
[i
][1]);
376 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
377 RV670_cp_microcode
[i
][2]);
380 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
381 DRM_INFO("Loading RV670 PFP Microcode\n");
382 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
383 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV670_pfp_microcode
[i
]);
384 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
)) {
385 DRM_INFO("Loading RS780 CP Microcode\n");
386 for (i
= 0; i
< PM4_UCODE_SIZE
; i
++) {
387 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
388 RV670_cp_microcode
[i
][0]);
389 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
390 RV670_cp_microcode
[i
][1]);
391 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
392 RV670_cp_microcode
[i
][2]);
395 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
396 DRM_INFO("Loading RS780 PFP Microcode\n");
397 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
398 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV670_pfp_microcode
[i
]);
400 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
401 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
402 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
406 static void r700_vm_init(struct drm_device
*dev
)
408 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
409 /* initialise the VM to use the page table we constructed up there */
412 u32 vm_l2_cntl
, vm_l2_cntl3
;
413 /* okay set up the PCIE aperture type thingo */
414 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
415 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
416 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
418 mc_vm_md_l1
= R700_ENABLE_L1_TLB
|
419 R700_ENABLE_L1_FRAGMENT_PROCESSING
|
420 R700_SYSTEM_ACCESS_MODE_IN_SYS
|
421 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
422 R700_EFFECTIVE_L1_TLB_SIZE(5) |
423 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
425 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL
, mc_vm_md_l1
);
426 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL
, mc_vm_md_l1
);
427 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL
, mc_vm_md_l1
);
428 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL
, mc_vm_md_l1
);
429 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL
, mc_vm_md_l1
);
430 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL
, mc_vm_md_l1
);
431 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL
, mc_vm_md_l1
);
433 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
434 vm_l2_cntl
|= R700_VM_L2_CNTL_QUEUE_SIZE(7);
435 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
437 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
438 vm_l2_cntl3
= R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
439 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
441 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
443 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
445 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
447 /* disable all other contexts */
448 for (i
= 1; i
< 8; i
++)
449 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
451 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
452 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
453 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
455 r600_vm_flush_gart_range(dev
);
458 /* load r600 microcode */
459 static void r700_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
463 r600_do_cp_stop(dev_priv
);
465 RADEON_WRITE(R600_CP_RB_CNTL
,
470 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
471 RADEON_READ(R600_GRBM_SOFT_RESET
);
473 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
476 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV770
)) {
477 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
478 DRM_INFO("Loading RV770 PFP Microcode\n");
479 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
480 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV770_pfp_microcode
[i
]);
481 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
483 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
484 DRM_INFO("Loading RV770 CP Microcode\n");
485 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
486 RADEON_WRITE(R600_CP_ME_RAM_DATA
, RV770_cp_microcode
[i
]);
487 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
489 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV730
)) {
490 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
491 DRM_INFO("Loading RV730 PFP Microcode\n");
492 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
493 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV730_pfp_microcode
[i
]);
494 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
496 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
497 DRM_INFO("Loading RV730 CP Microcode\n");
498 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
499 RADEON_WRITE(R600_CP_ME_RAM_DATA
, RV730_cp_microcode
[i
]);
500 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
502 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)) {
503 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
504 DRM_INFO("Loading RV710 PFP Microcode\n");
505 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
506 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, RV710_pfp_microcode
[i
]);
507 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
509 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
510 DRM_INFO("Loading RV710 CP Microcode\n");
511 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
512 RADEON_WRITE(R600_CP_ME_RAM_DATA
, RV710_cp_microcode
[i
]);
513 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
516 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
517 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
518 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
522 static void r600_test_writeback(drm_radeon_private_t
*dev_priv
)
526 /* Start with assuming that writeback doesn't work */
527 dev_priv
->writeback_works
= 0;
529 /* Writeback doesn't seem to work everywhere, test it here and possibly
530 * enable it if it appears to work
532 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
534 RADEON_WRITE(R600_SCRATCH_REG1
, 0xdeadbeef);
536 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
539 val
= radeon_read_ring_rptr(dev_priv
, R600_SCRATCHOFF(1));
540 if (val
== 0xdeadbeef)
545 if (tmp
< dev_priv
->usec_timeout
) {
546 dev_priv
->writeback_works
= 1;
547 DRM_INFO("writeback test succeeded in %d usecs\n", tmp
);
549 dev_priv
->writeback_works
= 0;
550 DRM_INFO("writeback test failed\n");
552 if (radeon_no_wb
== 1) {
553 dev_priv
->writeback_works
= 0;
554 DRM_INFO("writeback forced off\n");
557 if (!dev_priv
->writeback_works
) {
558 /* Disable writeback to avoid unnecessary bus master transfer */
559 RADEON_WRITE(R600_CP_RB_CNTL
, RADEON_READ(R600_CP_RB_CNTL
) |
560 RADEON_RB_NO_UPDATE
);
561 RADEON_WRITE(R600_SCRATCH_UMSK
, 0);
565 int r600_do_engine_reset(struct drm_device
*dev
)
567 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
568 u32 cp_ptr
, cp_me_cntl
, cp_rb_cntl
;
570 DRM_INFO("Resetting GPU\n");
572 cp_ptr
= RADEON_READ(R600_CP_RB_WPTR
);
573 cp_me_cntl
= RADEON_READ(R600_CP_ME_CNTL
);
574 RADEON_WRITE(R600_CP_ME_CNTL
, R600_CP_ME_HALT
);
576 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0x7fff);
577 RADEON_READ(R600_GRBM_SOFT_RESET
);
579 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
580 RADEON_READ(R600_GRBM_SOFT_RESET
);
582 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
583 cp_rb_cntl
= RADEON_READ(R600_CP_RB_CNTL
);
584 RADEON_WRITE(R600_CP_RB_CNTL
, R600_RB_RPTR_WR_ENA
);
586 RADEON_WRITE(R600_CP_RB_RPTR_WR
, cp_ptr
);
587 RADEON_WRITE(R600_CP_RB_WPTR
, cp_ptr
);
588 RADEON_WRITE(R600_CP_RB_CNTL
, cp_rb_cntl
);
589 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me_cntl
);
591 /* Reset the CP ring */
592 r600_do_cp_reset(dev_priv
);
594 /* The CP is no longer running after an engine reset */
595 dev_priv
->cp_running
= 0;
597 /* Reset any pending vertex, indirect buffers */
598 radeon_freelist_reset(dev
);
604 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
606 u32 backend_disable_mask
)
609 u32 enabled_backends_mask
;
610 u32 enabled_backends_count
;
612 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
616 if (num_tile_pipes
> R6XX_MAX_PIPES
)
617 num_tile_pipes
= R6XX_MAX_PIPES
;
618 if (num_tile_pipes
< 1)
620 if (num_backends
> R6XX_MAX_BACKENDS
)
621 num_backends
= R6XX_MAX_BACKENDS
;
622 if (num_backends
< 1)
625 enabled_backends_mask
= 0;
626 enabled_backends_count
= 0;
627 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
628 if (((backend_disable_mask
>> i
) & 1) == 0) {
629 enabled_backends_mask
|= (1 << i
);
630 ++enabled_backends_count
;
632 if (enabled_backends_count
== num_backends
)
636 if (enabled_backends_count
== 0) {
637 enabled_backends_mask
= 1;
638 enabled_backends_count
= 1;
641 if (enabled_backends_count
!= num_backends
)
642 num_backends
= enabled_backends_count
;
644 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
645 switch (num_tile_pipes
) {
701 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
702 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
703 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
705 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
707 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
713 static int r600_count_pipe_bits(uint32_t val
)
716 for (i
= 0; i
< 32; i
++) {
723 static void r600_gfx_init(struct drm_device
*dev
,
724 drm_radeon_private_t
*dev_priv
)
726 int i
, j
, num_qd_pipes
;
730 u32 num_gs_verts_per_thread
;
732 u32 gs_prim_buffer_depth
= 0;
733 u32 sq_ms_fifo_sizes
;
735 u32 sq_gpr_resource_mgmt_1
= 0;
736 u32 sq_gpr_resource_mgmt_2
= 0;
737 u32 sq_thread_resource_mgmt
= 0;
738 u32 sq_stack_resource_mgmt_1
= 0;
739 u32 sq_stack_resource_mgmt_2
= 0;
740 u32 hdp_host_path_cntl
;
742 u32 gb_tiling_config
= 0;
743 u32 cc_rb_backend_disable
= 0;
744 u32 cc_gc_shader_pipe_config
= 0;
747 /* setup chip specs */
748 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
750 dev_priv
->r600_max_pipes
= 4;
751 dev_priv
->r600_max_tile_pipes
= 8;
752 dev_priv
->r600_max_simds
= 4;
753 dev_priv
->r600_max_backends
= 4;
754 dev_priv
->r600_max_gprs
= 256;
755 dev_priv
->r600_max_threads
= 192;
756 dev_priv
->r600_max_stack_entries
= 256;
757 dev_priv
->r600_max_hw_contexts
= 8;
758 dev_priv
->r600_max_gs_threads
= 16;
759 dev_priv
->r600_sx_max_export_size
= 128;
760 dev_priv
->r600_sx_max_export_pos_size
= 16;
761 dev_priv
->r600_sx_max_export_smx_size
= 128;
762 dev_priv
->r600_sq_num_cf_insts
= 2;
766 dev_priv
->r600_max_pipes
= 2;
767 dev_priv
->r600_max_tile_pipes
= 2;
768 dev_priv
->r600_max_simds
= 3;
769 dev_priv
->r600_max_backends
= 1;
770 dev_priv
->r600_max_gprs
= 128;
771 dev_priv
->r600_max_threads
= 192;
772 dev_priv
->r600_max_stack_entries
= 128;
773 dev_priv
->r600_max_hw_contexts
= 8;
774 dev_priv
->r600_max_gs_threads
= 4;
775 dev_priv
->r600_sx_max_export_size
= 128;
776 dev_priv
->r600_sx_max_export_pos_size
= 16;
777 dev_priv
->r600_sx_max_export_smx_size
= 128;
778 dev_priv
->r600_sq_num_cf_insts
= 2;
783 dev_priv
->r600_max_pipes
= 1;
784 dev_priv
->r600_max_tile_pipes
= 1;
785 dev_priv
->r600_max_simds
= 2;
786 dev_priv
->r600_max_backends
= 1;
787 dev_priv
->r600_max_gprs
= 128;
788 dev_priv
->r600_max_threads
= 192;
789 dev_priv
->r600_max_stack_entries
= 128;
790 dev_priv
->r600_max_hw_contexts
= 4;
791 dev_priv
->r600_max_gs_threads
= 4;
792 dev_priv
->r600_sx_max_export_size
= 128;
793 dev_priv
->r600_sx_max_export_pos_size
= 16;
794 dev_priv
->r600_sx_max_export_smx_size
= 128;
795 dev_priv
->r600_sq_num_cf_insts
= 1;
798 dev_priv
->r600_max_pipes
= 4;
799 dev_priv
->r600_max_tile_pipes
= 4;
800 dev_priv
->r600_max_simds
= 4;
801 dev_priv
->r600_max_backends
= 4;
802 dev_priv
->r600_max_gprs
= 192;
803 dev_priv
->r600_max_threads
= 192;
804 dev_priv
->r600_max_stack_entries
= 256;
805 dev_priv
->r600_max_hw_contexts
= 8;
806 dev_priv
->r600_max_gs_threads
= 16;
807 dev_priv
->r600_sx_max_export_size
= 128;
808 dev_priv
->r600_sx_max_export_pos_size
= 16;
809 dev_priv
->r600_sx_max_export_smx_size
= 128;
810 dev_priv
->r600_sq_num_cf_insts
= 2;
818 for (i
= 0; i
< 32; i
++) {
819 RADEON_WRITE((0x2c14 + j
), 0x00000000);
820 RADEON_WRITE((0x2c18 + j
), 0x00000000);
821 RADEON_WRITE((0x2c1c + j
), 0x00000000);
822 RADEON_WRITE((0x2c20 + j
), 0x00000000);
823 RADEON_WRITE((0x2c24 + j
), 0x00000000);
827 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
829 /* setup tiling, simd, pipe config */
830 ramcfg
= RADEON_READ(R600_RAMCFG
);
832 switch (dev_priv
->r600_max_tile_pipes
) {
834 gb_tiling_config
|= R600_PIPE_TILING(0);
837 gb_tiling_config
|= R600_PIPE_TILING(1);
840 gb_tiling_config
|= R600_PIPE_TILING(2);
843 gb_tiling_config
|= R600_PIPE_TILING(3);
849 gb_tiling_config
|= R600_BANK_TILING((ramcfg
>> R600_NOOFBANK_SHIFT
) & R600_NOOFBANK_MASK
);
851 gb_tiling_config
|= R600_GROUP_SIZE(0);
853 if (((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
) > 3) {
854 gb_tiling_config
|= R600_ROW_TILING(3);
855 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
858 R600_ROW_TILING(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
860 R600_SAMPLE_SPLIT(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
863 gb_tiling_config
|= R600_BANK_SWAPS(1);
865 backend_map
= r600_get_tile_pipe_to_backend_map(dev_priv
->r600_max_tile_pipes
,
866 dev_priv
->r600_max_backends
,
867 (0xff << dev_priv
->r600_max_backends
) & 0xff);
868 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
870 cc_gc_shader_pipe_config
=
871 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R6XX_MAX_PIPES_MASK
);
872 cc_gc_shader_pipe_config
|=
873 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R6XX_MAX_SIMDS_MASK
);
875 cc_rb_backend_disable
=
876 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R6XX_MAX_BACKENDS_MASK
);
878 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
879 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
880 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
882 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
883 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
884 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
887 R6XX_MAX_BACKENDS
- r600_count_pipe_bits(cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
);
888 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
889 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
891 /* set HW defaults for 3D engine */
892 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
893 R600_ROQ_IB2_START(0x2b)));
895 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, (R600_MEQ_END(0x40) |
896 R600_ROQ_END(0x40)));
898 RADEON_WRITE(R600_TA_CNTL_AUX
, (R600_DISABLE_CUBE_ANISO
|
903 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
)
904 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL
, 0x00000021);
906 sx_debug_1
= RADEON_READ(R600_SX_DEBUG_1
);
907 sx_debug_1
|= R600_SMX_EVENT_RELEASE
;
908 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_R600
))
909 sx_debug_1
|= R600_ENABLE_NEW_SMX_ADDRESS
;
910 RADEON_WRITE(R600_SX_DEBUG_1
, sx_debug_1
);
912 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
913 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
914 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
915 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
916 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
))
917 RADEON_WRITE(R600_DB_DEBUG
, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
919 RADEON_WRITE(R600_DB_DEBUG
, 0);
921 RADEON_WRITE(R600_DB_WATERMARKS
, (R600_DEPTH_FREE(4) |
922 R600_DEPTH_FLUSH(16) |
923 R600_DEPTH_PENDING_FREE(4) |
924 R600_DEPTH_CACHELINE_FREE(16)));
925 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
926 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 0);
928 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
929 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(0));
931 sq_ms_fifo_sizes
= RADEON_READ(R600_SQ_MS_FIFO_SIZES
);
932 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
933 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
934 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
)) {
935 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(0xa) |
936 R600_FETCH_FIFO_HIWATER(0xa) |
937 R600_DONE_FIFO_HIWATER(0xe0) |
938 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
939 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
940 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
)) {
941 sq_ms_fifo_sizes
&= ~R600_DONE_FIFO_HIWATER(0xff);
942 sq_ms_fifo_sizes
|= R600_DONE_FIFO_HIWATER(0x4);
944 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
946 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
947 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
949 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
950 sq_config
&= ~(R600_PS_PRIO(3) |
954 sq_config
|= (R600_DX9_CONSTS
|
961 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) {
962 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(124) |
963 R600_NUM_VS_GPRS(124) |
964 R600_NUM_CLAUSE_TEMP_GPRS(4));
965 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(0) |
966 R600_NUM_ES_GPRS(0));
967 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(136) |
968 R600_NUM_VS_THREADS(48) |
969 R600_NUM_GS_THREADS(4) |
970 R600_NUM_ES_THREADS(4));
971 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(128) |
972 R600_NUM_VS_STACK_ENTRIES(128));
973 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(0) |
974 R600_NUM_ES_STACK_ENTRIES(0));
975 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
976 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
977 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
)) {
978 /* no vertex cache */
979 sq_config
&= ~R600_VC_ENABLE
;
981 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
982 R600_NUM_VS_GPRS(44) |
983 R600_NUM_CLAUSE_TEMP_GPRS(2));
984 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
985 R600_NUM_ES_GPRS(17));
986 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
987 R600_NUM_VS_THREADS(78) |
988 R600_NUM_GS_THREADS(4) |
989 R600_NUM_ES_THREADS(31));
990 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
991 R600_NUM_VS_STACK_ENTRIES(40));
992 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
993 R600_NUM_ES_STACK_ENTRIES(16));
994 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
995 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV635
)) {
996 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
997 R600_NUM_VS_GPRS(44) |
998 R600_NUM_CLAUSE_TEMP_GPRS(2));
999 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(18) |
1000 R600_NUM_ES_GPRS(18));
1001 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1002 R600_NUM_VS_THREADS(78) |
1003 R600_NUM_GS_THREADS(4) |
1004 R600_NUM_ES_THREADS(31));
1005 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
1006 R600_NUM_VS_STACK_ENTRIES(40));
1007 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
1008 R600_NUM_ES_STACK_ENTRIES(16));
1009 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
) {
1010 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1011 R600_NUM_VS_GPRS(44) |
1012 R600_NUM_CLAUSE_TEMP_GPRS(2));
1013 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
1014 R600_NUM_ES_GPRS(17));
1015 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1016 R600_NUM_VS_THREADS(78) |
1017 R600_NUM_GS_THREADS(4) |
1018 R600_NUM_ES_THREADS(31));
1019 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(64) |
1020 R600_NUM_VS_STACK_ENTRIES(64));
1021 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(64) |
1022 R600_NUM_ES_STACK_ENTRIES(64));
1025 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1026 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1027 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1028 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1029 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1030 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1032 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
1033 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
1034 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
))
1035 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_TC_ONLY
));
1037 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_VC_AND_TC
));
1039 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S
, (R600_S0_X(0xc) |
1043 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S
, (R600_S0_X(0xe) |
1051 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (R600_S0_X(0xe) |
1059 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (R600_S4_X(0x6) |
1069 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1073 gs_prim_buffer_depth
= 0;
1078 gs_prim_buffer_depth
= 32;
1081 gs_prim_buffer_depth
= 128;
1087 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1088 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1089 /* Max value for this is 256 */
1090 if (vgt_gs_per_es
> 256)
1091 vgt_gs_per_es
= 256;
1093 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1094 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1095 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1096 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1098 /* more default values. 2D/3D driver should adjust as needed */
1099 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1100 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1101 RADEON_WRITE(R600_SX_MISC
, 0);
1102 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1103 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1104 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1105 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1106 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1107 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1109 /* clear render buffer base addresses */
1110 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1111 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1112 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1113 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1114 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1115 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1116 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1117 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1119 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1123 tc_cntl
= R600_TC_L2_SIZE(8);
1127 tc_cntl
= R600_TC_L2_SIZE(4);
1130 tc_cntl
= R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT
;
1133 tc_cntl
= R600_TC_L2_SIZE(0);
1137 RADEON_WRITE(R600_TC_CNTL
, tc_cntl
);
1139 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1140 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1142 arb_pop
= RADEON_READ(R600_ARB_POP
);
1143 arb_pop
|= R600_ENABLE_TC128
;
1144 RADEON_WRITE(R600_ARB_POP
, arb_pop
);
1146 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1147 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1148 R600_NUM_CLIP_SEQ(3)));
1149 RADEON_WRITE(R600_PA_SC_ENHANCE
, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1153 static u32
r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
1155 u32 backend_disable_mask
)
1157 u32 backend_map
= 0;
1158 u32 enabled_backends_mask
;
1159 u32 enabled_backends_count
;
1161 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
1165 if (num_tile_pipes
> R7XX_MAX_PIPES
)
1166 num_tile_pipes
= R7XX_MAX_PIPES
;
1167 if (num_tile_pipes
< 1)
1169 if (num_backends
> R7XX_MAX_BACKENDS
)
1170 num_backends
= R7XX_MAX_BACKENDS
;
1171 if (num_backends
< 1)
1174 enabled_backends_mask
= 0;
1175 enabled_backends_count
= 0;
1176 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
1177 if (((backend_disable_mask
>> i
) & 1) == 0) {
1178 enabled_backends_mask
|= (1 << i
);
1179 ++enabled_backends_count
;
1181 if (enabled_backends_count
== num_backends
)
1185 if (enabled_backends_count
== 0) {
1186 enabled_backends_mask
= 1;
1187 enabled_backends_count
= 1;
1190 if (enabled_backends_count
!= num_backends
)
1191 num_backends
= enabled_backends_count
;
1193 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
1194 switch (num_tile_pipes
) {
1196 swizzle_pipe
[0] = 0;
1199 swizzle_pipe
[0] = 0;
1200 swizzle_pipe
[1] = 1;
1203 swizzle_pipe
[0] = 0;
1204 swizzle_pipe
[1] = 2;
1205 swizzle_pipe
[2] = 1;
1208 swizzle_pipe
[0] = 0;
1209 swizzle_pipe
[1] = 2;
1210 swizzle_pipe
[2] = 3;
1211 swizzle_pipe
[3] = 1;
1214 swizzle_pipe
[0] = 0;
1215 swizzle_pipe
[1] = 2;
1216 swizzle_pipe
[2] = 4;
1217 swizzle_pipe
[3] = 1;
1218 swizzle_pipe
[4] = 3;
1221 swizzle_pipe
[0] = 0;
1222 swizzle_pipe
[1] = 2;
1223 swizzle_pipe
[2] = 4;
1224 swizzle_pipe
[3] = 5;
1225 swizzle_pipe
[4] = 3;
1226 swizzle_pipe
[5] = 1;
1229 swizzle_pipe
[0] = 0;
1230 swizzle_pipe
[1] = 2;
1231 swizzle_pipe
[2] = 4;
1232 swizzle_pipe
[3] = 6;
1233 swizzle_pipe
[4] = 3;
1234 swizzle_pipe
[5] = 1;
1235 swizzle_pipe
[6] = 5;
1238 swizzle_pipe
[0] = 0;
1239 swizzle_pipe
[1] = 2;
1240 swizzle_pipe
[2] = 4;
1241 swizzle_pipe
[3] = 6;
1242 swizzle_pipe
[4] = 3;
1243 swizzle_pipe
[5] = 1;
1244 swizzle_pipe
[6] = 7;
1245 swizzle_pipe
[7] = 5;
1250 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1251 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1252 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1254 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
1256 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1262 static void r700_gfx_init(struct drm_device
*dev
,
1263 drm_radeon_private_t
*dev_priv
)
1265 int i
, j
, num_qd_pipes
;
1268 u32 num_gs_verts_per_thread
;
1270 u32 gs_prim_buffer_depth
= 0;
1271 u32 sq_ms_fifo_sizes
;
1273 u32 sq_thread_resource_mgmt
;
1274 u32 hdp_host_path_cntl
;
1275 u32 sq_dyn_gpr_size_simd_ab_0
;
1277 u32 gb_tiling_config
= 0;
1278 u32 cc_rb_backend_disable
= 0;
1279 u32 cc_gc_shader_pipe_config
= 0;
1283 /* setup chip specs */
1284 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1286 dev_priv
->r600_max_pipes
= 4;
1287 dev_priv
->r600_max_tile_pipes
= 8;
1288 dev_priv
->r600_max_simds
= 10;
1289 dev_priv
->r600_max_backends
= 4;
1290 dev_priv
->r600_max_gprs
= 256;
1291 dev_priv
->r600_max_threads
= 248;
1292 dev_priv
->r600_max_stack_entries
= 512;
1293 dev_priv
->r600_max_hw_contexts
= 8;
1294 dev_priv
->r600_max_gs_threads
= 16 * 2;
1295 dev_priv
->r600_sx_max_export_size
= 128;
1296 dev_priv
->r600_sx_max_export_pos_size
= 16;
1297 dev_priv
->r600_sx_max_export_smx_size
= 112;
1298 dev_priv
->r600_sq_num_cf_insts
= 2;
1300 dev_priv
->r700_sx_num_of_sets
= 7;
1301 dev_priv
->r700_sc_prim_fifo_size
= 0xF9;
1302 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1303 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1306 dev_priv
->r600_max_pipes
= 2;
1307 dev_priv
->r600_max_tile_pipes
= 4;
1308 dev_priv
->r600_max_simds
= 8;
1309 dev_priv
->r600_max_backends
= 2;
1310 dev_priv
->r600_max_gprs
= 128;
1311 dev_priv
->r600_max_threads
= 248;
1312 dev_priv
->r600_max_stack_entries
= 256;
1313 dev_priv
->r600_max_hw_contexts
= 8;
1314 dev_priv
->r600_max_gs_threads
= 16 * 2;
1315 dev_priv
->r600_sx_max_export_size
= 256;
1316 dev_priv
->r600_sx_max_export_pos_size
= 32;
1317 dev_priv
->r600_sx_max_export_smx_size
= 224;
1318 dev_priv
->r600_sq_num_cf_insts
= 2;
1320 dev_priv
->r700_sx_num_of_sets
= 7;
1321 dev_priv
->r700_sc_prim_fifo_size
= 0xf9;
1322 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1323 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1326 dev_priv
->r600_max_pipes
= 2;
1327 dev_priv
->r600_max_tile_pipes
= 2;
1328 dev_priv
->r600_max_simds
= 2;
1329 dev_priv
->r600_max_backends
= 1;
1330 dev_priv
->r600_max_gprs
= 256;
1331 dev_priv
->r600_max_threads
= 192;
1332 dev_priv
->r600_max_stack_entries
= 256;
1333 dev_priv
->r600_max_hw_contexts
= 4;
1334 dev_priv
->r600_max_gs_threads
= 8 * 2;
1335 dev_priv
->r600_sx_max_export_size
= 128;
1336 dev_priv
->r600_sx_max_export_pos_size
= 16;
1337 dev_priv
->r600_sx_max_export_smx_size
= 112;
1338 dev_priv
->r600_sq_num_cf_insts
= 1;
1340 dev_priv
->r700_sx_num_of_sets
= 7;
1341 dev_priv
->r700_sc_prim_fifo_size
= 0x40;
1342 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1343 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1349 /* Initialize HDP */
1351 for (i
= 0; i
< 32; i
++) {
1352 RADEON_WRITE((0x2c14 + j
), 0x00000000);
1353 RADEON_WRITE((0x2c18 + j
), 0x00000000);
1354 RADEON_WRITE((0x2c1c + j
), 0x00000000);
1355 RADEON_WRITE((0x2c20 + j
), 0x00000000);
1356 RADEON_WRITE((0x2c24 + j
), 0x00000000);
1360 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
1362 /* setup tiling, simd, pipe config */
1363 mc_arb_ramcfg
= RADEON_READ(R700_MC_ARB_RAMCFG
);
1365 switch (dev_priv
->r600_max_tile_pipes
) {
1367 gb_tiling_config
|= R600_PIPE_TILING(0);
1370 gb_tiling_config
|= R600_PIPE_TILING(1);
1373 gb_tiling_config
|= R600_PIPE_TILING(2);
1376 gb_tiling_config
|= R600_PIPE_TILING(3);
1382 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV770
)
1383 gb_tiling_config
|= R600_BANK_TILING(1);
1385 gb_tiling_config
|= R600_BANK_TILING((mc_arb_ramcfg
>> R700_NOOFBANK_SHIFT
) & R700_NOOFBANK_MASK
);
1387 gb_tiling_config
|= R600_GROUP_SIZE(0);
1389 if (((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
) > 3) {
1390 gb_tiling_config
|= R600_ROW_TILING(3);
1391 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
1394 R600_ROW_TILING(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1396 R600_SAMPLE_SPLIT(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1399 gb_tiling_config
|= R600_BANK_SWAPS(1);
1401 backend_map
= r700_get_tile_pipe_to_backend_map(dev_priv
->r600_max_tile_pipes
,
1402 dev_priv
->r600_max_backends
,
1403 (0xff << dev_priv
->r600_max_backends
) & 0xff);
1404 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
1406 cc_gc_shader_pipe_config
=
1407 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R7XX_MAX_PIPES_MASK
);
1408 cc_gc_shader_pipe_config
|=
1409 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R7XX_MAX_SIMDS_MASK
);
1411 cc_rb_backend_disable
=
1412 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R7XX_MAX_BACKENDS_MASK
);
1414 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
1415 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1416 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1418 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1419 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1420 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1422 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1423 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE
, 0);
1424 RADEON_WRITE(R700_CGTS_TCC_DISABLE
, 0);
1425 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE
, 0);
1426 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE
, 0);
1429 R7XX_MAX_BACKENDS
- r600_count_pipe_bits(cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
);
1430 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
1431 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
1433 /* set HW defaults for 3D engine */
1434 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
1435 R600_ROQ_IB2_START(0x2b)));
1437 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, R700_STQ_SPLIT(0x30));
1439 RADEON_WRITE(R600_TA_CNTL_AUX
, (R600_DISABLE_CUBE_ANISO
|
1440 R600_SYNC_GRADIENT
|
1442 R600_SYNC_ALIGNER
));
1444 sx_debug_1
= RADEON_READ(R700_SX_DEBUG_1
);
1445 sx_debug_1
|= R700_ENABLE_NEW_SMX_ADDRESS
;
1446 RADEON_WRITE(R700_SX_DEBUG_1
, sx_debug_1
);
1448 smx_dc_ctl0
= RADEON_READ(R600_SMX_DC_CTL0
);
1449 smx_dc_ctl0
&= ~R700_CACHE_DEPTH(0x1ff);
1450 smx_dc_ctl0
|= R700_CACHE_DEPTH((dev_priv
->r700_sx_num_of_sets
* 64) - 1);
1451 RADEON_WRITE(R600_SMX_DC_CTL0
, smx_dc_ctl0
);
1453 RADEON_WRITE(R700_SMX_EVENT_CTL
, (R700_ES_FLUSH_CTL(4) |
1454 R700_GS_FLUSH_CTL(4) |
1455 R700_ACK_FLUSH_CTL(3) |
1456 R700_SYNC_FLUSH_CTL
));
1458 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV770
)
1459 RADEON_WRITE(R700_DB_DEBUG3
, R700_DB_CLK_OFF_DELAY(0x1f));
1461 db_debug4
= RADEON_READ(RV700_DB_DEBUG4
);
1462 db_debug4
|= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER
;
1463 RADEON_WRITE(RV700_DB_DEBUG4
, db_debug4
);
1466 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES
, (R600_COLOR_BUFFER_SIZE((dev_priv
->r600_sx_max_export_size
/ 4) - 1) |
1467 R600_POSITION_BUFFER_SIZE((dev_priv
->r600_sx_max_export_pos_size
/ 4) - 1) |
1468 R600_SMX_BUFFER_SIZE((dev_priv
->r600_sx_max_export_smx_size
/ 4) - 1)));
1470 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX
, (R700_SC_PRIM_FIFO_SIZE(dev_priv
->r700_sc_prim_fifo_size
) |
1471 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_hiz_tile_fifo_size
) |
1472 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_earlyz_tile_fifo_fize
)));
1474 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1476 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 1);
1478 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
1480 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(4));
1482 RADEON_WRITE(R600_CP_PERFMON_CNTL
, 0);
1484 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(16 * dev_priv
->r600_sq_num_cf_insts
) |
1485 R600_DONE_FIFO_HIWATER(0xe0) |
1486 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1487 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1489 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x1);
1494 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x4);
1497 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
1499 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1500 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1502 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
1503 sq_config
&= ~(R600_PS_PRIO(3) |
1507 sq_config
|= (R600_DX9_CONSTS
|
1514 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1515 /* no vertex cache */
1516 sq_config
&= ~R600_VC_ENABLE
;
1518 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1520 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, (R600_NUM_PS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1521 R600_NUM_VS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1522 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv
->r600_max_gprs
* 24)/64)/2)));
1524 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, (R600_NUM_GS_GPRS((dev_priv
->r600_max_gprs
* 7)/64) |
1525 R600_NUM_ES_GPRS((dev_priv
->r600_max_gprs
* 7)/64)));
1527 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS((dev_priv
->r600_max_threads
* 4)/8) |
1528 R600_NUM_VS_THREADS((dev_priv
->r600_max_threads
* 2)/8) |
1529 R600_NUM_ES_THREADS((dev_priv
->r600_max_threads
* 1)/8));
1530 if (((dev_priv
->r600_max_threads
* 1) / 8) > dev_priv
->r600_max_gs_threads
)
1531 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS(dev_priv
->r600_max_gs_threads
);
1533 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS((dev_priv
->r600_max_gs_threads
* 1)/8);
1534 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1536 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, (R600_NUM_PS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1537 R600_NUM_VS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1539 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, (R600_NUM_GS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1540 R600_NUM_ES_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1542 sq_dyn_gpr_size_simd_ab_0
= (R700_SIMDA_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1543 R700_SIMDA_RING1((dev_priv
->r600_max_gprs
* 38)/64) |
1544 R700_SIMDB_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1545 R700_SIMDB_RING1((dev_priv
->r600_max_gprs
* 38)/64));
1547 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
1548 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
1549 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
1550 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
1551 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
1552 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
1553 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
1554 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
1556 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS
, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1557 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1559 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1560 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_TC_ONLY
) |
1561 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1563 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_VC_AND_TC
) |
1564 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1566 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1569 gs_prim_buffer_depth
= 384;
1572 gs_prim_buffer_depth
= 128;
1578 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1579 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1580 /* Max value for this is 256 */
1581 if (vgt_gs_per_es
> 256)
1582 vgt_gs_per_es
= 256;
1584 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1585 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1586 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1588 /* more default values. 2D/3D driver should adjust as needed */
1589 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1590 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1591 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1592 RADEON_WRITE(R600_SX_MISC
, 0);
1593 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1594 RADEON_WRITE(R700_PA_SC_EDGERULE
, 0xaaaaaaaa);
1595 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1596 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE
, 0xffff);
1597 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1598 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1599 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1600 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1602 /* clear render buffer base addresses */
1603 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1604 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1605 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1606 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1607 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1608 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1609 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1610 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1612 RADEON_WRITE(R700_TCP_CNTL
, 0);
1614 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1615 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1617 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1619 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1620 R600_NUM_CLIP_SEQ(3)));
1624 static void r600_cp_init_ring_buffer(struct drm_device
*dev
,
1625 drm_radeon_private_t
*dev_priv
,
1626 struct drm_file
*file_priv
)
1628 struct drm_radeon_master_private
*master_priv
;
1631 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
1632 r700_gfx_init(dev
, dev_priv
);
1634 r600_gfx_init(dev
, dev_priv
);
1636 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
1637 RADEON_READ(R600_GRBM_SOFT_RESET
);
1639 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
1642 /* Set ring buffer size */
1644 RADEON_WRITE(R600_CP_RB_CNTL
,
1645 RADEON_BUF_SWAP_32BIT
|
1646 RADEON_RB_NO_UPDATE
|
1647 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1648 dev_priv
->ring
.size_l2qw
);
1650 RADEON_WRITE(R600_CP_RB_CNTL
,
1651 RADEON_RB_NO_UPDATE
|
1652 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1653 dev_priv
->ring
.size_l2qw
);
1656 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER
, 0x4);
1658 /* Set the write pointer delay */
1659 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
1662 RADEON_WRITE(R600_CP_RB_CNTL
,
1663 RADEON_BUF_SWAP_32BIT
|
1664 RADEON_RB_NO_UPDATE
|
1665 RADEON_RB_RPTR_WR_ENA
|
1666 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1667 dev_priv
->ring
.size_l2qw
);
1669 RADEON_WRITE(R600_CP_RB_CNTL
,
1670 RADEON_RB_NO_UPDATE
|
1671 RADEON_RB_RPTR_WR_ENA
|
1672 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1673 dev_priv
->ring
.size_l2qw
);
1676 /* Initialize the ring buffer's read and write pointers */
1677 RADEON_WRITE(R600_CP_RB_RPTR_WR
, 0);
1678 RADEON_WRITE(R600_CP_RB_WPTR
, 0);
1679 SET_RING_HEAD(dev_priv
, 0);
1680 dev_priv
->ring
.tail
= 0;
1683 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1685 RADEON_WRITE(R600_CP_RB_RPTR_ADDR
,
1686 (dev_priv
->ring_rptr
->offset
1687 - dev
->agp
->base
+ dev_priv
->gart_vm_start
) >> 8);
1688 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI
, 0);
1692 struct drm_sg_mem
*entry
= dev
->sg
;
1693 unsigned long tmp_ofs
, page_ofs
;
1695 tmp_ofs
= dev_priv
->ring_rptr
->offset
-
1696 (unsigned long)dev
->sg
->virtual;
1697 page_ofs
= tmp_ofs
>> PAGE_SHIFT
;
1699 RADEON_WRITE(R600_CP_RB_RPTR_ADDR
, entry
->busaddr
[page_ofs
] >> 8);
1700 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI
, 0);
1701 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1702 (unsigned long)entry
->busaddr
[page_ofs
],
1703 entry
->handle
+ tmp_ofs
);
1707 RADEON_WRITE(R600_CP_RB_CNTL
,
1708 RADEON_BUF_SWAP_32BIT
|
1709 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1710 dev_priv
->ring
.size_l2qw
);
1712 RADEON_WRITE(R600_CP_RB_CNTL
,
1713 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1714 dev_priv
->ring
.size_l2qw
);
1718 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1720 radeon_write_agp_base(dev_priv
, dev
->agp
->base
);
1723 radeon_write_agp_location(dev_priv
,
1724 (((dev_priv
->gart_vm_start
- 1 +
1725 dev_priv
->gart_size
) & 0xffff0000) |
1726 (dev_priv
->gart_vm_start
>> 16)));
1728 ring_start
= (dev_priv
->cp_ring
->offset
1730 + dev_priv
->gart_vm_start
);
1733 ring_start
= (dev_priv
->cp_ring
->offset
1734 - (unsigned long)dev
->sg
->virtual
1735 + dev_priv
->gart_vm_start
);
1737 RADEON_WRITE(R600_CP_RB_BASE
, ring_start
>> 8);
1739 RADEON_WRITE(R600_CP_ME_CNTL
, 0xff);
1741 RADEON_WRITE(R600_CP_DEBUG
, (1 << 27) | (1 << 28));
1743 /* Start with assuming that writeback doesn't work */
1744 dev_priv
->writeback_works
= 0;
1746 /* Initialize the scratch register pointer. This will cause
1747 * the scratch register values to be written out to memory
1748 * whenever they are updated.
1750 * We simply put this behind the ring read pointer, this works
1751 * with PCI GART as well as (whatever kind of) AGP GART
1753 RADEON_WRITE(R600_SCRATCH_ADDR
, ((RADEON_READ(R600_CP_RB_RPTR_ADDR
) << 8)
1754 + R600_SCRATCH_REG_OFFSET
) >> 8);
1756 RADEON_WRITE(R600_SCRATCH_UMSK
, 0x7);
1758 /* Turn on bus mastering */
1759 radeon_enable_bm(dev_priv
);
1761 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(0), 0);
1762 RADEON_WRITE(R600_LAST_FRAME_REG
, 0);
1764 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
1765 RADEON_WRITE(R600_LAST_DISPATCH_REG
, 0);
1767 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(2), 0);
1768 RADEON_WRITE(R600_LAST_CLEAR_REG
, 0);
1770 /* reset sarea copies of these */
1771 master_priv
= file_priv
->master
->driver_priv
;
1772 if (master_priv
->sarea_priv
) {
1773 master_priv
->sarea_priv
->last_frame
= 0;
1774 master_priv
->sarea_priv
->last_dispatch
= 0;
1775 master_priv
->sarea_priv
->last_clear
= 0;
1778 r600_do_wait_for_idle(dev_priv
);
1782 int r600_do_cleanup_cp(struct drm_device
*dev
)
1784 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1787 /* Make sure interrupts are disabled here because the uninstall ioctl
1788 * may not have been called from userspace and after dev_private
1789 * is freed, it's too late.
1791 if (dev
->irq_enabled
)
1792 drm_irq_uninstall(dev
);
1795 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1796 if (dev_priv
->cp_ring
!= NULL
) {
1797 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1798 dev_priv
->cp_ring
= NULL
;
1800 if (dev_priv
->ring_rptr
!= NULL
) {
1801 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1802 dev_priv
->ring_rptr
= NULL
;
1804 if (dev
->agp_buffer_map
!= NULL
) {
1805 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1806 dev
->agp_buffer_map
= NULL
;
1812 if (dev_priv
->gart_info
.bus_addr
)
1813 r600_page_table_cleanup(dev
, &dev_priv
->gart_info
);
1815 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
) {
1816 drm_core_ioremapfree(&dev_priv
->gart_info
.mapping
, dev
);
1817 dev_priv
->gart_info
.addr
= 0;
1820 /* only clear to the start of flags */
1821 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1826 int r600_do_init_cp(struct drm_device
*dev
, drm_radeon_init_t
*init
,
1827 struct drm_file
*file_priv
)
1829 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1830 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
1834 /* if we require new memory map but we don't have it fail */
1835 if ((dev_priv
->flags
& RADEON_NEW_MEMMAP
) && !dev_priv
->new_memmap
) {
1836 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1837 r600_do_cleanup_cp(dev
);
1841 if (init
->is_pci
&& (dev_priv
->flags
& RADEON_IS_AGP
)) {
1842 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1843 dev_priv
->flags
&= ~RADEON_IS_AGP
;
1844 /* The writeback test succeeds, but when writeback is enabled,
1845 * the ring buffer read ptr update fails after first 128 bytes.
1848 } else if (!(dev_priv
->flags
& (RADEON_IS_AGP
| RADEON_IS_PCI
| RADEON_IS_PCIE
))
1850 DRM_DEBUG("Restoring AGP flag\n");
1851 dev_priv
->flags
|= RADEON_IS_AGP
;
1854 dev_priv
->usec_timeout
= init
->usec_timeout
;
1855 if (dev_priv
->usec_timeout
< 1 ||
1856 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
1857 DRM_DEBUG("TIMEOUT problem!\n");
1858 r600_do_cleanup_cp(dev
);
1862 /* Enable vblank on CRTC1 for older X servers
1864 dev_priv
->vblank_crtc
= DRM_RADEON_VBLANK_CRTC1
;
1866 dev_priv
->cp_mode
= init
->cp_mode
;
1868 /* We don't support anything other than bus-mastering ring mode,
1869 * but the ring can be in either AGP or PCI space for the ring
1872 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
1873 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
1874 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
1875 r600_do_cleanup_cp(dev
);
1879 switch (init
->fb_bpp
) {
1881 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
1885 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
1888 dev_priv
->front_offset
= init
->front_offset
;
1889 dev_priv
->front_pitch
= init
->front_pitch
;
1890 dev_priv
->back_offset
= init
->back_offset
;
1891 dev_priv
->back_pitch
= init
->back_pitch
;
1893 dev_priv
->ring_offset
= init
->ring_offset
;
1894 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
1895 dev_priv
->buffers_offset
= init
->buffers_offset
;
1896 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
1898 master_priv
->sarea
= drm_getsarea(dev
);
1899 if (!master_priv
->sarea
) {
1900 DRM_ERROR("could not find sarea!\n");
1901 r600_do_cleanup_cp(dev
);
1905 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
1906 if (!dev_priv
->cp_ring
) {
1907 DRM_ERROR("could not find cp ring region!\n");
1908 r600_do_cleanup_cp(dev
);
1911 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
1912 if (!dev_priv
->ring_rptr
) {
1913 DRM_ERROR("could not find ring read pointer!\n");
1914 r600_do_cleanup_cp(dev
);
1917 dev
->agp_buffer_token
= init
->buffers_offset
;
1918 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
1919 if (!dev
->agp_buffer_map
) {
1920 DRM_ERROR("could not find dma buffer region!\n");
1921 r600_do_cleanup_cp(dev
);
1925 if (init
->gart_textures_offset
) {
1926 dev_priv
->gart_textures
=
1927 drm_core_findmap(dev
, init
->gart_textures_offset
);
1928 if (!dev_priv
->gart_textures
) {
1929 DRM_ERROR("could not find GART texture region!\n");
1930 r600_do_cleanup_cp(dev
);
1937 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1938 drm_core_ioremap_wc(dev_priv
->cp_ring
, dev
);
1939 drm_core_ioremap_wc(dev_priv
->ring_rptr
, dev
);
1940 drm_core_ioremap_wc(dev
->agp_buffer_map
, dev
);
1941 if (!dev_priv
->cp_ring
->handle
||
1942 !dev_priv
->ring_rptr
->handle
||
1943 !dev
->agp_buffer_map
->handle
) {
1944 DRM_ERROR("could not find ioremap agp regions!\n");
1945 r600_do_cleanup_cp(dev
);
1951 dev_priv
->cp_ring
->handle
= (void *)dev_priv
->cp_ring
->offset
;
1952 dev_priv
->ring_rptr
->handle
=
1953 (void *)dev_priv
->ring_rptr
->offset
;
1954 dev
->agp_buffer_map
->handle
=
1955 (void *)dev
->agp_buffer_map
->offset
;
1957 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1958 dev_priv
->cp_ring
->handle
);
1959 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1960 dev_priv
->ring_rptr
->handle
);
1961 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1962 dev
->agp_buffer_map
->handle
);
1965 dev_priv
->fb_location
= (radeon_read_fb_location(dev_priv
) & 0xffff) << 24;
1967 (((radeon_read_fb_location(dev_priv
) & 0xffff0000u
) << 8) + 0x1000000)
1968 - dev_priv
->fb_location
;
1970 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
1971 ((dev_priv
->front_offset
1972 + dev_priv
->fb_location
) >> 10));
1974 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
1975 ((dev_priv
->back_offset
1976 + dev_priv
->fb_location
) >> 10));
1978 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
1979 ((dev_priv
->depth_offset
1980 + dev_priv
->fb_location
) >> 10));
1982 dev_priv
->gart_size
= init
->gart_size
;
1984 /* New let's set the memory map ... */
1985 if (dev_priv
->new_memmap
) {
1988 DRM_INFO("Setting GART location based on new memory map\n");
1990 /* If using AGP, try to locate the AGP aperture at the same
1991 * location in the card and on the bus, though we have to
1996 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1997 base
= dev
->agp
->base
;
1998 /* Check if valid */
1999 if ((base
+ dev_priv
->gart_size
- 1) >= dev_priv
->fb_location
&&
2000 base
< (dev_priv
->fb_location
+ dev_priv
->fb_size
- 1)) {
2001 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2007 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2009 base
= dev_priv
->fb_location
+ dev_priv
->fb_size
;
2010 if (base
< dev_priv
->fb_location
||
2011 ((base
+ dev_priv
->gart_size
) & 0xfffffffful
) < base
)
2012 base
= dev_priv
->fb_location
2013 - dev_priv
->gart_size
;
2015 dev_priv
->gart_vm_start
= base
& 0xffc00000u
;
2016 if (dev_priv
->gart_vm_start
!= base
)
2017 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2018 base
, dev_priv
->gart_vm_start
);
2023 if (dev_priv
->flags
& RADEON_IS_AGP
)
2024 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2026 + dev_priv
->gart_vm_start
);
2029 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2030 - (unsigned long)dev
->sg
->virtual
2031 + dev_priv
->gart_vm_start
);
2033 DRM_DEBUG("fb 0x%08x size %d\n",
2034 (unsigned int) dev_priv
->fb_location
,
2035 (unsigned int) dev_priv
->fb_size
);
2036 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
2037 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2038 (unsigned int) dev_priv
->gart_vm_start
);
2039 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2040 dev_priv
->gart_buffers_offset
);
2042 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
2043 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
2044 + init
->ring_size
/ sizeof(u32
));
2045 dev_priv
->ring
.size
= init
->ring_size
;
2046 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
2048 dev_priv
->ring
.rptr_update
= /* init->rptr_update */ 4096;
2049 dev_priv
->ring
.rptr_update_l2qw
= drm_order(/* init->rptr_update */ 4096 / 8);
2051 dev_priv
->ring
.fetch_size
= /* init->fetch_size */ 32;
2052 dev_priv
->ring
.fetch_size_l2ow
= drm_order(/* init->fetch_size */ 32 / 16);
2054 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
2056 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
2059 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2060 /* XXX turn off pcie gart */
2064 dev_priv
->gart_info
.table_mask
= DMA_BIT_MASK(32);
2065 /* if we have an offset set from userspace */
2066 if (!dev_priv
->pcigart_offset_set
) {
2067 DRM_ERROR("Need gart offset from userspace\n");
2068 r600_do_cleanup_cp(dev
);
2072 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv
->pcigart_offset
);
2074 dev_priv
->gart_info
.bus_addr
=
2075 dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
2076 dev_priv
->gart_info
.mapping
.offset
=
2077 dev_priv
->pcigart_offset
+ dev_priv
->fb_aper_offset
;
2078 dev_priv
->gart_info
.mapping
.size
=
2079 dev_priv
->gart_info
.table_size
;
2081 drm_core_ioremap_wc(&dev_priv
->gart_info
.mapping
, dev
);
2082 if (!dev_priv
->gart_info
.mapping
.handle
) {
2083 DRM_ERROR("ioremap failed.\n");
2084 r600_do_cleanup_cp(dev
);
2088 dev_priv
->gart_info
.addr
=
2089 dev_priv
->gart_info
.mapping
.handle
;
2091 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2092 dev_priv
->gart_info
.addr
,
2093 dev_priv
->pcigart_offset
);
2095 if (r600_page_table_init(dev
)) {
2096 DRM_ERROR("Failed to init GART table\n");
2097 r600_do_cleanup_cp(dev
);
2101 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2107 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2108 r700_cp_load_microcode(dev_priv
);
2110 r600_cp_load_microcode(dev_priv
);
2112 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2114 dev_priv
->last_buf
= 0;
2116 r600_do_engine_reset(dev
);
2117 r600_test_writeback(dev_priv
);
2122 int r600_do_resume_cp(struct drm_device
*dev
, struct drm_file
*file_priv
)
2124 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2127 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)) {
2129 r700_cp_load_microcode(dev_priv
);
2132 r600_cp_load_microcode(dev_priv
);
2134 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2135 r600_do_engine_reset(dev
);
2140 /* Wait for the CP to go idle.
2142 int r600_do_cp_idle(drm_radeon_private_t
*dev_priv
)
2148 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
2149 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT
);
2150 /* wait for 3D idle clean */
2151 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
2152 OUT_RING((R600_WAIT_UNTIL
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
2153 OUT_RING(RADEON_WAIT_3D_IDLE
| RADEON_WAIT_3D_IDLECLEAN
);
2158 return r600_do_wait_for_idle(dev_priv
);
2161 /* Start the Command Processor.
2163 void r600_do_cp_start(drm_radeon_private_t
*dev_priv
)
2170 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE
, 5));
2171 OUT_RING(0x00000001);
2172 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_RV770
))
2173 OUT_RING(0x00000003);
2175 OUT_RING(0x00000000);
2176 OUT_RING((dev_priv
->r600_max_hw_contexts
- 1));
2177 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2178 OUT_RING(0x00000000);
2179 OUT_RING(0x00000000);
2183 /* set the mux and reset the halt bit */
2185 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2187 dev_priv
->cp_running
= 1;
2191 void r600_do_cp_reset(drm_radeon_private_t
*dev_priv
)
2196 cur_read_ptr
= RADEON_READ(R600_CP_RB_RPTR
);
2197 RADEON_WRITE(R600_CP_RB_WPTR
, cur_read_ptr
);
2198 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
2199 dev_priv
->ring
.tail
= cur_read_ptr
;
2202 void r600_do_cp_stop(drm_radeon_private_t
*dev_priv
)
2208 cp_me
= 0xff | R600_CP_ME_HALT
;
2210 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2212 dev_priv
->cp_running
= 0;
2215 int r600_cp_dispatch_indirect(struct drm_device
*dev
,
2216 struct drm_buf
*buf
, int start
, int end
)
2218 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2222 unsigned long offset
= (dev_priv
->gart_buffers_offset
2223 + buf
->offset
+ start
);
2224 int dwords
= (end
- start
+ 3) / sizeof(u32
);
2226 DRM_DEBUG("dwords:%d\n", dwords
);
2227 DRM_DEBUG("offset 0x%lx\n", offset
);
2230 /* Indirect buffer data must be a multiple of 16 dwords.
2231 * pad the data with a Type-2 CP packet.
2233 while (dwords
& 0xf) {
2235 ((char *)dev
->agp_buffer_map
->handle
2236 + buf
->offset
+ start
);
2237 data
[dwords
++] = RADEON_CP_PACKET2
;
2240 /* Fire off the indirect buffer */
2242 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER
, 2));
2243 OUT_RING((offset
& 0xfffffffc));
2244 OUT_RING((upper_32_bits(offset
) & 0xff));