include/asm-xtensa/xtensa/config-linux_be/specreg.h

   1 /*
   2  * Xtensa Special Register symbolic names
   3  */
   4
   5 /* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
   6
   7 /*
   8  * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2.1 of the GNU Lesser General Public
  12  * License as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it would be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17  *
  18  * Further, this software is distributed without any warranty that it is
  19  * free of the rightful claim of any third person regarding infringement
  20  * or the like.  Any license provided herein, whether implied or
  21  * otherwise, applies only to this software file.  Patent licenses, if
  22  * any, provided herein do not apply to combinations of this program with
  23  * other software, or any other product whatsoever.
  24  *
  25  * You should have received a copy of the GNU Lesser General Public
  26  * License along with this program; if not, write the Free Software
  27  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
  28  * USA.
  29  */
  30
  31 #ifndef XTENSA_SPECREG_H
  32 #define XTENSA_SPECREG_H
  33
  34 /*  Include these special register bitfield definitions, for historical reasons:  */
  35 #include <xtensa/corebits.h>
  36
  37
  38 /*  Special registers:  */
  39 #define LBEG            0
  40 #define LEND            1
  41 #define LCOUNT          2
  42 #define SAR             3
  43 #define WINDOWBASE      72
  44 #define WINDOWSTART     73
  45 #define PTEVADDR        83
  46 #define RASID           90
  47 #define ITLBCFG         91
  48 #define DTLBCFG         92
  49 #define IBREAKENABLE    96
  50 #define DDR             104
  51 #define IBREAKA_0       128
  52 #define IBREAKA_1       129
  53 #define DBREAKA_0       144
  54 #define DBREAKA_1       145
  55 #define DBREAKC_0       160
  56 #define DBREAKC_1       161
  57 #define EPC_1           177
  58 #define EPC_2           178
  59 #define EPC_3           179
  60 #define EPC_4           180
  61 #define DEPC            192
  62 #define EPS_2           194
  63 #define EPS_3           195
  64 #define EPS_4           196
  65 #define EXCSAVE_1       209
  66 #define EXCSAVE_2       210
  67 #define EXCSAVE_3       211
  68 #define EXCSAVE_4       212
  69 #define INTERRUPT       226
  70 #define INTENABLE       228
  71 #define PS              230
  72 #define EXCCAUSE        232
  73 #define DEBUGCAUSE      233
  74 #define CCOUNT          234
  75 #define ICOUNT          236
  76 #define ICOUNTLEVEL     237
  77 #define EXCVADDR        238
  78 #define CCOMPARE_0      240
  79 #define CCOMPARE_1      241
  80 #define CCOMPARE_2      242
  81 #define MISC_REG_0      244
  82 #define MISC_REG_1      245
  83
  84 /*  Special cases (bases of special register series):  */
  85 #define IBREAKA         128
  86 #define DBREAKA         144
  87 #define DBREAKC         160
  88 #define EPC             176
  89 #define EPS             192
  90 #define EXCSAVE         208
  91 #define CCOMPARE        240
  92
  93 /*  Special names for read-only and write-only interrupt registers:  */
  94 #define INTREAD         226
  95 #define INTSET          226
  96 #define INTCLEAR        227
  97
  98 #endif /* XTENSA_SPECREG_H */
  99