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[PATCH] drivers/isdn/gigaset: build asyncdata.o into the gigaset module (fix)
[linux-2.6/linux-loongson.git] / drivers / serial / sh-sci.c
blobc53b69610a51005c0b845eb9a63c00e900a311e7
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20
21 #undef DEBUG
22
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/timer.h>
26 #include <linux/interrupt.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/sysrq.h>
33 #include <linux/ioport.h>
34 #include <linux/mm.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/console.h>
38 #include <linux/platform_device.h>
39
40 #ifdef CONFIG_CPU_FREQ
41 #include <linux/notifier.h>
42 #include <linux/cpufreq.h>
43 #endif
44
45 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
46 #include <asm/clock.h>
47 #include <asm/sh_bios.h>
48 #include <asm/kgdb.h>
49 #endif
50
51 #include <asm/sci.h>
52
53 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #define SUPPORT_SYSRQ
55 #endif
56
57 #include "sh-sci.h"
58
59 struct sci_port {
60 struct uart_port port;
61
62 /* Port type */
63 unsigned int type;
64
65 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
66 unsigned int irqs[SCIx_NR_IRQS];
67
68 /* Port pin configuration */
69 void (*init_pins)(struct uart_port *port,
70 unsigned int cflag);
71
72 /* Port enable callback */
73 void (*enable)(struct uart_port *port);
74
75 /* Port disable callback */
76 void (*disable)(struct uart_port *port);
77
78 /* Break timer */
79 struct timer_list break_timer;
80 int break_flag;
81 };
82
83 #ifdef CONFIG_SH_KGDB
84 static struct sci_port *kgdb_sci_port;
85 #endif
86
87 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
88 static struct sci_port *serial_console_port;
89 #endif
90
91 /* Function prototypes */
92 static void sci_stop_tx(struct uart_port *port);
93
94 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
95
96 static struct sci_port sci_ports[SCI_NPORTS];
97 static struct uart_driver sci_uart_driver;
98
99 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
100 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
101 static inline void handle_error(struct uart_port *port)
102 {
103 /* Clear error flags */
104 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
105 }
106
107 static int get_char(struct uart_port *port)
108 {
109 unsigned long flags;
110 unsigned short status;
111 int c;
112
113 spin_lock_irqsave(&port->lock, flags);
114 do {
115 status = sci_in(port, SCxSR);
116 if (status & SCxSR_ERRORS(port)) {
117 handle_error(port);
118 continue;
119 }
120 } while (!(status & SCxSR_RDxF(port)));
121 c = sci_in(port, SCxRDR);
122 sci_in(port, SCxSR); /* Dummy read */
123 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
124 spin_unlock_irqrestore(&port->lock, flags);
125
126 return c;
127 }
128 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
129
130 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
131 static void put_char(struct uart_port *port, char c)
132 {
133 unsigned long flags;
134 unsigned short status;
135
136 spin_lock_irqsave(&port->lock, flags);
137
138 do {
139 status = sci_in(port, SCxSR);
140 } while (!(status & SCxSR_TDxE(port)));
141
142 sci_out(port, SCxTDR, c);
143 sci_in(port, SCxSR); /* Dummy read */
144 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
145
146 spin_unlock_irqrestore(&port->lock, flags);
147 }
148 #endif
149
150 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
151 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
152 {
153 struct uart_port *port = &sci_port->port;
154 const unsigned char *p = buffer;
155 int i;
156
157 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
158 int checksum;
159 int usegdb=0;
160
161 #ifdef CONFIG_SH_STANDARD_BIOS
162 /* This call only does a trap the first time it is
163 * called, and so is safe to do here unconditionally
164 */
165 usegdb |= sh_bios_in_gdb_mode();
166 #endif
167 #ifdef CONFIG_SH_KGDB
168 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
169 #endif
170
171 if (usegdb) {
172 /* $<packet info>#<checksum>. */
173 do {
174 unsigned char c;
175 put_char(port, '$');
176 put_char(port, 'O'); /* 'O'utput to console */
177 checksum = 'O';
178
179 for (i=0; i<count; i++) { /* Don't use run length encoding */
180 int h, l;
181
182 c = *p++;
183 h = highhex(c);
184 l = lowhex(c);
185 put_char(port, h);
186 put_char(port, l);
187 checksum += h + l;
188 }
189 put_char(port, '#');
190 put_char(port, highhex(checksum));
191 put_char(port, lowhex(checksum));
192 } while (get_char(port) != '+');
193 } else
194 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
195 for (i=0; i<count; i++) {
196 if (*p == 10)
197 put_char(port, '\r');
198 put_char(port, *p++);
199 }
200 }
201 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
202
203 #ifdef CONFIG_SH_KGDB
204 static int kgdb_sci_getchar(void)
205 {
206 int c;
207
208 /* Keep trying to read a character, this could be neater */
209 while ((c = get_char(kgdb_sci_port)) < 0)
210 cpu_relax();
211
212 return c;
213 }
214
215 static inline void kgdb_sci_putchar(int c)
216 {
217 put_char(kgdb_sci_port, c);
218 }
219 #endif /* CONFIG_SH_KGDB */
220
221 #if defined(__H8300S__)
222 enum { sci_disable, sci_enable };
223
224 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
225 {
226 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
227 int ch = (port->mapbase - SMR0) >> 3;
228 unsigned char mask = 1 << (ch+1);
229
230 if (ctrl == sci_disable) {
231 *mstpcrl |= mask;
232 } else {
233 *mstpcrl &= ~mask;
234 }
235 }
236
237 static inline void h8300_sci_enable(struct uart_port *port)
238 {
239 h8300_sci_config(port, sci_enable);
240 }
241
242 static inline void h8300_sci_disable(struct uart_port *port)
243 {
244 h8300_sci_config(port, sci_disable);
245 }
246 #endif
247
248 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
249 defined(__H8300H__) || defined(__H8300S__)
250 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
251 {
252 int ch = (port->mapbase - SMR0) >> 3;
253
254 /* set DDR regs */
255 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
256 h8300_sci_pins[ch].rx,
257 H8300_GPIO_INPUT);
258 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
259 h8300_sci_pins[ch].tx,
260 H8300_GPIO_OUTPUT);
261
262 /* tx mark output*/
263 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
264 }
265 #else
266 #define sci_init_pins_sci NULL
267 #endif
268
269 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
270 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
271 {
272 unsigned int fcr_val = 0;
273
274 if (cflag & CRTSCTS)
275 fcr_val |= SCFCR_MCE;
276
277 sci_out(port, SCFCR, fcr_val);
278 }
279 #else
280 #define sci_init_pins_irda NULL
281 #endif
282
283 #ifdef SCI_ONLY
284 #define sci_init_pins_scif NULL
285 #endif
286
287 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
288 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
289 /* SH7300 doesn't use RTS/CTS */
290 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
291 {
292 sci_out(port, SCFCR, 0);
293 }
294 #elif defined(CONFIG_CPU_SH3)
295 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
296 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
297 {
298 unsigned int fcr_val = 0;
299 unsigned short data;
300
301 /* We need to set SCPCR to enable RTS/CTS */
302 data = ctrl_inw(SCPCR);
303 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
304 ctrl_outw(data & 0x0fcf, SCPCR);
305
306 if (cflag & CRTSCTS)
307 fcr_val |= SCFCR_MCE;
308 else {
309 /* We need to set SCPCR to enable RTS/CTS */
310 data = ctrl_inw(SCPCR);
311 /* Clear out SCP7MD1,0, SCP4MD1,0,
312 Set SCP6MD1,0 = {01} (output) */
313 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
314
315 data = ctrl_inb(SCPDR);
316 /* Set /RTS2 (bit6) = 0 */
317 ctrl_outb(data & 0xbf, SCPDR);
318 }
319
320 sci_out(port, SCFCR, fcr_val);
321 }
322 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
323 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
324 {
325 unsigned int fcr_val = 0;
326
327 if (cflag & CRTSCTS) {
328 fcr_val |= SCFCR_MCE;
329
330 ctrl_outw(0x0000, PORT_PSCR);
331 } else {
332 unsigned short data;
333
334 data = ctrl_inw(PORT_PSCR);
335 data &= 0x033f;
336 data |= 0x0400;
337 ctrl_outw(data, PORT_PSCR);
338
339 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
340 }
341
342 sci_out(port, SCFCR, fcr_val);
343 }
344 #else
345 /* For SH7750 */
346 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
347 {
348 unsigned int fcr_val = 0;
349
350 if (cflag & CRTSCTS) {
351 fcr_val |= SCFCR_MCE;
352 } else {
353 #ifdef CONFIG_CPU_SUBTYPE_SH7343
354 /* Nothing */
355 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
356 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
357 #else
358 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
359 #endif
360 }
361 sci_out(port, SCFCR, fcr_val);
362 }
363 #endif
364
365 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
366 static inline int scif_txroom(struct uart_port *port)
367 {
368 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
369 }
370
371 static inline int scif_rxroom(struct uart_port *port)
372 {
373 return sci_in(port, SCRFDR) & 0x7f;
374 }
375 #else
376 static inline int scif_txroom(struct uart_port *port)
377 {
378 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
379 }
380
381 static inline int scif_rxroom(struct uart_port *port)
382 {
383 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
384 }
385 #endif
386 #endif /* SCIF_ONLY || SCI_AND_SCIF */
387
388 static inline int sci_txroom(struct uart_port *port)
389 {
390 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
391 }
392
393 static inline int sci_rxroom(struct uart_port *port)
394 {
395 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
396 }
397
398 /* ********************************************************************** *
399 * the interrupt related routines *
400 * ********************************************************************** */
401
402 static void sci_transmit_chars(struct uart_port *port)
403 {
404 struct circ_buf *xmit = &port->info->xmit;
405 unsigned int stopped = uart_tx_stopped(port);
406 unsigned short status;
407 unsigned short ctrl;
408 int count;
409
410 status = sci_in(port, SCxSR);
411 if (!(status & SCxSR_TDxE(port))) {
412 ctrl = sci_in(port, SCSCR);
413 if (uart_circ_empty(xmit)) {
414 ctrl &= ~SCI_CTRL_FLAGS_TIE;
415 } else {
416 ctrl |= SCI_CTRL_FLAGS_TIE;
417 }
418 sci_out(port, SCSCR, ctrl);
419 return;
420 }
421
422 #ifndef SCI_ONLY
423 if (port->type == PORT_SCIF)
424 count = scif_txroom(port);
425 else
426 #endif
427 count = sci_txroom(port);
428
429 do {
430 unsigned char c;
431
432 if (port->x_char) {
433 c = port->x_char;
434 port->x_char = 0;
435 } else if (!uart_circ_empty(xmit) && !stopped) {
436 c = xmit->buf[xmit->tail];
437 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
438 } else {
439 break;
440 }
441
442 sci_out(port, SCxTDR, c);
443
444 port->icount.tx++;
445 } while (--count > 0);
446
447 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
448
449 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
450 uart_write_wakeup(port);
451 if (uart_circ_empty(xmit)) {
452 sci_stop_tx(port);
453 } else {
454 ctrl = sci_in(port, SCSCR);
455
456 #if !defined(SCI_ONLY)
457 if (port->type == PORT_SCIF) {
458 sci_in(port, SCxSR); /* Dummy read */
459 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
460 }
461 #endif
462
463 ctrl |= SCI_CTRL_FLAGS_TIE;
464 sci_out(port, SCSCR, ctrl);
465 }
466 }
467
468 /* On SH3, SCIF may read end-of-break as a space->mark char */
469 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
470
471 static inline void sci_receive_chars(struct uart_port *port)
472 {
473 struct sci_port *sci_port = (struct sci_port *)port;
474 struct tty_struct *tty = port->info->tty;
475 int i, count, copied = 0;
476 unsigned short status;
477 unsigned char flag;
478
479 status = sci_in(port, SCxSR);
480 if (!(status & SCxSR_RDxF(port)))
481 return;
482
483 while (1) {
484 #if !defined(SCI_ONLY)
485 if (port->type == PORT_SCIF)
486 count = scif_rxroom(port);
487 else
488 #endif
489 count = sci_rxroom(port);
490
491 /* Don't copy more bytes than there is room for in the buffer */
492 count = tty_buffer_request_room(tty, count);
493
494 /* If for any reason we can't copy more data, we're done! */
495 if (count == 0)
496 break;
497
498 if (port->type == PORT_SCI) {
499 char c = sci_in(port, SCxRDR);
500 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
501 count = 0;
502 else {
503 tty_insert_flip_char(tty, c, TTY_NORMAL);
504 }
505 } else {
506 for (i=0; i<count; i++) {
507 char c = sci_in(port, SCxRDR);
508 status = sci_in(port, SCxSR);
509 #if defined(CONFIG_CPU_SH3)
510 /* Skip "chars" during break */
511 if (sci_port->break_flag) {
512 if ((c == 0) &&
513 (status & SCxSR_FER(port))) {
514 count--; i--;
515 continue;
516 }
517
518 /* Nonzero => end-of-break */
519 pr_debug("scif: debounce<%02x>\n", c);
520 sci_port->break_flag = 0;
521
522 if (STEPFN(c)) {
523 count--; i--;
524 continue;
525 }
526 }
527 #endif /* CONFIG_CPU_SH3 */
528 if (uart_handle_sysrq_char(port, c)) {
529 count--; i--;
530 continue;
531 }
532
533 /* Store data and status */
534 if (status&SCxSR_FER(port)) {
535 flag = TTY_FRAME;
536 pr_debug("sci: frame error\n");
537 } else if (status&SCxSR_PER(port)) {
538 flag = TTY_PARITY;
539 pr_debug("sci: parity error\n");
540 } else
541 flag = TTY_NORMAL;
542 tty_insert_flip_char(tty, c, flag);
543 }
544 }
545
546 sci_in(port, SCxSR); /* dummy read */
547 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
548
549 copied += count;
550 port->icount.rx += count;
551 }
552
553 if (copied) {
554 /* Tell the rest of the system the news. New characters! */
555 tty_flip_buffer_push(tty);
556 } else {
557 sci_in(port, SCxSR); /* dummy read */
558 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
559 }
560 }
561
562 #define SCI_BREAK_JIFFIES (HZ/20)
563 /* The sci generates interrupts during the break,
564 * 1 per millisecond or so during the break period, for 9600 baud.
565 * So dont bother disabling interrupts.
566 * But dont want more than 1 break event.
567 * Use a kernel timer to periodically poll the rx line until
568 * the break is finished.
569 */
570 static void sci_schedule_break_timer(struct sci_port *port)
571 {
572 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
573 add_timer(&port->break_timer);
574 }
575 /* Ensure that two consecutive samples find the break over. */
576 static void sci_break_timer(unsigned long data)
577 {
578 struct sci_port *port = (struct sci_port *)data;
579
580 if (sci_rxd_in(&port->port) == 0) {
581 port->break_flag = 1;
582 sci_schedule_break_timer(port);
583 } else if (port->break_flag == 1) {
584 /* break is over. */
585 port->break_flag = 2;
586 sci_schedule_break_timer(port);
587 } else
588 port->break_flag = 0;
589 }
590
591 static inline int sci_handle_errors(struct uart_port *port)
592 {
593 int copied = 0;
594 unsigned short status = sci_in(port, SCxSR);
595 struct tty_struct *tty = port->info->tty;
596
597 if (status & SCxSR_ORER(port)) {
598 /* overrun error */
599 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
600 copied++;
601 pr_debug("sci: overrun error\n");
602 }
603
604 if (status & SCxSR_FER(port)) {
605 if (sci_rxd_in(port) == 0) {
606 /* Notify of BREAK */
607 struct sci_port *sci_port = (struct sci_port *)port;
608
609 if (!sci_port->break_flag) {
610 sci_port->break_flag = 1;
611 sci_schedule_break_timer(sci_port);
612
613 /* Do sysrq handling. */
614 if (uart_handle_break(port))
615 return 0;
616 pr_debug("sci: BREAK detected\n");
617 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
618 copied++;
619 }
620 } else {
621 /* frame error */
622 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
623 copied++;
624 pr_debug("sci: frame error\n");
625 }
626 }
627
628 if (status & SCxSR_PER(port)) {
629 /* parity error */
630 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
631 copied++;
632 pr_debug("sci: parity error\n");
633 }
634
635 if (copied)
636 tty_flip_buffer_push(tty);
637
638 return copied;
639 }
640
641 static inline int sci_handle_breaks(struct uart_port *port)
642 {
643 int copied = 0;
644 unsigned short status = sci_in(port, SCxSR);
645 struct tty_struct *tty = port->info->tty;
646 struct sci_port *s = &sci_ports[port->line];
647
648 if (!s->break_flag && status & SCxSR_BRK(port)) {
649 #if defined(CONFIG_CPU_SH3)
650 /* Debounce break */
651 s->break_flag = 1;
652 #endif
653 /* Notify of BREAK */
654 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
655 copied++;
656 pr_debug("sci: BREAK detected\n");
657 }
658
659 #if defined(SCIF_ORER)
660 /* XXX: Handle SCIF overrun error */
661 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
662 sci_out(port, SCLSR, 0);
663 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
664 copied++;
665 pr_debug("sci: overrun error\n");
666 }
667 }
668 #endif
669
670 if (copied)
671 tty_flip_buffer_push(tty);
672
673 return copied;
674 }
675
676 static irqreturn_t sci_rx_interrupt(int irq, void *port)
677 {
678 /* I think sci_receive_chars has to be called irrespective
679 * of whether the I_IXOFF is set, otherwise, how is the interrupt
680 * to be disabled?
681 */
682 sci_receive_chars(port);
683
684 return IRQ_HANDLED;
685 }
686
687 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
688 {
689 struct uart_port *port = ptr;
690
691 spin_lock_irq(&port->lock);
692 sci_transmit_chars(port);
693 spin_unlock_irq(&port->lock);
694
695 return IRQ_HANDLED;
696 }
697
698 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
699 {
700 struct uart_port *port = ptr;
701
702 /* Handle errors */
703 if (port->type == PORT_SCI) {
704 if (sci_handle_errors(port)) {
705 /* discard character in rx buffer */
706 sci_in(port, SCxSR);
707 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
708 }
709 } else {
710 #if defined(SCIF_ORER)
711 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
712 struct tty_struct *tty = port->info->tty;
713
714 sci_out(port, SCLSR, 0);
715 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
716 tty_flip_buffer_push(tty);
717 pr_debug("scif: overrun error\n");
718 }
719 #endif
720 sci_rx_interrupt(irq, ptr);
721 }
722
723 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
724
725 /* Kick the transmission */
726 sci_tx_interrupt(irq, ptr);
727
728 return IRQ_HANDLED;
729 }
730
731 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
732 {
733 struct uart_port *port = ptr;
734
735 /* Handle BREAKs */
736 sci_handle_breaks(port);
737
738 #ifdef CONFIG_SH_KGDB
739 /* Break into the debugger if a break is detected */
740 BREAKPOINT();
741 #endif
742
743 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
744
745 return IRQ_HANDLED;
746 }
747
748 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
749 {
750 unsigned short ssr_status, scr_status;
751 struct uart_port *port = ptr;
752
753 ssr_status = sci_in(port,SCxSR);
754 scr_status = sci_in(port,SCSCR);
755
756 /* Tx Interrupt */
757 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
758 sci_tx_interrupt(irq, ptr);
759 /* Rx Interrupt */
760 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
761 sci_rx_interrupt(irq, ptr);
762 /* Error Interrupt */
763 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
764 sci_er_interrupt(irq, ptr);
765 /* Break Interrupt */
766 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
767 sci_br_interrupt(irq, ptr);
768
769 return IRQ_HANDLED;
770 }
771
772 #ifdef CONFIG_CPU_FREQ
773 /*
774 * Here we define a transistion notifier so that we can update all of our
775 * ports' baud rate when the peripheral clock changes.
776 */
777 static int sci_notifier(struct notifier_block *self,
778 unsigned long phase, void *p)
779 {
780 struct cpufreq_freqs *freqs = p;
781 int i;
782
783 if ((phase == CPUFREQ_POSTCHANGE) ||
784 (phase == CPUFREQ_RESUMECHANGE)){
785 for (i = 0; i < SCI_NPORTS; i++) {
786 struct uart_port *port = &sci_ports[i].port;
787 struct clk *clk;
788
789 /*
790 * Update the uartclk per-port if frequency has
791 * changed, since it will no longer necessarily be
792 * consistent with the old frequency.
793 *
794 * Really we want to be able to do something like
795 * uart_change_speed() or something along those lines
796 * here to implicitly reset the per-port baud rate..
797 *
798 * Clean this up later..
799 */
800 clk = clk_get(NULL, "module_clk");
801 port->uartclk = clk_get_rate(clk) * 16;
802 clk_put(clk);
803 }
804
805 printk(KERN_INFO "%s: got a postchange notification "
806 "for cpu %d (old %d, new %d)\n",
807 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
808 }
809
810 return NOTIFY_OK;
811 }
812
813 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
814 #endif /* CONFIG_CPU_FREQ */
815
816 static int sci_request_irq(struct sci_port *port)
817 {
818 int i;
819 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
820 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
821 sci_br_interrupt,
822 };
823 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
824 "SCI Transmit Data Empty", "SCI Break" };
825
826 if (port->irqs[0] == port->irqs[1]) {
827 if (!port->irqs[0]) {
828 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
829 return -ENODEV;
830 }
831
832 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
833 IRQF_DISABLED, "sci", port)) {
834 printk(KERN_ERR "sci: Cannot allocate irq.\n");
835 return -ENODEV;
836 }
837 } else {
838 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
839 if (!port->irqs[i])
840 continue;
841 if (request_irq(port->irqs[i], handlers[i],
842 IRQF_DISABLED, desc[i], port)) {
843 printk(KERN_ERR "sci: Cannot allocate irq.\n");
844 return -ENODEV;
845 }
846 }
847 }
848
849 return 0;
850 }
851
852 static void sci_free_irq(struct sci_port *port)
853 {
854 int i;
855
856 if (port->irqs[0] == port->irqs[1]) {
857 if (!port->irqs[0])
858 printk("sci: sci_free_irq error\n");
859 else
860 free_irq(port->irqs[0], port);
861 } else {
862 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
863 if (!port->irqs[i])
864 continue;
865
866 free_irq(port->irqs[i], port);
867 }
868 }
869 }
870
871 static unsigned int sci_tx_empty(struct uart_port *port)
872 {
873 /* Can't detect */
874 return TIOCSER_TEMT;
875 }
876
877 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
878 {
879 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
880 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
881 /* If you have signals for DTR and DCD, please implement here. */
882 }
883
884 static unsigned int sci_get_mctrl(struct uart_port *port)
885 {
886 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
887 and CTS/RTS */
888
889 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
890 }
891
892 static void sci_start_tx(struct uart_port *port)
893 {
894 unsigned short ctrl;
895
896 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
897 ctrl = sci_in(port, SCSCR);
898 ctrl |= SCI_CTRL_FLAGS_TIE;
899 sci_out(port, SCSCR, ctrl);
900 }
901
902 static void sci_stop_tx(struct uart_port *port)
903 {
904 unsigned short ctrl;
905
906 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
907 ctrl = sci_in(port, SCSCR);
908 ctrl &= ~SCI_CTRL_FLAGS_TIE;
909 sci_out(port, SCSCR, ctrl);
910 }
911
912 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
913 {
914 unsigned short ctrl;
915
916 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
917 ctrl = sci_in(port, SCSCR);
918 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
919 sci_out(port, SCSCR, ctrl);
920 }
921
922 static void sci_stop_rx(struct uart_port *port)
923 {
924 unsigned short ctrl;
925
926 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
927 ctrl = sci_in(port, SCSCR);
928 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
929 sci_out(port, SCSCR, ctrl);
930 }
931
932 static void sci_enable_ms(struct uart_port *port)
933 {
934 /* Nothing here yet .. */
935 }
936
937 static void sci_break_ctl(struct uart_port *port, int break_state)
938 {
939 /* Nothing here yet .. */
940 }
941
942 static int sci_startup(struct uart_port *port)
943 {
944 struct sci_port *s = &sci_ports[port->line];
945
946 if (s->enable)
947 s->enable(port);
948
949 sci_request_irq(s);
950 sci_start_tx(port);
951 sci_start_rx(port, 1);
952
953 return 0;
954 }
955
956 static void sci_shutdown(struct uart_port *port)
957 {
958 struct sci_port *s = &sci_ports[port->line];
959
960 sci_stop_rx(port);
961 sci_stop_tx(port);
962 sci_free_irq(s);
963
964 if (s->disable)
965 s->disable(port);
966 }
967
968 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
969 struct ktermios *old)
970 {
971 struct sci_port *s = &sci_ports[port->line];
972 unsigned int status, baud, smr_val;
973 unsigned long flags;
974 int t;
975
976 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
977
978 switch (baud) {
979 case 0:
980 t = -1;
981 break;
982 default:
983 {
984 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
985 struct clk *clk = clk_get(NULL, "module_clk");
986 t = SCBRR_VALUE(baud, clk_get_rate(clk));
987 clk_put(clk);
988 #else
989 t = SCBRR_VALUE(baud);
990 #endif
991 }
992 break;
993 }
994
995 spin_lock_irqsave(&port->lock, flags);
996
997 do {
998 status = sci_in(port, SCxSR);
999 } while (!(status & SCxSR_TEND(port)));
1000
1001 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1002
1003 #if !defined(SCI_ONLY)
1004 if (port->type == PORT_SCIF)
1005 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1006 #endif
1007
1008 smr_val = sci_in(port, SCSMR) & 3;
1009 if ((termios->c_cflag & CSIZE) == CS7)
1010 smr_val |= 0x40;
1011 if (termios->c_cflag & PARENB)
1012 smr_val |= 0x20;
1013 if (termios->c_cflag & PARODD)
1014 smr_val |= 0x30;
1015 if (termios->c_cflag & CSTOPB)
1016 smr_val |= 0x08;
1017
1018 uart_update_timeout(port, termios->c_cflag, baud);
1019
1020 sci_out(port, SCSMR, smr_val);
1021
1022 if (t > 0) {
1023 if(t >= 256) {
1024 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1025 t >>= 2;
1026 } else {
1027 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1028 }
1029 sci_out(port, SCBRR, t);
1030 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1031 }
1032
1033 if (likely(s->init_pins))
1034 s->init_pins(port, termios->c_cflag);
1035
1036 sci_out(port, SCSCR, SCSCR_INIT(port));
1037
1038 if ((termios->c_cflag & CREAD) != 0)
1039 sci_start_rx(port,0);
1040
1041 spin_unlock_irqrestore(&port->lock, flags);
1042 }
1043
1044 static const char *sci_type(struct uart_port *port)
1045 {
1046 switch (port->type) {
1047 case PORT_SCI: return "sci";
1048 case PORT_SCIF: return "scif";
1049 case PORT_IRDA: return "irda";
1050 }
1051
1052 return 0;
1053 }
1054
1055 static void sci_release_port(struct uart_port *port)
1056 {
1057 /* Nothing here yet .. */
1058 }
1059
1060 static int sci_request_port(struct uart_port *port)
1061 {
1062 /* Nothing here yet .. */
1063 return 0;
1064 }
1065
1066 static void sci_config_port(struct uart_port *port, int flags)
1067 {
1068 struct sci_port *s = &sci_ports[port->line];
1069
1070 port->type = s->type;
1071
1072 switch (port->type) {
1073 case PORT_SCI:
1074 s->init_pins = sci_init_pins_sci;
1075 break;
1076 case PORT_SCIF:
1077 s->init_pins = sci_init_pins_scif;
1078 break;
1079 case PORT_IRDA:
1080 s->init_pins = sci_init_pins_irda;
1081 break;
1082 }
1083
1084 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1085 if (port->mapbase == 0)
1086 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1087
1088 port->membase = (void __iomem *)port->mapbase;
1089 #endif
1090 }
1091
1092 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1093 {
1094 struct sci_port *s = &sci_ports[port->line];
1095
1096 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1097 return -EINVAL;
1098 if (ser->baud_base < 2400)
1099 /* No paper tape reader for Mitch.. */
1100 return -EINVAL;
1101
1102 return 0;
1103 }
1104
1105 static struct uart_ops sci_uart_ops = {
1106 .tx_empty = sci_tx_empty,
1107 .set_mctrl = sci_set_mctrl,
1108 .get_mctrl = sci_get_mctrl,
1109 .start_tx = sci_start_tx,
1110 .stop_tx = sci_stop_tx,
1111 .stop_rx = sci_stop_rx,
1112 .enable_ms = sci_enable_ms,
1113 .break_ctl = sci_break_ctl,
1114 .startup = sci_startup,
1115 .shutdown = sci_shutdown,
1116 .set_termios = sci_set_termios,
1117 .type = sci_type,
1118 .release_port = sci_release_port,
1119 .request_port = sci_request_port,
1120 .config_port = sci_config_port,
1121 .verify_port = sci_verify_port,
1122 };
1123
1124 static void __init sci_init_ports(void)
1125 {
1126 static int first = 1;
1127 int i;
1128
1129 if (!first)
1130 return;
1131
1132 first = 0;
1133
1134 for (i = 0; i < SCI_NPORTS; i++) {
1135 sci_ports[i].port.ops = &sci_uart_ops;
1136 sci_ports[i].port.iotype = UPIO_MEM;
1137 sci_ports[i].port.line = i;
1138 sci_ports[i].port.fifosize = 1;
1139
1140 #if defined(__H8300H__) || defined(__H8300S__)
1141 #ifdef __H8300S__
1142 sci_ports[i].enable = h8300_sci_enable;
1143 sci_ports[i].disable = h8300_sci_disable;
1144 #endif
1145 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1146 #elif defined(CONFIG_SUPERH64)
1147 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1148 #else
1149 /*
1150 * XXX: We should use a proper SCI/SCIF clock
1151 */
1152 {
1153 struct clk *clk = clk_get(NULL, "module_clk");
1154 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1155 clk_put(clk);
1156 }
1157 #endif
1158
1159 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1160 sci_ports[i].break_timer.function = sci_break_timer;
1161
1162 init_timer(&sci_ports[i].break_timer);
1163 }
1164 }
1165
1166 int __init early_sci_setup(struct uart_port *port)
1167 {
1168 if (unlikely(port->line > SCI_NPORTS))
1169 return -ENODEV;
1170
1171 sci_init_ports();
1172
1173 sci_ports[port->line].port.membase = port->membase;
1174 sci_ports[port->line].port.mapbase = port->mapbase;
1175 sci_ports[port->line].port.type = port->type;
1176
1177 return 0;
1178 }
1179
1180 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1181 /*
1182 * Print a string to the serial port trying not to disturb
1183 * any possible real use of the port...
1184 */
1185 static void serial_console_write(struct console *co, const char *s,
1186 unsigned count)
1187 {
1188 put_string(serial_console_port, s, count);
1189 }
1190
1191 static int __init serial_console_setup(struct console *co, char *options)
1192 {
1193 struct uart_port *port;
1194 int baud = 115200;
1195 int bits = 8;
1196 int parity = 'n';
1197 int flow = 'n';
1198 int ret;
1199
1200 /*
1201 * Check whether an invalid uart number has been specified, and
1202 * if so, search for the first available port that does have
1203 * console support.
1204 */
1205 if (co->index >= SCI_NPORTS)
1206 co->index = 0;
1207
1208 serial_console_port = &sci_ports[co->index];
1209 port = &serial_console_port->port;
1210
1211 /*
1212 * Also need to check port->type, we don't actually have any
1213 * UPIO_PORT ports, but uart_report_port() handily misreports
1214 * it anyways if we don't have a port available by the time this is
1215 * called.
1216 */
1217 if (!port->type)
1218 return -ENODEV;
1219 if (!port->membase || !port->mapbase)
1220 return -ENODEV;
1221
1222 spin_lock_init(&port->lock);
1223
1224 port->type = serial_console_port->type;
1225
1226 if (port->flags & UPF_IOREMAP)
1227 sci_config_port(port, 0);
1228
1229 if (serial_console_port->enable)
1230 serial_console_port->enable(port);
1231
1232 if (options)
1233 uart_parse_options(options, &baud, &parity, &bits, &flow);
1234
1235 ret = uart_set_options(port, co, baud, parity, bits, flow);
1236 #if defined(__H8300H__) || defined(__H8300S__)
1237 /* disable rx interrupt */
1238 if (ret == 0)
1239 sci_stop_rx(port);
1240 #endif
1241 return ret;
1242 }
1243
1244 static struct console serial_console = {
1245 .name = "ttySC",
1246 .device = uart_console_device,
1247 .write = serial_console_write,
1248 .setup = serial_console_setup,
1249 .flags = CON_PRINTBUFFER,
1250 .index = -1,
1251 .data = &sci_uart_driver,
1252 };
1253
1254 static int __init sci_console_init(void)
1255 {
1256 sci_init_ports();
1257 register_console(&serial_console);
1258 return 0;
1259 }
1260 console_initcall(sci_console_init);
1261 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1262
1263 #ifdef CONFIG_SH_KGDB
1264 /*
1265 * FIXME: Most of this can go away.. at the moment, we rely on
1266 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1267 * most of that can easily be done here instead.
1268 *
1269 * For the time being, just accept the values that were parsed earlier..
1270 */
1271 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1272 int *parity, int *bits)
1273 {
1274 *baud = kgdb_baud;
1275 *parity = tolower(kgdb_parity);
1276 *bits = kgdb_bits - '0';
1277 }
1278
1279 /*
1280 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1281 * care of the early-on initialization for kgdb, regardless of whether we
1282 * actually use kgdb as a console or not.
1283 *
1284 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1285 */
1286 int __init kgdb_console_setup(struct console *co, char *options)
1287 {
1288 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1289 int baud = 38400;
1290 int bits = 8;
1291 int parity = 'n';
1292 int flow = 'n';
1293
1294 spin_lock_init(&port->lock);
1295
1296 if (co->index != kgdb_portnum)
1297 co->index = kgdb_portnum;
1298
1299 if (options)
1300 uart_parse_options(options, &baud, &parity, &bits, &flow);
1301 else
1302 kgdb_console_get_options(port, &baud, &parity, &bits);
1303
1304 kgdb_getchar = kgdb_sci_getchar;
1305 kgdb_putchar = kgdb_sci_putchar;
1306
1307 return uart_set_options(port, co, baud, parity, bits, flow);
1308 }
1309 #endif /* CONFIG_SH_KGDB */
1310
1311 #ifdef CONFIG_SH_KGDB_CONSOLE
1312 static struct console kgdb_console = {
1313 .name = "ttySC",
1314 .write = kgdb_console_write,
1315 .setup = kgdb_console_setup,
1316 .flags = CON_PRINTBUFFER | CON_ENABLED,
1317 .index = -1,
1318 .data = &sci_uart_driver,
1319 };
1320
1321 /* Register the KGDB console so we get messages (d'oh!) */
1322 static int __init kgdb_console_init(void)
1323 {
1324 sci_init_ports();
1325 register_console(&kgdb_console);
1326 return 0;
1327 }
1328 console_initcall(kgdb_console_init);
1329 #endif /* CONFIG_SH_KGDB_CONSOLE */
1330
1331 #if defined(CONFIG_SH_KGDB_CONSOLE)
1332 #define SCI_CONSOLE &kgdb_console
1333 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1334 #define SCI_CONSOLE &serial_console
1335 #else
1336 #define SCI_CONSOLE 0
1337 #endif
1338
1339 static char banner[] __initdata =
1340 KERN_INFO "SuperH SCI(F) driver initialized\n";
1341
1342 static struct uart_driver sci_uart_driver = {
1343 .owner = THIS_MODULE,
1344 .driver_name = "sci",
1345 .dev_name = "ttySC",
1346 .major = SCI_MAJOR,
1347 .minor = SCI_MINOR_START,
1348 .nr = SCI_NPORTS,
1349 .cons = SCI_CONSOLE,
1350 };
1351
1352 /*
1353 * Register a set of serial devices attached to a platform device. The
1354 * list is terminated with a zero flags entry, which means we expect
1355 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1356 * remapping (such as sh64) should also set UPF_IOREMAP.
1357 */
1358 static int __devinit sci_probe(struct platform_device *dev)
1359 {
1360 struct plat_sci_port *p = dev->dev.platform_data;
1361 int i;
1362
1363 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1364 struct sci_port *sciport = &sci_ports[i];
1365
1366 sciport->port.mapbase = p->mapbase;
1367
1368 /*
1369 * For the simple (and majority of) cases where we don't need
1370 * to do any remapping, just cast the cookie directly.
1371 */
1372 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1373 p->membase = (void __iomem *)p->mapbase;
1374
1375 sciport->port.membase = p->membase;
1376
1377 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1378 sciport->port.flags = p->flags;
1379 sciport->port.dev = &dev->dev;
1380
1381 sciport->type = sciport->port.type = p->type;
1382
1383 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1384
1385 uart_add_one_port(&sci_uart_driver, &sciport->port);
1386 }
1387
1388 #ifdef CONFIG_CPU_FREQ
1389 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1390 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1391 #endif
1392
1393 #ifdef CONFIG_SH_STANDARD_BIOS
1394 sh_bios_gdb_detach();
1395 #endif
1396
1397 return 0;
1398 }
1399
1400 static int __devexit sci_remove(struct platform_device *dev)
1401 {
1402 int i;
1403
1404 for (i = 0; i < SCI_NPORTS; i++)
1405 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1406
1407 return 0;
1408 }
1409
1410 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1411 {
1412 int i;
1413
1414 for (i = 0; i < SCI_NPORTS; i++) {
1415 struct sci_port *p = &sci_ports[i];
1416
1417 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1418 uart_suspend_port(&sci_uart_driver, &p->port);
1419 }
1420
1421 return 0;
1422 }
1423
1424 static int sci_resume(struct platform_device *dev)
1425 {
1426 int i;
1427
1428 for (i = 0; i < SCI_NPORTS; i++) {
1429 struct sci_port *p = &sci_ports[i];
1430
1431 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1432 uart_resume_port(&sci_uart_driver, &p->port);
1433 }
1434
1435 return 0;
1436 }
1437
1438 static struct platform_driver sci_driver = {
1439 .probe = sci_probe,
1440 .remove = __devexit_p(sci_remove),
1441 .suspend = sci_suspend,
1442 .resume = sci_resume,
1443 .driver = {
1444 .name = "sh-sci",
1445 .owner = THIS_MODULE,
1446 },
1447 };
1448
1449 static int __init sci_init(void)
1450 {
1451 int ret;
1452
1453 printk(banner);
1454
1455 sci_init_ports();
1456
1457 ret = uart_register_driver(&sci_uart_driver);
1458 if (likely(ret == 0)) {
1459 ret = platform_driver_register(&sci_driver);
1460 if (unlikely(ret))
1461 uart_unregister_driver(&sci_uart_driver);
1462 }
1463
1464 return ret;
1465 }
1466
1467 static void __exit sci_exit(void)
1468 {
1469 platform_driver_unregister(&sci_driver);
1470 uart_unregister_driver(&sci_uart_driver);
1471 }
1472
1473 module_init(sci_init);
1474 module_exit(sci_exit);
1475
1476 MODULE_LICENSE("GPL");
linux kernel for loongson