arch/arm/mach-lh7a40x/irq-lh7a404.c

   1 /* arch/arm/mach-lh7a40x/irq-lh7a404.c
   2  *
   3  *  Copyright (C) 2004 Logic Product Development
   4  *
   5  *  This program is free software; you can redistribute it and/or
   6  *  modify it under the terms of the GNU General Public License
   7  *  version 2 as published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/ptrace.h>
  15
  16 #include <asm/hardware.h>
  17 #include <asm/irq.h>
  18 #include <asm/mach/irq.h>
  19 #include <asm/arch/irqs.h>
  20
  21 #include "common.h"
  22
  23 #define USE_PRIORITIES
  24
  25 /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
  26  * information on using the vectored interrupt controller's
  27  * prioritizing feature. */
  28
  29 static unsigned char irq_pri_vic1[] = {
  30 #if defined (USE_PRIORITIES)
  31 IRQ_GPIO3INTR,
  32 #endif
  33 };
  34 static unsigned char irq_pri_vic2[] = {
  35 #if defined (USE_PRIORITIES)
  36         IRQ_T3UI, IRQ_GPIO7INTR,
  37         IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
  38 #endif
  39 };
  40
  41   /* CPU IRQ handling */
  42
  43 static void lh7a404_vic1_mask_irq (u32 irq)
  44 {
  45         VIC1_INTENCLR = (1 << irq);
  46 }
  47
  48 static void lh7a404_vic1_unmask_irq (u32 irq)
  49 {
  50         VIC1_INTEN = (1 << irq);
  51 }
  52
  53 static void lh7a404_vic2_mask_irq (u32 irq)
  54 {
  55         VIC2_INTENCLR = (1 << (irq - 32));
  56 }
  57
  58 static void lh7a404_vic2_unmask_irq (u32 irq)
  59 {
  60         VIC2_INTEN = (1 << (irq - 32));
  61 }
  62
  63 static void lh7a404_vic1_ack_gpio_irq (u32 irq)
  64 {
  65         GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  66         VIC1_INTENCLR = (1 << irq);
  67 }
  68
  69 static void lh7a404_vic2_ack_gpio_irq (u32 irq)
  70 {
  71         GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  72         VIC2_INTENCLR = (1 << irq);
  73 }
  74
  75 static struct irqchip lh7a404_vic1_chip = {
  76         .ack    = lh7a404_vic1_mask_irq, /* Because level-triggered */
  77         .mask   = lh7a404_vic1_mask_irq,
  78         .unmask = lh7a404_vic1_unmask_irq,
  79 };
  80
  81 static struct irqchip lh7a404_vic2_chip = {
  82         .ack    = lh7a404_vic2_mask_irq, /* Because level-triggered */
  83         .mask   = lh7a404_vic2_mask_irq,
  84         .unmask = lh7a404_vic2_unmask_irq,
  85 };
  86
  87 static struct irqchip lh7a404_gpio_vic1_chip = {
  88         .ack    = lh7a404_vic1_ack_gpio_irq,
  89         .mask   = lh7a404_vic1_mask_irq,
  90         .unmask = lh7a404_vic1_unmask_irq,
  91 };
  92
  93 static struct irqchip lh7a404_gpio_vic2_chip = {
  94         .ack    = lh7a404_vic2_ack_gpio_irq,
  95         .mask   = lh7a404_vic2_mask_irq,
  96         .unmask = lh7a404_vic2_unmask_irq,
  97 };
  98
  99   /* IRQ initialization */
 100
 101 void __init lh7a404_init_irq (void)
 102 {
 103         int irq;
 104
 105         VIC1_INTENCLR = 0xffffffff;
 106         VIC2_INTENCLR = 0xffffffff;
 107         VIC1_INTSEL = 0;                /* All IRQs */
 108         VIC2_INTSEL = 0;                /* All IRQs */
 109         VIC1_NVADDR = VA_VIC1DEFAULT;
 110         VIC2_NVADDR = VA_VIC2DEFAULT;
 111         VIC1_VECTADDR = 0;
 112         VIC2_VECTADDR = 0;
 113
 114         GPIO_GPIOFINTEN = 0x00;         /* Disable all GPIOF interrupts */
 115         barrier ();
 116
 117                 /* Install prioritized interrupts, if there are any. */
 118                 /* The | 0x20*/
 119         for (irq = 0; irq < 16; ++irq) {
 120                 (&VIC1_VAD0)[irq]
 121                         = (irq < ARRAY_SIZE (irq_pri_vic1))
 122                         ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
 123                 (&VIC1_VECTCNTL0)[irq]
 124                         = (irq < ARRAY_SIZE (irq_pri_vic1))
 125                         ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
 126                 (&VIC2_VAD0)[irq]
 127                         = (irq < ARRAY_SIZE (irq_pri_vic2))
 128                         ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
 129                 (&VIC2_VECTCNTL0)[irq]
 130                         = (irq < ARRAY_SIZE (irq_pri_vic2))
 131                         ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
 132         }
 133
 134         for (irq = 0; irq < NR_IRQS; ++irq) {
 135                 switch (irq) {
 136                 case IRQ_GPIO0INTR:
 137                 case IRQ_GPIO1INTR:
 138                 case IRQ_GPIO2INTR:
 139                 case IRQ_GPIO3INTR:
 140                 case IRQ_GPIO4INTR:
 141                 case IRQ_GPIO5INTR:
 142                 case IRQ_GPIO6INTR:
 143                 case IRQ_GPIO7INTR:
 144                         set_irq_chip (irq, irq < 32
 145                                       ? &lh7a404_gpio_vic1_chip
 146                                       : &lh7a404_gpio_vic2_chip);
 147                         set_irq_handler (irq, do_level_IRQ); /* OK default */
 148                         break;
 149                 default:
 150                         set_irq_chip (irq, irq < 32
 151                                       ? &lh7a404_vic1_chip
 152                                       : &lh7a404_vic2_chip);
 153                         set_irq_handler (irq, do_level_IRQ);
 154                 }
 155                 set_irq_flags (irq, IRQF_VALID);
 156         }
 157
 158         lh7a40x_init_board_irq ();
 159 }