[IB] mthca: Always re-arm EQs in mthca_tavor_interrupt()
[linux-2.6/linux-loongson.git] / drivers / infiniband / hw / mthca / mthca_eq.c
blob8dfafda5ed241c9c4269877704981f21f020673d
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
33 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
41 #include "mthca_dev.h"
42 #include "mthca_cmd.h"
43 #include "mthca_config_reg.h"
45 enum {
46 MTHCA_NUM_ASYNC_EQE = 0x80,
47 MTHCA_NUM_CMD_EQE = 0x80,
48 MTHCA_EQ_ENTRY_SIZE = 0x20
52 * Must be packed because start is 64 bits but only aligned to 32 bits.
54 struct mthca_eq_context {
55 __be32 flags;
56 __be64 start;
57 __be32 logsize_usrpage;
58 __be32 tavor_pd; /* reserved for Arbel */
59 u8 reserved1[3];
60 u8 intr;
61 __be32 arbel_pd; /* lost_count for Tavor */
62 __be32 lkey;
63 u32 reserved2[2];
64 __be32 consumer_index;
65 __be32 producer_index;
66 u32 reserved3[4];
67 } __attribute__((packed));
69 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
70 #define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
71 #define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
72 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
73 #define MTHCA_EQ_OWNER_HW ( 1 << 24)
74 #define MTHCA_EQ_FLAG_TR ( 1 << 18)
75 #define MTHCA_EQ_FLAG_OI ( 1 << 17)
76 #define MTHCA_EQ_STATE_ARMED ( 1 << 8)
77 #define MTHCA_EQ_STATE_FIRED ( 2 << 8)
78 #define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
79 #define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
81 enum {
82 MTHCA_EVENT_TYPE_COMP = 0x00,
83 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
84 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
85 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
86 MTHCA_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
87 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
88 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
89 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
90 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
91 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
92 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
93 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
94 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
95 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
96 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
97 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
98 MTHCA_EVENT_TYPE_CMD = 0x0a
101 #define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
102 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
103 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
104 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
105 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
106 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
107 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
108 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
109 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
110 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
111 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
112 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
113 #define MTHCA_SRQ_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
114 (1ULL << MTHCA_EVENT_TYPE_SRQ_LAST_WQE)
115 #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
117 #define MTHCA_EQ_DB_INC_CI (1 << 24)
118 #define MTHCA_EQ_DB_REQ_NOT (2 << 24)
119 #define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
120 #define MTHCA_EQ_DB_SET_CI (4 << 24)
121 #define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
123 struct mthca_eqe {
124 u8 reserved1;
125 u8 type;
126 u8 reserved2;
127 u8 subtype;
128 union {
129 u32 raw[6];
130 struct {
131 __be32 cqn;
132 } __attribute__((packed)) comp;
133 struct {
134 u16 reserved1;
135 __be16 token;
136 u32 reserved2;
137 u8 reserved3[3];
138 u8 status;
139 __be64 out_param;
140 } __attribute__((packed)) cmd;
141 struct {
142 __be32 qpn;
143 } __attribute__((packed)) qp;
144 struct {
145 __be32 cqn;
146 u32 reserved1;
147 u8 reserved2[3];
148 u8 syndrome;
149 } __attribute__((packed)) cq_err;
150 struct {
151 u32 reserved1[2];
152 __be32 port;
153 } __attribute__((packed)) port_change;
154 } event;
155 u8 reserved3[3];
156 u8 owner;
157 } __attribute__((packed));
159 #define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
160 #define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
162 static inline u64 async_mask(struct mthca_dev *dev)
164 return dev->mthca_flags & MTHCA_FLAG_SRQ ?
165 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
166 MTHCA_ASYNC_EVENT_MASK;
169 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
171 __be32 doorbell[2];
173 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn);
174 doorbell[1] = cpu_to_be32(ci & (eq->nent - 1));
177 * This barrier makes sure that all updates to ownership bits
178 * done by set_eqe_hw() hit memory before the consumer index
179 * is updated. set_eq_ci() allows the HCA to possibly write
180 * more EQ entries, and we want to avoid the exceedingly
181 * unlikely possibility of the HCA writing an entry and then
182 * having set_eqe_hw() overwrite the owner field.
184 wmb();
185 mthca_write64(doorbell,
186 dev->kar + MTHCA_EQ_DOORBELL,
187 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
190 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
192 /* See comment in tavor_set_eq_ci() above. */
193 wmb();
194 __raw_writel((__force u32) cpu_to_be32(ci),
195 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
196 /* We still want ordering, just not swabbing, so add a barrier */
197 mb();
200 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
202 if (mthca_is_memfree(dev))
203 arbel_set_eq_ci(dev, eq, ci);
204 else
205 tavor_set_eq_ci(dev, eq, ci);
208 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
210 __be32 doorbell[2];
212 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn);
213 doorbell[1] = 0;
215 mthca_write64(doorbell,
216 dev->kar + MTHCA_EQ_DOORBELL,
217 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
220 static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
222 writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
225 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
227 if (!mthca_is_memfree(dev)) {
228 __be32 doorbell[2];
230 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn);
231 doorbell[1] = cpu_to_be32(cqn);
233 mthca_write64(doorbell,
234 dev->kar + MTHCA_EQ_DOORBELL,
235 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
239 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
241 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
242 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
245 static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq)
247 struct mthca_eqe* eqe;
248 eqe = get_eqe(eq, eq->cons_index);
249 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
252 static inline void set_eqe_hw(struct mthca_eqe *eqe)
254 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
257 static void port_change(struct mthca_dev *dev, int port, int active)
259 struct ib_event record;
261 mthca_dbg(dev, "Port change to %s for port %d\n",
262 active ? "active" : "down", port);
264 record.device = &dev->ib_dev;
265 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
266 record.element.port_num = port;
268 ib_dispatch_event(&record);
271 static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
273 struct mthca_eqe *eqe;
274 int disarm_cqn;
275 int eqes_found = 0;
277 while ((eqe = next_eqe_sw(eq))) {
278 int set_ci = 0;
281 * Make sure we read EQ entry contents after we've
282 * checked the ownership bit.
284 rmb();
286 switch (eqe->type) {
287 case MTHCA_EVENT_TYPE_COMP:
288 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
289 disarm_cq(dev, eq->eqn, disarm_cqn);
290 mthca_cq_event(dev, disarm_cqn);
291 break;
293 case MTHCA_EVENT_TYPE_PATH_MIG:
294 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
295 IB_EVENT_PATH_MIG);
296 break;
298 case MTHCA_EVENT_TYPE_COMM_EST:
299 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
300 IB_EVENT_COMM_EST);
301 break;
303 case MTHCA_EVENT_TYPE_SQ_DRAINED:
304 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
305 IB_EVENT_SQ_DRAINED);
306 break;
308 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
309 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
310 IB_EVENT_QP_FATAL);
311 break;
313 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
314 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
315 IB_EVENT_PATH_MIG_ERR);
316 break;
318 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
319 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
320 IB_EVENT_QP_REQ_ERR);
321 break;
323 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
324 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
325 IB_EVENT_QP_ACCESS_ERR);
326 break;
328 case MTHCA_EVENT_TYPE_CMD:
329 mthca_cmd_event(dev,
330 be16_to_cpu(eqe->event.cmd.token),
331 eqe->event.cmd.status,
332 be64_to_cpu(eqe->event.cmd.out_param));
334 * cmd_event() may add more commands.
335 * The card will think the queue has overflowed if
336 * we don't tell it we've been processing events.
338 set_ci = 1;
339 break;
341 case MTHCA_EVENT_TYPE_PORT_CHANGE:
342 port_change(dev,
343 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
344 eqe->subtype == 0x4);
345 break;
347 case MTHCA_EVENT_TYPE_CQ_ERROR:
348 mthca_warn(dev, "CQ %s on CQN %06x\n",
349 eqe->event.cq_err.syndrome == 1 ?
350 "overrun" : "access violation",
351 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
352 break;
354 case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
355 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
356 break;
358 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
359 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
360 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
361 case MTHCA_EVENT_TYPE_ECC_DETECT:
362 default:
363 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
364 eqe->type, eqe->subtype, eq->eqn);
365 break;
368 set_eqe_hw(eqe);
369 ++eq->cons_index;
370 eqes_found = 1;
372 if (unlikely(set_ci)) {
374 * Conditional on hca_type is OK here because
375 * this is a rare case, not the fast path.
377 set_eq_ci(dev, eq, eq->cons_index);
378 set_ci = 0;
383 * Rely on caller to set consumer index so that we don't have
384 * to test hca_type in our interrupt handling fast path.
386 return eqes_found;
389 static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
391 struct mthca_dev *dev = dev_ptr;
392 u32 ecr;
393 int i;
395 if (dev->eq_table.clr_mask)
396 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
398 ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
399 if (!ecr)
400 return IRQ_NONE;
402 writel(ecr, dev->eq_regs.tavor.ecr_base +
403 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
405 for (i = 0; i < MTHCA_NUM_EQ; ++i)
406 if (ecr & dev->eq_table.eq[i].eqn_mask) {
407 if (mthca_eq_int(dev, &dev->eq_table.eq[i]))
408 tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
409 dev->eq_table.eq[i].cons_index);
410 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
413 return IRQ_HANDLED;
416 static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr,
417 struct pt_regs *regs)
419 struct mthca_eq *eq = eq_ptr;
420 struct mthca_dev *dev = eq->dev;
422 mthca_eq_int(dev, eq);
423 tavor_set_eq_ci(dev, eq, eq->cons_index);
424 tavor_eq_req_not(dev, eq->eqn);
426 /* MSI-X vectors always belong to us */
427 return IRQ_HANDLED;
430 static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
432 struct mthca_dev *dev = dev_ptr;
433 int work = 0;
434 int i;
436 if (dev->eq_table.clr_mask)
437 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
439 for (i = 0; i < MTHCA_NUM_EQ; ++i)
440 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
441 work = 1;
442 arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
443 dev->eq_table.eq[i].cons_index);
446 arbel_eq_req_not(dev, dev->eq_table.arm_mask);
448 return IRQ_RETVAL(work);
451 static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr,
452 struct pt_regs *regs)
454 struct mthca_eq *eq = eq_ptr;
455 struct mthca_dev *dev = eq->dev;
457 mthca_eq_int(dev, eq);
458 arbel_set_eq_ci(dev, eq, eq->cons_index);
459 arbel_eq_req_not(dev, eq->eqn_mask);
461 /* MSI-X vectors always belong to us */
462 return IRQ_HANDLED;
465 static int __devinit mthca_create_eq(struct mthca_dev *dev,
466 int nent,
467 u8 intr,
468 struct mthca_eq *eq)
470 int npages = (nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
471 PAGE_SIZE;
472 u64 *dma_list = NULL;
473 dma_addr_t t;
474 struct mthca_mailbox *mailbox;
475 struct mthca_eq_context *eq_context;
476 int err = -ENOMEM;
477 int i;
478 u8 status;
480 eq->dev = dev;
481 eq->nent = roundup_pow_of_two(max(nent, 2));
483 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
484 GFP_KERNEL);
485 if (!eq->page_list)
486 goto err_out;
488 for (i = 0; i < npages; ++i)
489 eq->page_list[i].buf = NULL;
491 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
492 if (!dma_list)
493 goto err_out_free;
495 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
496 if (IS_ERR(mailbox))
497 goto err_out_free;
498 eq_context = mailbox->buf;
500 for (i = 0; i < npages; ++i) {
501 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
502 PAGE_SIZE, &t, GFP_KERNEL);
503 if (!eq->page_list[i].buf)
504 goto err_out_free_pages;
506 dma_list[i] = t;
507 pci_unmap_addr_set(&eq->page_list[i], mapping, t);
509 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
512 for (i = 0; i < eq->nent; ++i)
513 set_eqe_hw(get_eqe(eq, i));
515 eq->eqn = mthca_alloc(&dev->eq_table.alloc);
516 if (eq->eqn == -1)
517 goto err_out_free_pages;
519 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
520 dma_list, PAGE_SHIFT, npages,
521 0, npages * PAGE_SIZE,
522 MTHCA_MPT_FLAG_LOCAL_WRITE |
523 MTHCA_MPT_FLAG_LOCAL_READ,
524 &eq->mr);
525 if (err)
526 goto err_out_free_eq;
528 memset(eq_context, 0, sizeof *eq_context);
529 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
530 MTHCA_EQ_OWNER_HW |
531 MTHCA_EQ_STATE_ARMED |
532 MTHCA_EQ_FLAG_TR);
533 if (mthca_is_memfree(dev))
534 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
536 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24);
537 if (mthca_is_memfree(dev)) {
538 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
539 } else {
540 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
541 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
543 eq_context->intr = intr;
544 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
546 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status);
547 if (err) {
548 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
549 goto err_out_free_mr;
551 if (status) {
552 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
553 status);
554 err = -EINVAL;
555 goto err_out_free_mr;
558 kfree(dma_list);
559 mthca_free_mailbox(dev, mailbox);
561 eq->eqn_mask = swab32(1 << eq->eqn);
562 eq->cons_index = 0;
564 dev->eq_table.arm_mask |= eq->eqn_mask;
566 mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
567 eq->eqn, eq->nent);
569 return err;
571 err_out_free_mr:
572 mthca_free_mr(dev, &eq->mr);
574 err_out_free_eq:
575 mthca_free(&dev->eq_table.alloc, eq->eqn);
577 err_out_free_pages:
578 for (i = 0; i < npages; ++i)
579 if (eq->page_list[i].buf)
580 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
581 eq->page_list[i].buf,
582 pci_unmap_addr(&eq->page_list[i],
583 mapping));
585 mthca_free_mailbox(dev, mailbox);
587 err_out_free:
588 kfree(eq->page_list);
589 kfree(dma_list);
591 err_out:
592 return err;
595 static void mthca_free_eq(struct mthca_dev *dev,
596 struct mthca_eq *eq)
598 struct mthca_mailbox *mailbox;
599 int err;
600 u8 status;
601 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
602 PAGE_SIZE;
603 int i;
605 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
606 if (IS_ERR(mailbox))
607 return;
609 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status);
610 if (err)
611 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
612 if (status)
613 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
615 dev->eq_table.arm_mask &= ~eq->eqn_mask;
617 if (0) {
618 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
619 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
620 if (i % 4 == 0)
621 printk("[%02x] ", i * 4);
622 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
623 if ((i + 1) % 4 == 0)
624 printk("\n");
628 mthca_free_mr(dev, &eq->mr);
629 for (i = 0; i < npages; ++i)
630 pci_free_consistent(dev->pdev, PAGE_SIZE,
631 eq->page_list[i].buf,
632 pci_unmap_addr(&eq->page_list[i], mapping));
634 kfree(eq->page_list);
635 mthca_free_mailbox(dev, mailbox);
638 static void mthca_free_irqs(struct mthca_dev *dev)
640 int i;
642 if (dev->eq_table.have_irq)
643 free_irq(dev->pdev->irq, dev);
644 for (i = 0; i < MTHCA_NUM_EQ; ++i)
645 if (dev->eq_table.eq[i].have_irq)
646 free_irq(dev->eq_table.eq[i].msi_x_vector,
647 dev->eq_table.eq + i);
650 static int __devinit mthca_map_reg(struct mthca_dev *dev,
651 unsigned long offset, unsigned long size,
652 void __iomem **map)
654 unsigned long base = pci_resource_start(dev->pdev, 0);
656 if (!request_mem_region(base + offset, size, DRV_NAME))
657 return -EBUSY;
659 *map = ioremap(base + offset, size);
660 if (!*map) {
661 release_mem_region(base + offset, size);
662 return -ENOMEM;
665 return 0;
668 static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
669 unsigned long size, void __iomem *map)
671 unsigned long base = pci_resource_start(dev->pdev, 0);
673 release_mem_region(base + offset, size);
674 iounmap(map);
677 static int __devinit mthca_map_eq_regs(struct mthca_dev *dev)
679 unsigned long mthca_base;
681 mthca_base = pci_resource_start(dev->pdev, 0);
683 if (mthca_is_memfree(dev)) {
685 * We assume that the EQ arm and EQ set CI registers
686 * fall within the first BAR. We can't trust the
687 * values firmware gives us, since those addresses are
688 * valid on the HCA's side of the PCI bus but not
689 * necessarily the host side.
691 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
692 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
693 &dev->clr_base)) {
694 mthca_err(dev, "Couldn't map interrupt clear register, "
695 "aborting.\n");
696 return -ENOMEM;
700 * Add 4 because we limit ourselves to EQs 0 ... 31,
701 * so we only need the low word of the register.
703 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
704 dev->fw.arbel.eq_arm_base) + 4, 4,
705 &dev->eq_regs.arbel.eq_arm)) {
706 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
707 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
708 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
709 dev->clr_base);
710 return -ENOMEM;
713 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
714 dev->fw.arbel.eq_set_ci_base,
715 MTHCA_EQ_SET_CI_SIZE,
716 &dev->eq_regs.arbel.eq_set_ci_base)) {
717 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
718 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
719 dev->fw.arbel.eq_arm_base) + 4, 4,
720 dev->eq_regs.arbel.eq_arm);
721 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
722 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
723 dev->clr_base);
724 return -ENOMEM;
726 } else {
727 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
728 &dev->clr_base)) {
729 mthca_err(dev, "Couldn't map interrupt clear register, "
730 "aborting.\n");
731 return -ENOMEM;
734 if (mthca_map_reg(dev, MTHCA_ECR_BASE,
735 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
736 &dev->eq_regs.tavor.ecr_base)) {
737 mthca_err(dev, "Couldn't map ecr register, "
738 "aborting.\n");
739 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
740 dev->clr_base);
741 return -ENOMEM;
745 return 0;
749 static void __devexit mthca_unmap_eq_regs(struct mthca_dev *dev)
751 if (mthca_is_memfree(dev)) {
752 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
753 dev->fw.arbel.eq_set_ci_base,
754 MTHCA_EQ_SET_CI_SIZE,
755 dev->eq_regs.arbel.eq_set_ci_base);
756 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
757 dev->fw.arbel.eq_arm_base) + 4, 4,
758 dev->eq_regs.arbel.eq_arm);
759 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
760 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
761 dev->clr_base);
762 } else {
763 mthca_unmap_reg(dev, MTHCA_ECR_BASE,
764 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
765 dev->eq_regs.tavor.ecr_base);
766 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
767 dev->clr_base);
771 int __devinit mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
773 int ret;
774 u8 status;
777 * We assume that mapping one page is enough for the whole EQ
778 * context table. This is fine with all current HCAs, because
779 * we only use 32 EQs and each EQ uses 32 bytes of context
780 * memory, or 1 KB total.
782 dev->eq_table.icm_virt = icm_virt;
783 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
784 if (!dev->eq_table.icm_page)
785 return -ENOMEM;
786 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
787 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
788 if (pci_dma_mapping_error(dev->eq_table.icm_dma)) {
789 __free_page(dev->eq_table.icm_page);
790 return -ENOMEM;
793 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
794 if (!ret && status)
795 ret = -EINVAL;
796 if (ret) {
797 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
798 PCI_DMA_BIDIRECTIONAL);
799 __free_page(dev->eq_table.icm_page);
802 return ret;
805 void __devexit mthca_unmap_eq_icm(struct mthca_dev *dev)
807 u8 status;
809 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, PAGE_SIZE / 4096, &status);
810 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
811 PCI_DMA_BIDIRECTIONAL);
812 __free_page(dev->eq_table.icm_page);
815 int __devinit mthca_init_eq_table(struct mthca_dev *dev)
817 int err;
818 u8 status;
819 u8 intr;
820 int i;
822 err = mthca_alloc_init(&dev->eq_table.alloc,
823 dev->limits.num_eqs,
824 dev->limits.num_eqs - 1,
825 dev->limits.reserved_eqs);
826 if (err)
827 return err;
829 err = mthca_map_eq_regs(dev);
830 if (err)
831 goto err_out_free;
833 if (dev->mthca_flags & MTHCA_FLAG_MSI ||
834 dev->mthca_flags & MTHCA_FLAG_MSI_X) {
835 dev->eq_table.clr_mask = 0;
836 } else {
837 dev->eq_table.clr_mask =
838 swab32(1 << (dev->eq_table.inta_pin & 31));
839 dev->eq_table.clr_int = dev->clr_base +
840 (dev->eq_table.inta_pin < 32 ? 4 : 0);
843 dev->eq_table.arm_mask = 0;
845 intr = (dev->mthca_flags & MTHCA_FLAG_MSI) ?
846 128 : dev->eq_table.inta_pin;
848 err = mthca_create_eq(dev, dev->limits.num_cqs,
849 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
850 &dev->eq_table.eq[MTHCA_EQ_COMP]);
851 if (err)
852 goto err_out_unmap;
854 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE,
855 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
856 &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
857 if (err)
858 goto err_out_comp;
860 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE,
861 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
862 &dev->eq_table.eq[MTHCA_EQ_CMD]);
863 if (err)
864 goto err_out_async;
866 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
867 static const char *eq_name[] = {
868 [MTHCA_EQ_COMP] = DRV_NAME " (comp)",
869 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
870 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
873 for (i = 0; i < MTHCA_NUM_EQ; ++i) {
874 err = request_irq(dev->eq_table.eq[i].msi_x_vector,
875 mthca_is_memfree(dev) ?
876 mthca_arbel_msi_x_interrupt :
877 mthca_tavor_msi_x_interrupt,
878 0, eq_name[i], dev->eq_table.eq + i);
879 if (err)
880 goto err_out_cmd;
881 dev->eq_table.eq[i].have_irq = 1;
883 } else {
884 err = request_irq(dev->pdev->irq,
885 mthca_is_memfree(dev) ?
886 mthca_arbel_interrupt :
887 mthca_tavor_interrupt,
888 SA_SHIRQ, DRV_NAME, dev);
889 if (err)
890 goto err_out_cmd;
891 dev->eq_table.have_irq = 1;
894 err = mthca_MAP_EQ(dev, async_mask(dev),
895 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
896 if (err)
897 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
898 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
899 if (status)
900 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
901 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
903 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
904 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
905 if (err)
906 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
907 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
908 if (status)
909 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
910 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
912 for (i = 0; i < MTHCA_EQ_CMD; ++i)
913 if (mthca_is_memfree(dev))
914 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
915 else
916 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
918 return 0;
920 err_out_cmd:
921 mthca_free_irqs(dev);
922 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
924 err_out_async:
925 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
927 err_out_comp:
928 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
930 err_out_unmap:
931 mthca_unmap_eq_regs(dev);
933 err_out_free:
934 mthca_alloc_cleanup(&dev->eq_table.alloc);
935 return err;
938 void __devexit mthca_cleanup_eq_table(struct mthca_dev *dev)
940 u8 status;
941 int i;
943 mthca_free_irqs(dev);
945 mthca_MAP_EQ(dev, async_mask(dev),
946 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
947 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
948 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
950 for (i = 0; i < MTHCA_NUM_EQ; ++i)
951 mthca_free_eq(dev, &dev->eq_table.eq[i]);
953 mthca_unmap_eq_regs(dev);
955 mthca_alloc_cleanup(&dev->eq_table.alloc);