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Linux 2.6.26
[linux-2.6/linux-loongson.git] / drivers / char / drm / radeon_drv.h
blob3f0eca957aa7cfff93640a7db1bedab8f02016b3
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
102 */
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
106
107 /*
108 * Radeon chip families
109 */
110 enum radeon_family {
111 CHIP_R100,
112 CHIP_RV100,
113 CHIP_RS100,
114 CHIP_RV200,
115 CHIP_RS200,
116 CHIP_R200,
117 CHIP_RV250,
118 CHIP_RS300,
119 CHIP_RV280,
120 CHIP_R300,
121 CHIP_R350,
122 CHIP_RV350,
123 CHIP_RV380,
124 CHIP_R420,
125 CHIP_RV410,
126 CHIP_RS480,
127 CHIP_RS690,
128 CHIP_RV515,
129 CHIP_R520,
130 CHIP_RV530,
131 CHIP_RV560,
132 CHIP_RV570,
133 CHIP_R580,
134 CHIP_LAST,
135 };
136
137 enum radeon_cp_microcode_version {
138 UCODE_R100,
139 UCODE_R200,
140 UCODE_R300,
141 };
142
143 /*
144 * Chip flags
145 */
146 enum radeon_chip_flags {
147 RADEON_FAMILY_MASK = 0x0000ffffUL,
148 RADEON_FLAGS_MASK = 0xffff0000UL,
149 RADEON_IS_MOBILITY = 0x00010000UL,
150 RADEON_IS_IGP = 0x00020000UL,
151 RADEON_SINGLE_CRTC = 0x00040000UL,
152 RADEON_IS_AGP = 0x00080000UL,
153 RADEON_HAS_HIERZ = 0x00100000UL,
154 RADEON_IS_PCIE = 0x00200000UL,
155 RADEON_NEW_MEMMAP = 0x00400000UL,
156 RADEON_IS_PCI = 0x00800000UL,
157 RADEON_IS_IGPGART = 0x01000000UL,
158 };
159
160 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
161 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
162 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
163
164 typedef struct drm_radeon_freelist {
165 unsigned int age;
166 struct drm_buf *buf;
167 struct drm_radeon_freelist *next;
168 struct drm_radeon_freelist *prev;
169 } drm_radeon_freelist_t;
170
171 typedef struct drm_radeon_ring_buffer {
172 u32 *start;
173 u32 *end;
174 int size;
175 int size_l2qw;
176
177 int rptr_update; /* Double Words */
178 int rptr_update_l2qw; /* log2 Quad Words */
179
180 int fetch_size; /* Double Words */
181 int fetch_size_l2ow; /* log2 Oct Words */
182
183 u32 tail;
184 u32 tail_mask;
185 int space;
186
187 int high_mark;
188 } drm_radeon_ring_buffer_t;
189
190 typedef struct drm_radeon_depth_clear_t {
191 u32 rb3d_cntl;
192 u32 rb3d_zstencilcntl;
193 u32 se_cntl;
194 } drm_radeon_depth_clear_t;
195
196 struct drm_radeon_driver_file_fields {
197 int64_t radeon_fb_delta;
198 };
199
200 struct mem_block {
201 struct mem_block *next;
202 struct mem_block *prev;
203 int start;
204 int size;
205 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
206 };
207
208 struct radeon_surface {
209 int refcount;
210 u32 lower;
211 u32 upper;
212 u32 flags;
213 };
214
215 struct radeon_virt_surface {
216 int surface_index;
217 u32 lower;
218 u32 upper;
219 u32 flags;
220 struct drm_file *file_priv;
221 };
222
223 typedef struct drm_radeon_private {
224 drm_radeon_ring_buffer_t ring;
225 drm_radeon_sarea_t *sarea_priv;
226
227 u32 fb_location;
228 u32 fb_size;
229 int new_memmap;
230
231 int gart_size;
232 u32 gart_vm_start;
233 unsigned long gart_buffers_offset;
234
235 int cp_mode;
236 int cp_running;
237
238 drm_radeon_freelist_t *head;
239 drm_radeon_freelist_t *tail;
240 int last_buf;
241 volatile u32 *scratch;
242 int writeback_works;
243
244 int usec_timeout;
245
246 int microcode_version;
247
248 struct {
249 u32 boxes;
250 int freelist_timeouts;
251 int freelist_loops;
252 int requested_bufs;
253 int last_frame_reads;
254 int last_clear_reads;
255 int clears;
256 int texture_uploads;
257 } stats;
258
259 int do_boxes;
260 int page_flipping;
261
262 u32 color_fmt;
263 unsigned int front_offset;
264 unsigned int front_pitch;
265 unsigned int back_offset;
266 unsigned int back_pitch;
267
268 u32 depth_fmt;
269 unsigned int depth_offset;
270 unsigned int depth_pitch;
271
272 u32 front_pitch_offset;
273 u32 back_pitch_offset;
274 u32 depth_pitch_offset;
275
276 drm_radeon_depth_clear_t depth_clear;
277
278 unsigned long ring_offset;
279 unsigned long ring_rptr_offset;
280 unsigned long buffers_offset;
281 unsigned long gart_textures_offset;
282
283 drm_local_map_t *sarea;
284 drm_local_map_t *mmio;
285 drm_local_map_t *cp_ring;
286 drm_local_map_t *ring_rptr;
287 drm_local_map_t *gart_textures;
288
289 struct mem_block *gart_heap;
290 struct mem_block *fb_heap;
291
292 /* SW interrupt */
293 wait_queue_head_t swi_queue;
294 atomic_t swi_emitted;
295 int vblank_crtc;
296 uint32_t irq_enable_reg;
297 int irq_enabled;
298 uint32_t r500_disp_irq_reg;
299
300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
302
303 unsigned long pcigart_offset;
304 unsigned int pcigart_offset_set;
305 struct drm_ati_pcigart_info gart_info;
306
307 u32 scratch_ages[5];
308
309 /* starting from here on, data is preserved accross an open */
310 uint32_t flags; /* see radeon_chip_flags */
311 unsigned long fb_aper_offset;
312
313 int num_gb_pipes;
314 } drm_radeon_private_t;
315
316 typedef struct drm_radeon_buf_priv {
317 u32 age;
318 } drm_radeon_buf_priv_t;
319
320 typedef struct drm_radeon_kcmd_buffer {
321 int bufsz;
322 char *buf;
323 int nbox;
324 struct drm_clip_rect __user *boxes;
325 } drm_radeon_kcmd_buffer_t;
326
327 extern int radeon_no_wb;
328 extern struct drm_ioctl_desc radeon_ioctls[];
329 extern int radeon_max_ioctl;
330
331 /* Check whether the given hardware address is inside the framebuffer or the
332 * GART area.
333 */
334 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
335 u64 off)
336 {
337 u32 fb_start = dev_priv->fb_location;
338 u32 fb_end = fb_start + dev_priv->fb_size - 1;
339 u32 gart_start = dev_priv->gart_vm_start;
340 u32 gart_end = gart_start + dev_priv->gart_size - 1;
341
342 return ((off >= fb_start && off <= fb_end) ||
343 (off >= gart_start && off <= gart_end));
344 }
345
346 /* radeon_cp.c */
347 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
348 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
349 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
350 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
351 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
352 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
353 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
356 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
357
358 extern void radeon_freelist_reset(struct drm_device * dev);
359 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
360
361 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
362
363 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
364
365 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
366 extern int radeon_presetup(struct drm_device *dev);
367 extern int radeon_driver_postcleanup(struct drm_device *dev);
368
369 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
370 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
371 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
372 extern void radeon_mem_takedown(struct mem_block **heap);
373 extern void radeon_mem_release(struct drm_file *file_priv,
374 struct mem_block *heap);
375
376 /* radeon_irq.c */
377 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
378 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
379
380 extern void radeon_do_release(struct drm_device * dev);
381 extern int radeon_driver_vblank_wait(struct drm_device * dev,
382 unsigned int *sequence);
383 extern int radeon_driver_vblank_wait2(struct drm_device * dev,
384 unsigned int *sequence);
385 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
386 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
387 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
388 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389 extern void radeon_enable_interrupt(struct drm_device *dev);
390 extern int radeon_vblank_crtc_get(struct drm_device *dev);
391 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
392
393 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
394 extern int radeon_driver_unload(struct drm_device *dev);
395 extern int radeon_driver_firstopen(struct drm_device *dev);
396 extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
397 extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
398 extern void radeon_driver_lastclose(struct drm_device * dev);
399 extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
400 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
401 unsigned long arg);
402
403 /* r300_cmdbuf.c */
404 extern void r300_init_reg_flags(struct drm_device *dev);
405
406 extern int r300_do_cp_cmdbuf(struct drm_device * dev,
407 struct drm_file *file_priv,
408 drm_radeon_kcmd_buffer_t * cmdbuf);
409
410 /* Flags for stats.boxes
411 */
412 #define RADEON_BOX_DMA_IDLE 0x1
413 #define RADEON_BOX_RING_FULL 0x2
414 #define RADEON_BOX_FLIP 0x4
415 #define RADEON_BOX_WAIT_IDLE 0x8
416 #define RADEON_BOX_TEXTURE_LOAD 0x10
417
418 /* Register definitions, register access macros and drmAddMap constants
419 * for Radeon kernel driver.
420 */
421
422 #define RADEON_AGP_COMMAND 0x0f60
423 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
424 # define RADEON_AGP_ENABLE (1<<8)
425 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
426 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
427 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
428 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
429 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
430 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
431 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
432
433 #define RADEON_BUS_CNTL 0x0030
434 # define RADEON_BUS_MASTER_DIS (1 << 6)
435
436 #define RADEON_CLOCK_CNTL_DATA 0x000c
437 # define RADEON_PLL_WR_EN (1 << 7)
438 #define RADEON_CLOCK_CNTL_INDEX 0x0008
439 #define RADEON_CONFIG_APER_SIZE 0x0108
440 #define RADEON_CONFIG_MEMSIZE 0x00f8
441 #define RADEON_CRTC_OFFSET 0x0224
442 #define RADEON_CRTC_OFFSET_CNTL 0x0228
443 # define RADEON_CRTC_TILE_EN (1 << 15)
444 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
445 #define RADEON_CRTC2_OFFSET 0x0324
446 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
447
448 #define RADEON_PCIE_INDEX 0x0030
449 #define RADEON_PCIE_DATA 0x0034
450 #define RADEON_PCIE_TX_GART_CNTL 0x10
451 # define RADEON_PCIE_TX_GART_EN (1 << 0)
452 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
453 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
454 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
455 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
456 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
457 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
458 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
459 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
460 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
461 #define RADEON_PCIE_TX_GART_BASE 0x13
462 #define RADEON_PCIE_TX_GART_START_LO 0x14
463 #define RADEON_PCIE_TX_GART_START_HI 0x15
464 #define RADEON_PCIE_TX_GART_END_LO 0x16
465 #define RADEON_PCIE_TX_GART_END_HI 0x17
466
467 #define RS480_NB_MC_INDEX 0x168
468 # define RS480_NB_MC_IND_WR_EN (1 << 8)
469 #define RS480_NB_MC_DATA 0x16c
470
471 #define RS690_MC_INDEX 0x78
472 # define RS690_MC_INDEX_MASK 0x1ff
473 # define RS690_MC_INDEX_WR_EN (1 << 9)
474 # define RS690_MC_INDEX_WR_ACK 0x7f
475 #define RS690_MC_DATA 0x7c
476
477 /* MC indirect registers */
478 #define RS480_MC_MISC_CNTL 0x18
479 # define RS480_DISABLE_GTW (1 << 1)
480 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
481 # define RS480_GART_INDEX_REG_EN (1 << 12)
482 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
483 #define RS480_K8_FB_LOCATION 0x1e
484 #define RS480_GART_FEATURE_ID 0x2b
485 # define RS480_HANG_EN (1 << 11)
486 # define RS480_TLB_ENABLE (1 << 18)
487 # define RS480_P2P_ENABLE (1 << 19)
488 # define RS480_GTW_LAC_EN (1 << 25)
489 # define RS480_2LEVEL_GART (0 << 30)
490 # define RS480_1LEVEL_GART (1 << 30)
491 # define RS480_PDC_EN (1 << 31)
492 #define RS480_GART_BASE 0x2c
493 #define RS480_GART_CACHE_CNTRL 0x2e
494 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
495 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
496 # define RS480_GART_EN (1 << 0)
497 # define RS480_VA_SIZE_32MB (0 << 1)
498 # define RS480_VA_SIZE_64MB (1 << 1)
499 # define RS480_VA_SIZE_128MB (2 << 1)
500 # define RS480_VA_SIZE_256MB (3 << 1)
501 # define RS480_VA_SIZE_512MB (4 << 1)
502 # define RS480_VA_SIZE_1GB (5 << 1)
503 # define RS480_VA_SIZE_2GB (6 << 1)
504 #define RS480_AGP_MODE_CNTL 0x39
505 # define RS480_POST_GART_Q_SIZE (1 << 18)
506 # define RS480_NONGART_SNOOP (1 << 19)
507 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
508 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
509 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
510 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
511 #define RS480_MC_MISC_UMA_CNTL 0x5f
512 #define RS480_MC_MCLK_CNTL 0x7a
513 #define RS480_MC_UMA_DUALCH_CNTL 0x86
514
515 #define RS690_MC_FB_LOCATION 0x100
516 #define RS690_MC_AGP_LOCATION 0x101
517 #define RS690_MC_AGP_BASE 0x102
518 #define RS690_MC_AGP_BASE_2 0x103
519
520 #define R520_MC_IND_INDEX 0x70
521 #define R520_MC_IND_WR_EN (1 << 24)
522 #define R520_MC_IND_DATA 0x74
523
524 #define RV515_MC_FB_LOCATION 0x01
525 #define RV515_MC_AGP_LOCATION 0x02
526 #define RV515_MC_AGP_BASE 0x03
527 #define RV515_MC_AGP_BASE_2 0x04
528
529 #define R520_MC_FB_LOCATION 0x04
530 #define R520_MC_AGP_LOCATION 0x05
531 #define R520_MC_AGP_BASE 0x06
532 #define R520_MC_AGP_BASE_2 0x07
533
534 #define RADEON_MPP_TB_CONFIG 0x01c0
535 #define RADEON_MEM_CNTL 0x0140
536 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
537 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
538 #define RS480_AGP_BASE_2 0x0164
539 #define RADEON_AGP_BASE 0x0170
540
541 /* pipe config regs */
542 #define R400_GB_PIPE_SELECT 0x402c
543 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
544 #define R500_SU_REG_DEST 0x42c8
545 #define R300_GB_TILE_CONFIG 0x4018
546 # define R300_ENABLE_TILING (1 << 0)
547 # define R300_PIPE_COUNT_RV350 (0 << 1)
548 # define R300_PIPE_COUNT_R300 (3 << 1)
549 # define R300_PIPE_COUNT_R420_3P (6 << 1)
550 # define R300_PIPE_COUNT_R420 (7 << 1)
551 # define R300_TILE_SIZE_8 (0 << 4)
552 # define R300_TILE_SIZE_16 (1 << 4)
553 # define R300_TILE_SIZE_32 (2 << 4)
554 # define R300_SUBPIXEL_1_12 (0 << 16)
555 # define R300_SUBPIXEL_1_16 (1 << 16)
556 #define R300_DST_PIPE_CONFIG 0x170c
557 # define R300_PIPE_AUTO_CONFIG (1 << 31)
558 #define R300_RB2D_DSTCACHE_MODE 0x3428
559 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
560 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
561
562 #define RADEON_RB3D_COLOROFFSET 0x1c40
563 #define RADEON_RB3D_COLORPITCH 0x1c48
564
565 #define RADEON_SRC_X_Y 0x1590
566
567 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
568 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
569 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
570 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
571 # define RADEON_GMC_BRUSH_NONE (15 << 4)
572 # define RADEON_GMC_DST_16BPP (4 << 8)
573 # define RADEON_GMC_DST_24BPP (5 << 8)
574 # define RADEON_GMC_DST_32BPP (6 << 8)
575 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
576 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
577 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
578 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
579 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
580 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
581 # define RADEON_ROP3_S 0x00cc0000
582 # define RADEON_ROP3_P 0x00f00000
583 #define RADEON_DP_WRITE_MASK 0x16cc
584 #define RADEON_SRC_PITCH_OFFSET 0x1428
585 #define RADEON_DST_PITCH_OFFSET 0x142c
586 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
587 # define RADEON_DST_TILE_LINEAR (0 << 30)
588 # define RADEON_DST_TILE_MACRO (1 << 30)
589 # define RADEON_DST_TILE_MICRO (2 << 30)
590 # define RADEON_DST_TILE_BOTH (3 << 30)
591
592 #define RADEON_SCRATCH_REG0 0x15e0
593 #define RADEON_SCRATCH_REG1 0x15e4
594 #define RADEON_SCRATCH_REG2 0x15e8
595 #define RADEON_SCRATCH_REG3 0x15ec
596 #define RADEON_SCRATCH_REG4 0x15f0
597 #define RADEON_SCRATCH_REG5 0x15f4
598 #define RADEON_SCRATCH_UMSK 0x0770
599 #define RADEON_SCRATCH_ADDR 0x0774
600
601 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
602
603 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
604 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
605 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
606
607 #define RADEON_GEN_INT_CNTL 0x0040
608 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
609 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
610 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
611 # define RADEON_SW_INT_ENABLE (1 << 25)
612
613 #define RADEON_GEN_INT_STATUS 0x0044
614 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
615 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
616 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
617 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
618 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
619 # define RADEON_SW_INT_TEST (1 << 25)
620 # define RADEON_SW_INT_TEST_ACK (1 << 25)
621 # define RADEON_SW_INT_FIRE (1 << 26)
622
623 #define RADEON_HOST_PATH_CNTL 0x0130
624 # define RADEON_HDP_SOFT_RESET (1 << 26)
625 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
626 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
627
628 #define RADEON_ISYNC_CNTL 0x1724
629 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
630 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
631 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
632 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
633 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
634 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
635
636 #define RADEON_RBBM_GUICNTL 0x172c
637 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
638 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
639 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
640 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
641
642 #define RADEON_MC_AGP_LOCATION 0x014c
643 #define RADEON_MC_FB_LOCATION 0x0148
644 #define RADEON_MCLK_CNTL 0x0012
645 # define RADEON_FORCEON_MCLKA (1 << 16)
646 # define RADEON_FORCEON_MCLKB (1 << 17)
647 # define RADEON_FORCEON_YCLKA (1 << 18)
648 # define RADEON_FORCEON_YCLKB (1 << 19)
649 # define RADEON_FORCEON_MC (1 << 20)
650 # define RADEON_FORCEON_AIC (1 << 21)
651
652 #define RADEON_PP_BORDER_COLOR_0 0x1d40
653 #define RADEON_PP_BORDER_COLOR_1 0x1d44
654 #define RADEON_PP_BORDER_COLOR_2 0x1d48
655 #define RADEON_PP_CNTL 0x1c38
656 # define RADEON_SCISSOR_ENABLE (1 << 1)
657 #define RADEON_PP_LUM_MATRIX 0x1d00
658 #define RADEON_PP_MISC 0x1c14
659 #define RADEON_PP_ROT_MATRIX_0 0x1d58
660 #define RADEON_PP_TXFILTER_0 0x1c54
661 #define RADEON_PP_TXOFFSET_0 0x1c5c
662 #define RADEON_PP_TXFILTER_1 0x1c6c
663 #define RADEON_PP_TXFILTER_2 0x1c84
664
665 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
666 #define R300_DSTCACHE_CTLSTAT 0x1714
667 # define R300_RB2D_DC_FLUSH (3 << 0)
668 # define R300_RB2D_DC_FREE (3 << 2)
669 # define R300_RB2D_DC_FLUSH_ALL 0xf
670 # define R300_RB2D_DC_BUSY (1 << 31)
671 #define RADEON_RB3D_CNTL 0x1c3c
672 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
673 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
674 # define RADEON_DITHER_ENABLE (1 << 2)
675 # define RADEON_ROUND_ENABLE (1 << 3)
676 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
677 # define RADEON_DITHER_INIT (1 << 5)
678 # define RADEON_ROP_ENABLE (1 << 6)
679 # define RADEON_STENCIL_ENABLE (1 << 7)
680 # define RADEON_Z_ENABLE (1 << 8)
681 # define RADEON_ZBLOCK16 (1 << 15)
682 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
683 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
684 #define RADEON_RB3D_DEPTHPITCH 0x1c28
685 #define RADEON_RB3D_PLANEMASK 0x1d84
686 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
687 #define RADEON_RB3D_ZCACHE_MODE 0x3250
688 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
689 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
690 # define RADEON_RB3D_ZC_FREE (1 << 2)
691 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
692 # define RADEON_RB3D_ZC_BUSY (1 << 31)
693 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
694 # define R300_ZC_FLUSH (1 << 0)
695 # define R300_ZC_FREE (1 << 1)
696 # define R300_ZC_FLUSH_ALL 0x3
697 # define R300_ZC_BUSY (1 << 31)
698 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
699 # define RADEON_RB3D_DC_FLUSH (3 << 0)
700 # define RADEON_RB3D_DC_FREE (3 << 2)
701 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
702 # define RADEON_RB3D_DC_BUSY (1 << 31)
703 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704 # define R300_RB3D_DC_FINISH (1 << 4)
705 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
706 # define RADEON_Z_TEST_MASK (7 << 4)
707 # define RADEON_Z_TEST_ALWAYS (7 << 4)
708 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
709 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
710 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
711 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
712 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
713 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
714 # define RADEON_FORCE_Z_DIRTY (1 << 29)
715 # define RADEON_Z_WRITE_ENABLE (1 << 30)
716 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
717 #define RADEON_RBBM_SOFT_RESET 0x00f0
718 # define RADEON_SOFT_RESET_CP (1 << 0)
719 # define RADEON_SOFT_RESET_HI (1 << 1)
720 # define RADEON_SOFT_RESET_SE (1 << 2)
721 # define RADEON_SOFT_RESET_RE (1 << 3)
722 # define RADEON_SOFT_RESET_PP (1 << 4)
723 # define RADEON_SOFT_RESET_E2 (1 << 5)
724 # define RADEON_SOFT_RESET_RB (1 << 6)
725 # define RADEON_SOFT_RESET_HDP (1 << 7)
726 /*
727 * 6:0 Available slots in the FIFO
728 * 8 Host Interface active
729 * 9 CP request active
730 * 10 FIFO request active
731 * 11 Host Interface retry active
732 * 12 CP retry active
733 * 13 FIFO retry active
734 * 14 FIFO pipeline busy
735 * 15 Event engine busy
736 * 16 CP command stream busy
737 * 17 2D engine busy
738 * 18 2D portion of render backend busy
739 * 20 3D setup engine busy
740 * 26 GA engine busy
741 * 27 CBA 2D engine busy
742 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
743 * command stream queue not empty or Ring Buffer not empty
744 */
745 #define RADEON_RBBM_STATUS 0x0e40
746 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
747 /* #define RADEON_RBBM_STATUS 0x1740 */
748 /* bits 6:0 are dword slots available in the cmd fifo */
749 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
750 # define RADEON_HIRQ_ON_RBB (1 << 8)
751 # define RADEON_CPRQ_ON_RBB (1 << 9)
752 # define RADEON_CFRQ_ON_RBB (1 << 10)
753 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
754 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
755 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
756 # define RADEON_PIPE_BUSY (1 << 14)
757 # define RADEON_ENG_EV_BUSY (1 << 15)
758 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
759 # define RADEON_E2_BUSY (1 << 17)
760 # define RADEON_RB2D_BUSY (1 << 18)
761 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
762 # define RADEON_VAP_BUSY (1 << 20)
763 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
764 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
765 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
766 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
767 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
768 # define RADEON_GA_BUSY (1 << 26)
769 # define RADEON_CBA2D_BUSY (1 << 27)
770 # define RADEON_RBBM_ACTIVE (1 << 31)
771 #define RADEON_RE_LINE_PATTERN 0x1cd0
772 #define RADEON_RE_MISC 0x26c4
773 #define RADEON_RE_TOP_LEFT 0x26c0
774 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
775 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
776 #define RADEON_RE_STIPPLE_DATA 0x1ccc
777
778 #define RADEON_SCISSOR_TL_0 0x1cd8
779 #define RADEON_SCISSOR_BR_0 0x1cdc
780 #define RADEON_SCISSOR_TL_1 0x1ce0
781 #define RADEON_SCISSOR_BR_1 0x1ce4
782 #define RADEON_SCISSOR_TL_2 0x1ce8
783 #define RADEON_SCISSOR_BR_2 0x1cec
784 #define RADEON_SE_COORD_FMT 0x1c50
785 #define RADEON_SE_CNTL 0x1c4c
786 # define RADEON_FFACE_CULL_CW (0 << 0)
787 # define RADEON_BFACE_SOLID (3 << 1)
788 # define RADEON_FFACE_SOLID (3 << 3)
789 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
790 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
791 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
792 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
793 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
794 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
795 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
796 # define RADEON_FOG_SHADE_FLAT (1 << 14)
797 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
798 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
799 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
800 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
801 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
802 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
803 #define RADEON_SE_CNTL_STATUS 0x2140
804 #define RADEON_SE_LINE_WIDTH 0x1db8
805 #define RADEON_SE_VPORT_XSCALE 0x1d98
806 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
807 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
808 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
809 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
810 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
811 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
812 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
813 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
814 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
815 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
816 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
817 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
818 #define RADEON_SURFACE_CNTL 0x0b00
819 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
820 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
821 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
822 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
823 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
824 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
825 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
826 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
827 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
828 #define RADEON_SURFACE0_INFO 0x0b0c
829 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
830 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
831 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
832 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
833 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
834 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
835 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
836 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
837 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
838 #define RADEON_SURFACE1_INFO 0x0b1c
839 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
840 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
841 #define RADEON_SURFACE2_INFO 0x0b2c
842 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
843 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
844 #define RADEON_SURFACE3_INFO 0x0b3c
845 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
846 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
847 #define RADEON_SURFACE4_INFO 0x0b4c
848 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
849 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
850 #define RADEON_SURFACE5_INFO 0x0b5c
851 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
852 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
853 #define RADEON_SURFACE6_INFO 0x0b6c
854 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
855 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
856 #define RADEON_SURFACE7_INFO 0x0b7c
857 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
858 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
859 #define RADEON_SW_SEMAPHORE 0x013c
860
861 #define RADEON_WAIT_UNTIL 0x1720
862 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
863 # define RADEON_WAIT_2D_IDLE (1 << 14)
864 # define RADEON_WAIT_3D_IDLE (1 << 15)
865 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
866 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
867 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
868
869 #define RADEON_RB3D_ZMASKOFFSET 0x3234
870 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
871 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
872 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
873
874 /* CP registers */
875 #define RADEON_CP_ME_RAM_ADDR 0x07d4
876 #define RADEON_CP_ME_RAM_RADDR 0x07d8
877 #define RADEON_CP_ME_RAM_DATAH 0x07dc
878 #define RADEON_CP_ME_RAM_DATAL 0x07e0
879
880 #define RADEON_CP_RB_BASE 0x0700
881 #define RADEON_CP_RB_CNTL 0x0704
882 # define RADEON_BUF_SWAP_32BIT (2 << 16)
883 # define RADEON_RB_NO_UPDATE (1 << 27)
884 #define RADEON_CP_RB_RPTR_ADDR 0x070c
885 #define RADEON_CP_RB_RPTR 0x0710
886 #define RADEON_CP_RB_WPTR 0x0714
887
888 #define RADEON_CP_RB_WPTR_DELAY 0x0718
889 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
890 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
891
892 #define RADEON_CP_IB_BASE 0x0738
893
894 #define RADEON_CP_CSQ_CNTL 0x0740
895 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
896 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
897 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
898 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
899 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
900 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
901 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
902
903 #define RADEON_AIC_CNTL 0x01d0
904 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
905 #define RADEON_AIC_STAT 0x01d4
906 #define RADEON_AIC_PT_BASE 0x01d8
907 #define RADEON_AIC_LO_ADDR 0x01dc
908 #define RADEON_AIC_HI_ADDR 0x01e0
909 #define RADEON_AIC_TLB_ADDR 0x01e4
910 #define RADEON_AIC_TLB_DATA 0x01e8
911
912 /* CP command packets */
913 #define RADEON_CP_PACKET0 0x00000000
914 # define RADEON_ONE_REG_WR (1 << 15)
915 #define RADEON_CP_PACKET1 0x40000000
916 #define RADEON_CP_PACKET2 0x80000000
917 #define RADEON_CP_PACKET3 0xC0000000
918 # define RADEON_CP_NOP 0x00001000
919 # define RADEON_CP_NEXT_CHAR 0x00001900
920 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
921 # define RADEON_CP_SET_SCISSORS 0x00001E00
922 /* GEN_INDX_PRIM is unsupported starting with R300 */
923 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
924 # define RADEON_WAIT_FOR_IDLE 0x00002600
925 # define RADEON_3D_DRAW_VBUF 0x00002800
926 # define RADEON_3D_DRAW_IMMD 0x00002900
927 # define RADEON_3D_DRAW_INDX 0x00002A00
928 # define RADEON_CP_LOAD_PALETTE 0x00002C00
929 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
930 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
931 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
932 # define RADEON_3D_CLEAR_ZMASK 0x00003200
933 # define RADEON_CP_INDX_BUFFER 0x00003300
934 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
935 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
936 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
937 # define RADEON_3D_CLEAR_HIZ 0x00003700
938 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
939 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
940 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
941 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
942 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
943
944 #define RADEON_CP_PACKET_MASK 0xC0000000
945 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
946 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
947 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
948 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
949
950 #define RADEON_VTX_Z_PRESENT (1 << 31)
951 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
952
953 #define RADEON_PRIM_TYPE_NONE (0 << 0)
954 #define RADEON_PRIM_TYPE_POINT (1 << 0)
955 #define RADEON_PRIM_TYPE_LINE (2 << 0)
956 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
957 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
958 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
959 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
960 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
961 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
962 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
963 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
964 #define RADEON_PRIM_TYPE_MASK 0xf
965 #define RADEON_PRIM_WALK_IND (1 << 4)
966 #define RADEON_PRIM_WALK_LIST (2 << 4)
967 #define RADEON_PRIM_WALK_RING (3 << 4)
968 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
969 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
970 #define RADEON_MAOS_ENABLE (1 << 7)
971 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
972 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
973 #define RADEON_NUM_VERTICES_SHIFT 16
974
975 #define RADEON_COLOR_FORMAT_CI8 2
976 #define RADEON_COLOR_FORMAT_ARGB1555 3
977 #define RADEON_COLOR_FORMAT_RGB565 4
978 #define RADEON_COLOR_FORMAT_ARGB8888 6
979 #define RADEON_COLOR_FORMAT_RGB332 7
980 #define RADEON_COLOR_FORMAT_RGB8 9
981 #define RADEON_COLOR_FORMAT_ARGB4444 15
982
983 #define RADEON_TXFORMAT_I8 0
984 #define RADEON_TXFORMAT_AI88 1
985 #define RADEON_TXFORMAT_RGB332 2
986 #define RADEON_TXFORMAT_ARGB1555 3
987 #define RADEON_TXFORMAT_RGB565 4
988 #define RADEON_TXFORMAT_ARGB4444 5
989 #define RADEON_TXFORMAT_ARGB8888 6
990 #define RADEON_TXFORMAT_RGBA8888 7
991 #define RADEON_TXFORMAT_Y8 8
992 #define RADEON_TXFORMAT_VYUY422 10
993 #define RADEON_TXFORMAT_YVYU422 11
994 #define RADEON_TXFORMAT_DXT1 12
995 #define RADEON_TXFORMAT_DXT23 14
996 #define RADEON_TXFORMAT_DXT45 15
997
998 #define R200_PP_TXCBLEND_0 0x2f00
999 #define R200_PP_TXCBLEND_1 0x2f10
1000 #define R200_PP_TXCBLEND_2 0x2f20
1001 #define R200_PP_TXCBLEND_3 0x2f30
1002 #define R200_PP_TXCBLEND_4 0x2f40
1003 #define R200_PP_TXCBLEND_5 0x2f50
1004 #define R200_PP_TXCBLEND_6 0x2f60
1005 #define R200_PP_TXCBLEND_7 0x2f70
1006 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1007 #define R200_PP_TFACTOR_0 0x2ee0
1008 #define R200_SE_VTX_FMT_0 0x2088
1009 #define R200_SE_VAP_CNTL 0x2080
1010 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1011 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1012 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1013 #define R200_PP_TXFILTER_5 0x2ca0
1014 #define R200_PP_TXFILTER_4 0x2c80
1015 #define R200_PP_TXFILTER_3 0x2c60
1016 #define R200_PP_TXFILTER_2 0x2c40
1017 #define R200_PP_TXFILTER_1 0x2c20
1018 #define R200_PP_TXFILTER_0 0x2c00
1019 #define R200_PP_TXOFFSET_5 0x2d78
1020 #define R200_PP_TXOFFSET_4 0x2d60
1021 #define R200_PP_TXOFFSET_3 0x2d48
1022 #define R200_PP_TXOFFSET_2 0x2d30
1023 #define R200_PP_TXOFFSET_1 0x2d18
1024 #define R200_PP_TXOFFSET_0 0x2d00
1025
1026 #define R200_PP_CUBIC_FACES_0 0x2c18
1027 #define R200_PP_CUBIC_FACES_1 0x2c38
1028 #define R200_PP_CUBIC_FACES_2 0x2c58
1029 #define R200_PP_CUBIC_FACES_3 0x2c78
1030 #define R200_PP_CUBIC_FACES_4 0x2c98
1031 #define R200_PP_CUBIC_FACES_5 0x2cb8
1032 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1033 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1034 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1035 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1036 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1037 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1038 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1039 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1040 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1041 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1042 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1043 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1044 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1045 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1046 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1047 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1048 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1049 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1050 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1051 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1052 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1053 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1054 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1055 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1056 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1057 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1058 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1059 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1060 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1061 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1062
1063 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1064 #define R200_SE_VTE_CNTL 0x20b0
1065 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1066 #define R200_PP_TAM_DEBUG3 0x2d9c
1067 #define R200_PP_CNTL_X 0x2cc4
1068 #define R200_SE_VAP_CNTL_STATUS 0x2140
1069 #define R200_RE_SCISSOR_TL_0 0x1cd8
1070 #define R200_RE_SCISSOR_TL_1 0x1ce0
1071 #define R200_RE_SCISSOR_TL_2 0x1ce8
1072 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1073 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1074 #define R200_SE_VTX_STATE_CNTL 0x2180
1075 #define R200_RE_POINTSIZE 0x2648
1076 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1077
1078 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1079 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1080 #define RADEON_PP_TEX_SIZE_2 0x1d14
1081
1082 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1083 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1084 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1085 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1086 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1087 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1088
1089 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1090
1091 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1092 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1093 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1094 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1095 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1096 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1097 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1098 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1099 #define R200_3D_DRAW_IMMD_2 0xC0003500
1100 #define R200_SE_VTX_FMT_1 0x208c
1101 #define R200_RE_CNTL 0x1c50
1102
1103 #define R200_RB3D_BLENDCOLOR 0x3218
1104
1105 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1106
1107 #define R200_PP_TRI_PERF 0x2cf8
1108
1109 #define R200_PP_AFS_0 0x2f80
1110 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1111
1112 #define R200_VAP_PVS_CNTL_1 0x22D0
1113
1114 #define R500_D1CRTC_STATUS 0x609c
1115 #define R500_D2CRTC_STATUS 0x689c
1116 #define R500_CRTC_V_BLANK (1<<0)
1117
1118 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1119 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1120
1121 #define R500_D1MODE_V_COUNTER 0x6530
1122 #define R500_D2MODE_V_COUNTER 0x6d30
1123
1124 #define R500_D1MODE_VBLANK_STATUS 0x6534
1125 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1126 #define R500_VBLANK_OCCURED (1<<0)
1127 #define R500_VBLANK_ACK (1<<4)
1128 #define R500_VBLANK_STAT (1<<12)
1129 #define R500_VBLANK_INT (1<<16)
1130
1131 #define R500_DxMODE_INT_MASK 0x6540
1132 #define R500_D1MODE_INT_MASK (1<<0)
1133 #define R500_D2MODE_INT_MASK (1<<8)
1134
1135 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1136 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1137 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1138
1139 /* Constants */
1140 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1141
1142 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1143 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1144 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1145 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1146 #define RADEON_LAST_DISPATCH 1
1147
1148 #define RADEON_MAX_VB_AGE 0x7fffffff
1149 #define RADEON_MAX_VB_VERTS (0xffff)
1150
1151 #define RADEON_RING_HIGH_MARK 128
1152
1153 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1154
1155 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1156 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1157 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1158 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1159
1160 #define RADEON_WRITE_PLL(addr, val) \
1161 do { \
1162 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1163 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1164 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1165 } while (0)
1166
1167 #define RADEON_WRITE_PCIE(addr, val) \
1168 do { \
1169 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1170 ((addr) & 0xff)); \
1171 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1172 } while (0)
1173
1174 #define R500_WRITE_MCIND(addr, val) \
1175 do { \
1176 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1177 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1178 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1179 } while (0)
1180
1181 #define RS480_WRITE_MCIND(addr, val) \
1182 do { \
1183 RADEON_WRITE(RS480_NB_MC_INDEX, \
1184 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1185 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1186 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1187 } while (0)
1188
1189 #define RS690_WRITE_MCIND(addr, val) \
1190 do { \
1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1192 RADEON_WRITE(RS690_MC_DATA, val); \
1193 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1194 } while (0)
1195
1196 #define IGP_WRITE_MCIND(addr, val) \
1197 do { \
1198 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1199 RS690_WRITE_MCIND(addr, val); \
1200 else \
1201 RS480_WRITE_MCIND(addr, val); \
1202 } while (0)
1203
1204 #define CP_PACKET0( reg, n ) \
1205 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1206 #define CP_PACKET0_TABLE( reg, n ) \
1207 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1208 #define CP_PACKET1( reg0, reg1 ) \
1209 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1210 #define CP_PACKET2() \
1211 (RADEON_CP_PACKET2)
1212 #define CP_PACKET3( pkt, n ) \
1213 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1214
1215 /* ================================================================
1216 * Engine control helper macros
1217 */
1218
1219 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1220 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1221 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1222 RADEON_WAIT_HOST_IDLECLEAN) ); \
1223 } while (0)
1224
1225 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1226 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1227 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1228 RADEON_WAIT_HOST_IDLECLEAN) ); \
1229 } while (0)
1230
1231 #define RADEON_WAIT_UNTIL_IDLE() do { \
1232 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1233 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1234 RADEON_WAIT_3D_IDLECLEAN | \
1235 RADEON_WAIT_HOST_IDLECLEAN) ); \
1236 } while (0)
1237
1238 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1239 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1240 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1241 } while (0)
1242
1243 #define RADEON_FLUSH_CACHE() do { \
1244 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1245 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1246 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 } else { \
1248 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1249 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1250 } \
1251 } while (0)
1252
1253 #define RADEON_PURGE_CACHE() do { \
1254 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1255 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1256 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 } else { \
1258 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1259 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1260 } \
1261 } while (0)
1262
1263 #define RADEON_FLUSH_ZCACHE() do { \
1264 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1265 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1266 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1267 } else { \
1268 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1269 OUT_RING(R300_ZC_FLUSH); \
1270 } \
1271 } while (0)
1272
1273 #define RADEON_PURGE_ZCACHE() do { \
1274 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1275 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1276 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1277 } else { \
1278 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1279 OUT_RING(R300_ZC_FLUSH_ALL); \
1280 } \
1281 } while (0)
1282
1283 /* ================================================================
1284 * Misc helper macros
1285 */
1286
1287 /* Perfbox functionality only.
1288 */
1289 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1290 do { \
1291 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1292 u32 head = GET_RING_HEAD( dev_priv ); \
1293 if (head == dev_priv->ring.tail) \
1294 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1295 } \
1296 } while (0)
1297
1298 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1299 do { \
1300 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1301 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1302 int __ret = radeon_do_cp_idle( dev_priv ); \
1303 if ( __ret ) return __ret; \
1304 sarea_priv->last_dispatch = 0; \
1305 radeon_freelist_reset( dev ); \
1306 } \
1307 } while (0)
1308
1309 #define RADEON_DISPATCH_AGE( age ) do { \
1310 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1311 OUT_RING( age ); \
1312 } while (0)
1313
1314 #define RADEON_FRAME_AGE( age ) do { \
1315 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1316 OUT_RING( age ); \
1317 } while (0)
1318
1319 #define RADEON_CLEAR_AGE( age ) do { \
1320 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1321 OUT_RING( age ); \
1322 } while (0)
1323
1324 /* ================================================================
1325 * Ring control
1326 */
1327
1328 #define RADEON_VERBOSE 0
1329
1330 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1331
1332 #define BEGIN_RING( n ) do { \
1333 if ( RADEON_VERBOSE ) { \
1334 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1335 } \
1336 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1337 COMMIT_RING(); \
1338 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1339 } \
1340 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1341 ring = dev_priv->ring.start; \
1342 write = dev_priv->ring.tail; \
1343 mask = dev_priv->ring.tail_mask; \
1344 } while (0)
1345
1346 #define ADVANCE_RING() do { \
1347 if ( RADEON_VERBOSE ) { \
1348 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1349 write, dev_priv->ring.tail ); \
1350 } \
1351 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1352 DRM_ERROR( \
1353 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1354 ((dev_priv->ring.tail + _nr) & mask), \
1355 write, __LINE__); \
1356 } else \
1357 dev_priv->ring.tail = write; \
1358 } while (0)
1359
1360 #define COMMIT_RING() do { \
1361 /* Flush writes to ring */ \
1362 DRM_MEMORYBARRIER(); \
1363 GET_RING_HEAD( dev_priv ); \
1364 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1365 /* read from PCI bus to ensure correct posting */ \
1366 RADEON_READ( RADEON_CP_RB_RPTR ); \
1367 } while (0)
1368
1369 #define OUT_RING( x ) do { \
1370 if ( RADEON_VERBOSE ) { \
1371 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1372 (unsigned int)(x), write ); \
1373 } \
1374 ring[write++] = (x); \
1375 write &= mask; \
1376 } while (0)
1377
1378 #define OUT_RING_REG( reg, val ) do { \
1379 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1380 OUT_RING( val ); \
1381 } while (0)
1382
1383 #define OUT_RING_TABLE( tab, sz ) do { \
1384 int _size = (sz); \
1385 int *_tab = (int *)(tab); \
1386 \
1387 if (write + _size > mask) { \
1388 int _i = (mask+1) - write; \
1389 _size -= _i; \
1390 while (_i > 0 ) { \
1391 *(int *)(ring + write) = *_tab++; \
1392 write++; \
1393 _i--; \
1394 } \
1395 write = 0; \
1396 _tab += _i; \
1397 } \
1398 while (_size > 0) { \
1399 *(ring + write) = *_tab++; \
1400 write++; \
1401 _size--; \
1402 } \
1403 write &= mask; \
1404 } while (0)
1405
1406 #endif /* __RADEON_DRV_H__ */
linux kernel for loongson