1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
7 * Ani Joshi / Jeff Garzik
10 * Michel Danzer <michdaen@iiic.ethz.ch>
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
18 * Andreas Hundt <andi@convergence.de>
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
28 * Jon Smirl <jonsmirl@yahoo.com>
30 * - replace ROM BIOS search
32 * Based off of Geert's atyfb.c and vfb.c.
35 * - monitor sensing (DDC)
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
40 * Please cc: your patches to brad@neruo.com.
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
55 #include <linux/tty.h>
56 #include <linux/slab.h>
57 #include <linux/vmalloc.h>
58 #include <linux/delay.h>
59 #include <linux/interrupt.h>
60 #include <asm/uaccess.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/ioport.h>
65 #include <linux/console.h>
66 #include <linux/backlight.h>
69 #ifdef CONFIG_PPC_PMAC
70 #include <asm/machdep.h>
71 #include <asm/pmac_feature.h>
73 #include <asm/pci-bridge.h>
74 #include "../macmodes.h"
77 #ifdef CONFIG_PMAC_BACKLIGHT
78 #include <asm/backlight.h>
81 #ifdef CONFIG_BOOTX_TEXT
82 #include <asm/btext.h>
83 #endif /* CONFIG_BOOTX_TEXT */
89 #include <video/aty128.h>
95 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
97 #define DBG(fmt, args...)
100 #ifndef CONFIG_PPC_PMAC
102 static struct fb_var_screeninfo default_var __devinitdata
= {
103 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
104 640, 480, 640, 480, 0, 0, 8, 0,
105 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
106 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
107 0, FB_VMODE_NONINTERLACED
110 #else /* CONFIG_PPC_PMAC */
111 /* default to 1024x768 at 75Hz on PPC - this will work
112 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
113 static struct fb_var_screeninfo default_var
= {
114 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
115 1024, 768, 1024, 768, 0, 0, 8, 0,
116 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
117 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
118 FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
119 FB_VMODE_NONINTERLACED
121 #endif /* CONFIG_PPC_PMAC */
123 /* default modedb mode */
124 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
125 static struct fb_videomode defaultmode __devinitdata
= {
137 .vmode
= FB_VMODE_NONINTERLACED
140 /* Chip generations */
152 /* Must match above enum */
153 static const char *r128_family
[] __devinitdata
= {
165 * PCI driver prototypes
167 static int aty128_probe(struct pci_dev
*pdev
,
168 const struct pci_device_id
*ent
);
169 static void aty128_remove(struct pci_dev
*pdev
);
170 static int aty128_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
);
171 static int aty128_pci_resume(struct pci_dev
*pdev
);
172 static int aty128_do_resume(struct pci_dev
*pdev
);
174 /* supported Rage128 chipsets */
175 static struct pci_device_id aty128_pci_tbl
[] = {
176 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_LE
,
177 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_M3_pci
},
178 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_LF
,
179 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_M3
},
180 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_MF
,
181 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_M4
},
182 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_ML
,
183 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_M4
},
184 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PA
,
185 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
186 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PB
,
187 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
188 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PC
,
189 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
190 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PD
,
191 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro_pci
},
192 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PE
,
193 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
194 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PF
,
195 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
196 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PG
,
197 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
198 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PH
,
199 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
200 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PI
,
201 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
202 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PJ
,
203 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
204 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PK
,
205 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
206 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PL
,
207 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
208 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PM
,
209 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
210 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PN
,
211 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
212 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PO
,
213 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
214 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PP
,
215 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro_pci
},
216 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PQ
,
217 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
218 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PR
,
219 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro_pci
},
220 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PS
,
221 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
222 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PT
,
223 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
224 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PU
,
225 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
226 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PV
,
227 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
228 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PW
,
229 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
230 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_PX
,
231 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pro
},
232 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_RE
,
233 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pci
},
234 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_RF
,
235 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
236 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_RG
,
237 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
238 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_RK
,
239 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pci
},
240 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_RL
,
241 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
242 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SE
,
243 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
244 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SF
,
245 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_pci
},
246 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SG
,
247 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
248 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SH
,
249 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
250 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SK
,
251 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
252 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SL
,
253 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
254 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SM
,
255 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
256 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_SN
,
257 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128
},
258 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TF
,
259 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
260 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TL
,
261 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
262 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TR
,
263 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
264 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TS
,
265 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
266 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TT
,
267 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
268 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RAGE128_TU
,
269 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, rage_128_ultra
},
273 MODULE_DEVICE_TABLE(pci
, aty128_pci_tbl
);
275 static struct pci_driver aty128fb_driver
= {
277 .id_table
= aty128_pci_tbl
,
278 .probe
= aty128_probe
,
279 .remove
= __devexit_p(aty128_remove
),
280 .suspend
= aty128_pci_suspend
,
281 .resume
= aty128_pci_resume
,
284 /* packed BIOS settings */
289 u8 accelerator_entry
;
291 u16 VGA_table_offset
;
292 u16 POST_table_offset
;
298 u16 PCLK_ref_divider
;
302 u16 MCLK_ref_divider
;
306 u16 XCLK_ref_divider
;
309 } __attribute__ ((packed
)) PLL_BLOCK
;
310 #endif /* !CONFIG_PPC */
312 /* onboard memory information */
313 struct aty128_meminfo
{
327 /* various memory configurations */
328 static const struct aty128_meminfo sdr_128
=
329 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
330 static const struct aty128_meminfo sdr_64
=
331 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
332 static const struct aty128_meminfo sdr_sgram
=
333 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
334 static const struct aty128_meminfo ddr_sgram
=
335 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
337 static struct fb_fix_screeninfo aty128fb_fix __devinitdata
= {
339 .type
= FB_TYPE_PACKED_PIXELS
,
340 .visual
= FB_VISUAL_PSEUDOCOLOR
,
344 .accel
= FB_ACCEL_ATI_RAGE128
,
347 static char *mode_option __devinitdata
= NULL
;
349 #ifdef CONFIG_PPC_PMAC
350 static int default_vmode __devinitdata
= VMODE_1024_768_60
;
351 static int default_cmode __devinitdata
= CMODE_8
;
354 static int default_crt_on __devinitdata
= 0;
355 static int default_lcd_on __devinitdata
= 1;
362 struct aty128_constants
{
374 u32 h_total
, h_sync_strt_wid
;
375 u32 v_total
, v_sync_strt_wid
;
377 u32 offset
, offset_cntl
;
378 u32 xoffset
, yoffset
;
385 u32 feedback_divider
;
389 struct aty128_ddafifo
{
394 /* register values for a specific mode */
395 struct aty128fb_par
{
396 struct aty128_crtc crtc
;
397 struct aty128_pll pll
;
398 struct aty128_ddafifo fifo_reg
;
400 struct aty128_constants constants
; /* PLL and others */
401 void __iomem
*regbase
; /* remapped mmio */
402 u32 vram_size
; /* onboard video ram */
404 const struct aty128_meminfo
*mem
; /* onboard mem info */
406 struct { int vram
; int vram_valid
; } mtrr
;
408 int blitter_may_be_busy
;
409 int fifo_slots
; /* free slots in FIFO (64 max) */
413 struct pci_dev
*pdev
;
414 struct fb_info
*next
;
418 u8 red
[32]; /* see aty128fb_setcolreg */
421 u32 pseudo_palette
[16]; /* used for TRUECOLOR */
425 #define round_div(n, d) ((n+(d/2))/d)
427 static int aty128fb_check_var(struct fb_var_screeninfo
*var
,
428 struct fb_info
*info
);
429 static int aty128fb_set_par(struct fb_info
*info
);
430 static int aty128fb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
431 u_int transp
, struct fb_info
*info
);
432 static int aty128fb_pan_display(struct fb_var_screeninfo
*var
,
434 static int aty128fb_blank(int blank
, struct fb_info
*fb
);
435 static int aty128fb_ioctl(struct fb_info
*info
, u_int cmd
, unsigned long arg
);
436 static int aty128fb_sync(struct fb_info
*info
);
442 static int aty128_encode_var(struct fb_var_screeninfo
*var
,
443 const struct aty128fb_par
*par
);
444 static int aty128_decode_var(struct fb_var_screeninfo
*var
,
445 struct aty128fb_par
*par
);
447 static void __devinit
aty128_get_pllinfo(struct aty128fb_par
*par
,
449 static void __devinit __iomem
*aty128_map_ROM(struct pci_dev
*pdev
, const struct aty128fb_par
*par
);
451 static void aty128_timings(struct aty128fb_par
*par
);
452 static void aty128_init_engine(struct aty128fb_par
*par
);
453 static void aty128_reset_engine(const struct aty128fb_par
*par
);
454 static void aty128_flush_pixel_cache(const struct aty128fb_par
*par
);
455 static void do_wait_for_fifo(u16 entries
, struct aty128fb_par
*par
);
456 static void wait_for_fifo(u16 entries
, struct aty128fb_par
*par
);
457 static void wait_for_idle(struct aty128fb_par
*par
);
458 static u32
depth_to_dst(u32 depth
);
460 #define BIOS_IN8(v) (readb(bios + (v)))
461 #define BIOS_IN16(v) (readb(bios + (v)) | \
462 (readb(bios + (v) + 1) << 8))
463 #define BIOS_IN32(v) (readb(bios + (v)) | \
464 (readb(bios + (v) + 1) << 8) | \
465 (readb(bios + (v) + 2) << 16) | \
466 (readb(bios + (v) + 3) << 24))
469 static struct fb_ops aty128fb_ops
= {
470 .owner
= THIS_MODULE
,
471 .fb_check_var
= aty128fb_check_var
,
472 .fb_set_par
= aty128fb_set_par
,
473 .fb_setcolreg
= aty128fb_setcolreg
,
474 .fb_pan_display
= aty128fb_pan_display
,
475 .fb_blank
= aty128fb_blank
,
476 .fb_ioctl
= aty128fb_ioctl
,
477 .fb_sync
= aty128fb_sync
,
478 .fb_fillrect
= cfb_fillrect
,
479 .fb_copyarea
= cfb_copyarea
,
480 .fb_imageblit
= cfb_imageblit
,
484 * Functions to read from/write to the mmio registers
485 * - endian conversions may possibly be avoided by
486 * using the other register aperture. TODO.
488 static inline u32
_aty_ld_le32(volatile unsigned int regindex
,
489 const struct aty128fb_par
*par
)
491 return readl (par
->regbase
+ regindex
);
494 static inline void _aty_st_le32(volatile unsigned int regindex
, u32 val
,
495 const struct aty128fb_par
*par
)
497 writel (val
, par
->regbase
+ regindex
);
500 static inline u8
_aty_ld_8(unsigned int regindex
,
501 const struct aty128fb_par
*par
)
503 return readb (par
->regbase
+ regindex
);
506 static inline void _aty_st_8(unsigned int regindex
, u8 val
,
507 const struct aty128fb_par
*par
)
509 writeb (val
, par
->regbase
+ regindex
);
512 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
513 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
514 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
515 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
518 * Functions to read from/write to the pll registers
521 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
522 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
525 static u32
_aty_ld_pll(unsigned int pll_index
,
526 const struct aty128fb_par
*par
)
528 aty_st_8(CLOCK_CNTL_INDEX
, pll_index
& 0x3F);
529 return aty_ld_le32(CLOCK_CNTL_DATA
);
533 static void _aty_st_pll(unsigned int pll_index
, u32 val
,
534 const struct aty128fb_par
*par
)
536 aty_st_8(CLOCK_CNTL_INDEX
, (pll_index
& 0x3F) | PLL_WR_EN
);
537 aty_st_le32(CLOCK_CNTL_DATA
, val
);
541 /* return true when the PLL has completed an atomic update */
542 static int aty_pll_readupdate(const struct aty128fb_par
*par
)
544 return !(aty_ld_pll(PPLL_REF_DIV
) & PPLL_ATOMIC_UPDATE_R
);
548 static void aty_pll_wait_readupdate(const struct aty128fb_par
*par
)
550 unsigned long timeout
= jiffies
+ HZ
/100; // should be more than enough
553 while (time_before(jiffies
, timeout
))
554 if (aty_pll_readupdate(par
)) {
559 if (reset
) /* reset engine?? */
560 printk(KERN_DEBUG
"aty128fb: PLL write timeout!\n");
564 /* tell PLL to update */
565 static void aty_pll_writeupdate(const struct aty128fb_par
*par
)
567 aty_pll_wait_readupdate(par
);
569 aty_st_pll(PPLL_REF_DIV
,
570 aty_ld_pll(PPLL_REF_DIV
) | PPLL_ATOMIC_UPDATE_W
);
574 /* write to the scratch register to test r/w functionality */
575 static int __devinit
register_test(const struct aty128fb_par
*par
)
580 val
= aty_ld_le32(BIOS_0_SCRATCH
);
582 aty_st_le32(BIOS_0_SCRATCH
, 0x55555555);
583 if (aty_ld_le32(BIOS_0_SCRATCH
) == 0x55555555) {
584 aty_st_le32(BIOS_0_SCRATCH
, 0xAAAAAAAA);
586 if (aty_ld_le32(BIOS_0_SCRATCH
) == 0xAAAAAAAA)
590 aty_st_le32(BIOS_0_SCRATCH
, val
); // restore value
596 * Accelerator engine functions
598 static void do_wait_for_fifo(u16 entries
, struct aty128fb_par
*par
)
603 for (i
= 0; i
< 2000000; i
++) {
604 par
->fifo_slots
= aty_ld_le32(GUI_STAT
) & 0x0fff;
605 if (par
->fifo_slots
>= entries
)
608 aty128_reset_engine(par
);
613 static void wait_for_idle(struct aty128fb_par
*par
)
617 do_wait_for_fifo(64, par
);
620 for (i
= 0; i
< 2000000; i
++) {
621 if (!(aty_ld_le32(GUI_STAT
) & (1 << 31))) {
622 aty128_flush_pixel_cache(par
);
623 par
->blitter_may_be_busy
= 0;
627 aty128_reset_engine(par
);
632 static void wait_for_fifo(u16 entries
, struct aty128fb_par
*par
)
634 if (par
->fifo_slots
< entries
)
635 do_wait_for_fifo(64, par
);
636 par
->fifo_slots
-= entries
;
640 static void aty128_flush_pixel_cache(const struct aty128fb_par
*par
)
645 tmp
= aty_ld_le32(PC_NGUI_CTLSTAT
);
648 aty_st_le32(PC_NGUI_CTLSTAT
, tmp
);
650 for (i
= 0; i
< 2000000; i
++)
651 if (!(aty_ld_le32(PC_NGUI_CTLSTAT
) & PC_BUSY
))
656 static void aty128_reset_engine(const struct aty128fb_par
*par
)
658 u32 gen_reset_cntl
, clock_cntl_index
, mclk_cntl
;
660 aty128_flush_pixel_cache(par
);
662 clock_cntl_index
= aty_ld_le32(CLOCK_CNTL_INDEX
);
663 mclk_cntl
= aty_ld_pll(MCLK_CNTL
);
665 aty_st_pll(MCLK_CNTL
, mclk_cntl
| 0x00030000);
667 gen_reset_cntl
= aty_ld_le32(GEN_RESET_CNTL
);
668 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
| SOFT_RESET_GUI
);
669 aty_ld_le32(GEN_RESET_CNTL
);
670 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
& ~(SOFT_RESET_GUI
));
671 aty_ld_le32(GEN_RESET_CNTL
);
673 aty_st_pll(MCLK_CNTL
, mclk_cntl
);
674 aty_st_le32(CLOCK_CNTL_INDEX
, clock_cntl_index
);
675 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
);
677 /* use old pio mode */
678 aty_st_le32(PM4_BUFFER_CNTL
, PM4_BUFFER_CNTL_NONPM4
);
684 static void aty128_init_engine(struct aty128fb_par
*par
)
690 /* 3D scaler not spoken here */
691 wait_for_fifo(1, par
);
692 aty_st_le32(SCALE_3D_CNTL
, 0x00000000);
694 aty128_reset_engine(par
);
696 pitch_value
= par
->crtc
.pitch
;
697 if (par
->crtc
.bpp
== 24) {
698 pitch_value
= pitch_value
* 3;
701 wait_for_fifo(4, par
);
702 /* setup engine offset registers */
703 aty_st_le32(DEFAULT_OFFSET
, 0x00000000);
705 /* setup engine pitch registers */
706 aty_st_le32(DEFAULT_PITCH
, pitch_value
);
708 /* set the default scissor register to max dimensions */
709 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT
, (0x1FFF << 16) | 0x1FFF);
711 /* set the drawing controls registers */
712 aty_st_le32(DP_GUI_MASTER_CNTL
,
713 GMC_SRC_PITCH_OFFSET_DEFAULT
|
714 GMC_DST_PITCH_OFFSET_DEFAULT
|
715 GMC_SRC_CLIP_DEFAULT
|
716 GMC_DST_CLIP_DEFAULT
|
717 GMC_BRUSH_SOLIDCOLOR
|
718 (depth_to_dst(par
->crtc
.depth
) << 8) |
720 GMC_BYTE_ORDER_MSB_TO_LSB
|
721 GMC_DP_CONVERSION_TEMP_6500
|
725 GMC_DST_CLR_CMP_FCN_CLEAR
|
729 wait_for_fifo(8, par
);
730 /* clear the line drawing registers */
731 aty_st_le32(DST_BRES_ERR
, 0);
732 aty_st_le32(DST_BRES_INC
, 0);
733 aty_st_le32(DST_BRES_DEC
, 0);
735 /* set brush color registers */
736 aty_st_le32(DP_BRUSH_FRGD_CLR
, 0xFFFFFFFF); /* white */
737 aty_st_le32(DP_BRUSH_BKGD_CLR
, 0x00000000); /* black */
739 /* set source color registers */
740 aty_st_le32(DP_SRC_FRGD_CLR
, 0xFFFFFFFF); /* white */
741 aty_st_le32(DP_SRC_BKGD_CLR
, 0x00000000); /* black */
743 /* default write mask */
744 aty_st_le32(DP_WRITE_MASK
, 0xFFFFFFFF);
746 /* Wait for all the writes to be completed before returning */
751 /* convert depth values to their register representation */
752 static u32
depth_to_dst(u32 depth
)
756 else if (depth
<= 15)
758 else if (depth
== 16)
760 else if (depth
<= 24)
762 else if (depth
<= 32)
769 * PLL informations retreival
774 static void __iomem
* __devinit
aty128_map_ROM(const struct aty128fb_par
*par
, struct pci_dev
*dev
)
781 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
783 temp
= aty_ld_le32(RAGE128_MPP_TB_CONFIG
);
786 aty_st_le32(RAGE128_MPP_TB_CONFIG
, temp
);
787 temp
= aty_ld_le32(RAGE128_MPP_TB_CONFIG
);
789 bios
= pci_map_rom(dev
, &rom_size
);
792 printk(KERN_ERR
"aty128fb: ROM failed to map\n");
796 /* Very simple test to make sure it appeared */
797 if (BIOS_IN16(0) != 0xaa55) {
798 printk(KERN_DEBUG
"aty128fb: Invalid ROM signature %x should "
799 " be 0xaa55\n", BIOS_IN16(0));
803 /* Look for the PCI data to check the ROM type */
804 dptr
= BIOS_IN16(0x18);
806 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
807 * for now, until I've verified this works everywhere. The goal here is more
808 * to phase out Open Firmware images.
810 * Currently, we only look at the first PCI data, we could iteratre and deal with
811 * them all, and we should use fb_bios_start relative to start of image and not
812 * relative start of ROM, but so far, I never found a dual-image ATI card
815 * u32 signature; + 0x00
818 * u16 reserved_1; + 0x08
820 * u8 drevision; + 0x0c
821 * u8 class_hi; + 0x0d
822 * u16 class_lo; + 0x0e
824 * u16 irevision; + 0x12
826 * u8 indicator; + 0x15
827 * u16 reserved_2; + 0x16
830 if (BIOS_IN32(dptr
) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
831 printk(KERN_WARNING
"aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
835 rom_type
= BIOS_IN8(dptr
+ 0x14);
838 printk(KERN_INFO
"aty128fb: Found Intel x86 BIOS ROM Image\n");
841 printk(KERN_INFO
"aty128fb: Found Open Firmware ROM Image\n");
844 printk(KERN_INFO
"aty128fb: Found HP PA-RISC ROM Image\n");
847 printk(KERN_INFO
"aty128fb: Found unknown type %d ROM Image\n", rom_type
);
854 pci_unmap_rom(dev
, bios
);
858 static void __devinit
aty128_get_pllinfo(struct aty128fb_par
*par
, unsigned char __iomem
*bios
)
860 unsigned int bios_hdr
;
861 unsigned int bios_pll
;
863 bios_hdr
= BIOS_IN16(0x48);
864 bios_pll
= BIOS_IN16(bios_hdr
+ 0x30);
866 par
->constants
.ppll_max
= BIOS_IN32(bios_pll
+ 0x16);
867 par
->constants
.ppll_min
= BIOS_IN32(bios_pll
+ 0x12);
868 par
->constants
.xclk
= BIOS_IN16(bios_pll
+ 0x08);
869 par
->constants
.ref_divider
= BIOS_IN16(bios_pll
+ 0x10);
870 par
->constants
.ref_clk
= BIOS_IN16(bios_pll
+ 0x0e);
872 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
873 par
->constants
.ppll_max
, par
->constants
.ppll_min
,
874 par
->constants
.xclk
, par
->constants
.ref_divider
,
875 par
->constants
.ref_clk
);
880 static void __iomem
* __devinit
aty128_find_mem_vbios(struct aty128fb_par
*par
)
882 /* I simplified this code as we used to miss the signatures in
883 * a lot of case. It's now closer to XFree, we just don't check
884 * for signatures at all... Something better will have to be done
885 * if we end up having conflicts
888 unsigned char __iomem
*rom_base
= NULL
;
890 for (segstart
=0x000c0000; segstart
<0x000f0000; segstart
+=0x00001000) {
891 rom_base
= ioremap(segstart
, 0x10000);
892 if (rom_base
== NULL
)
894 if (readb(rom_base
) == 0x55 && readb(rom_base
+ 1) == 0xaa)
902 #endif /* ndef(__sparc__) */
904 /* fill in known card constants if pll_block is not available */
905 static void __devinit
aty128_timings(struct aty128fb_par
*par
)
908 /* instead of a table lookup, assume OF has properly
909 * setup the PLL registers and use their values
910 * to set the XCLK values and reference divider values */
912 u32 x_mpll_ref_fb_div
;
915 unsigned PostDivSet
[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
918 if (!par
->constants
.ref_clk
)
919 par
->constants
.ref_clk
= 2950;
922 x_mpll_ref_fb_div
= aty_ld_pll(X_MPLL_REF_FB_DIV
);
923 xclk_cntl
= aty_ld_pll(XCLK_CNTL
) & 0x7;
924 Nx
= (x_mpll_ref_fb_div
& 0x00ff00) >> 8;
925 M
= x_mpll_ref_fb_div
& 0x0000ff;
927 par
->constants
.xclk
= round_div((2 * Nx
* par
->constants
.ref_clk
),
928 (M
* PostDivSet
[xclk_cntl
]));
930 par
->constants
.ref_divider
=
931 aty_ld_pll(PPLL_REF_DIV
) & PPLL_REF_DIV_MASK
;
934 if (!par
->constants
.ref_divider
) {
935 par
->constants
.ref_divider
= 0x3b;
937 aty_st_pll(X_MPLL_REF_FB_DIV
, 0x004c4c1e);
938 aty_pll_writeupdate(par
);
940 aty_st_pll(PPLL_REF_DIV
, par
->constants
.ref_divider
);
941 aty_pll_writeupdate(par
);
943 /* from documentation */
944 if (!par
->constants
.ppll_min
)
945 par
->constants
.ppll_min
= 12500;
946 if (!par
->constants
.ppll_max
)
947 par
->constants
.ppll_max
= 25000; /* 23000 on some cards? */
948 if (!par
->constants
.xclk
)
949 par
->constants
.xclk
= 0x1d4d; /* same as mclk */
951 par
->constants
.fifo_width
= 128;
952 par
->constants
.fifo_depth
= 32;
954 switch (aty_ld_le32(MEM_CNTL
) & 0x3) {
959 par
->mem
= &sdr_sgram
;
962 par
->mem
= &ddr_sgram
;
965 par
->mem
= &sdr_sgram
;
975 /* Program the CRTC registers */
976 static void aty128_set_crtc(const struct aty128_crtc
*crtc
,
977 const struct aty128fb_par
*par
)
979 aty_st_le32(CRTC_GEN_CNTL
, crtc
->gen_cntl
);
980 aty_st_le32(CRTC_H_TOTAL_DISP
, crtc
->h_total
);
981 aty_st_le32(CRTC_H_SYNC_STRT_WID
, crtc
->h_sync_strt_wid
);
982 aty_st_le32(CRTC_V_TOTAL_DISP
, crtc
->v_total
);
983 aty_st_le32(CRTC_V_SYNC_STRT_WID
, crtc
->v_sync_strt_wid
);
984 aty_st_le32(CRTC_PITCH
, crtc
->pitch
);
985 aty_st_le32(CRTC_OFFSET
, crtc
->offset
);
986 aty_st_le32(CRTC_OFFSET_CNTL
, crtc
->offset_cntl
);
987 /* Disable ATOMIC updating. Is this the right place? */
988 aty_st_pll(PPLL_CNTL
, aty_ld_pll(PPLL_CNTL
) & ~(0x00030000));
992 static int aty128_var_to_crtc(const struct fb_var_screeninfo
*var
,
993 struct aty128_crtc
*crtc
,
994 const struct aty128fb_par
*par
)
996 u32 xres
, yres
, vxres
, vyres
, xoffset
, yoffset
, bpp
, dst
;
997 u32 left
, right
, upper
, lower
, hslen
, vslen
, sync
, vmode
;
998 u32 h_total
, h_disp
, h_sync_strt
, h_sync_wid
, h_sync_pol
;
999 u32 v_total
, v_disp
, v_sync_strt
, v_sync_wid
, v_sync_pol
, c_sync
;
1001 u8 mode_bytpp
[7] = { 0, 0, 1, 2, 2, 3, 4 };
1006 vxres
= var
->xres_virtual
;
1007 vyres
= var
->yres_virtual
;
1008 xoffset
= var
->xoffset
;
1009 yoffset
= var
->yoffset
;
1010 bpp
= var
->bits_per_pixel
;
1011 left
= var
->left_margin
;
1012 right
= var
->right_margin
;
1013 upper
= var
->upper_margin
;
1014 lower
= var
->lower_margin
;
1015 hslen
= var
->hsync_len
;
1016 vslen
= var
->vsync_len
;
1023 depth
= (var
->green
.length
== 6) ? 16 : 15;
1025 /* check for mode eligibility
1026 * accept only non interlaced modes */
1027 if ((vmode
& FB_VMODE_MASK
) != FB_VMODE_NONINTERLACED
)
1030 /* convert (and round up) and validate */
1031 xres
= (xres
+ 7) & ~7;
1032 xoffset
= (xoffset
+ 7) & ~7;
1034 if (vxres
< xres
+ xoffset
)
1035 vxres
= xres
+ xoffset
;
1037 if (vyres
< yres
+ yoffset
)
1038 vyres
= yres
+ yoffset
;
1040 /* convert depth into ATI register depth */
1041 dst
= depth_to_dst(depth
);
1043 if (dst
== -EINVAL
) {
1044 printk(KERN_ERR
"aty128fb: Invalid depth or RGBA\n");
1048 /* convert register depth to bytes per pixel */
1049 bytpp
= mode_bytpp
[dst
];
1051 /* make sure there is enough video ram for the mode */
1052 if ((u32
)(vxres
* vyres
* bytpp
) > par
->vram_size
) {
1053 printk(KERN_ERR
"aty128fb: Not enough memory for mode\n");
1057 h_disp
= (xres
>> 3) - 1;
1058 h_total
= (((xres
+ right
+ hslen
+ left
) >> 3) - 1) & 0xFFFFL
;
1061 v_total
= (yres
+ upper
+ vslen
+ lower
- 1) & 0xFFFFL
;
1063 /* check to make sure h_total and v_total are in range */
1064 if (((h_total
>> 3) - 1) > 0x1ff || (v_total
- 1) > 0x7FF) {
1065 printk(KERN_ERR
"aty128fb: invalid width ranges\n");
1069 h_sync_wid
= (hslen
+ 7) >> 3;
1070 if (h_sync_wid
== 0)
1072 else if (h_sync_wid
> 0x3f) /* 0x3f = max hwidth */
1075 h_sync_strt
= (h_disp
<< 3) + right
;
1078 if (v_sync_wid
== 0)
1080 else if (v_sync_wid
> 0x1f) /* 0x1f = max vwidth */
1083 v_sync_strt
= v_disp
+ lower
;
1085 h_sync_pol
= sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : 1;
1086 v_sync_pol
= sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : 1;
1088 c_sync
= sync
& FB_SYNC_COMP_HIGH_ACT
? (1 << 4) : 0;
1090 crtc
->gen_cntl
= 0x3000000L
| c_sync
| (dst
<< 8);
1092 crtc
->h_total
= h_total
| (h_disp
<< 16);
1093 crtc
->v_total
= v_total
| (v_disp
<< 16);
1095 crtc
->h_sync_strt_wid
= h_sync_strt
| (h_sync_wid
<< 16) |
1097 crtc
->v_sync_strt_wid
= v_sync_strt
| (v_sync_wid
<< 16) |
1100 crtc
->pitch
= vxres
>> 3;
1104 if ((var
->activate
& FB_ACTIVATE_MASK
) == FB_ACTIVATE_NOW
)
1105 crtc
->offset_cntl
= 0x00010000;
1107 crtc
->offset_cntl
= 0;
1109 crtc
->vxres
= vxres
;
1110 crtc
->vyres
= vyres
;
1111 crtc
->xoffset
= xoffset
;
1112 crtc
->yoffset
= yoffset
;
1113 crtc
->depth
= depth
;
1120 static int aty128_pix_width_to_var(int pix_width
, struct fb_var_screeninfo
*var
)
1123 /* fill in pixel info */
1124 var
->red
.msb_right
= 0;
1125 var
->green
.msb_right
= 0;
1126 var
->blue
.offset
= 0;
1127 var
->blue
.msb_right
= 0;
1128 var
->transp
.offset
= 0;
1129 var
->transp
.length
= 0;
1130 var
->transp
.msb_right
= 0;
1131 switch (pix_width
) {
1132 case CRTC_PIX_WIDTH_8BPP
:
1133 var
->bits_per_pixel
= 8;
1134 var
->red
.offset
= 0;
1135 var
->red
.length
= 8;
1136 var
->green
.offset
= 0;
1137 var
->green
.length
= 8;
1138 var
->blue
.length
= 8;
1140 case CRTC_PIX_WIDTH_15BPP
:
1141 var
->bits_per_pixel
= 16;
1142 var
->red
.offset
= 10;
1143 var
->red
.length
= 5;
1144 var
->green
.offset
= 5;
1145 var
->green
.length
= 5;
1146 var
->blue
.length
= 5;
1148 case CRTC_PIX_WIDTH_16BPP
:
1149 var
->bits_per_pixel
= 16;
1150 var
->red
.offset
= 11;
1151 var
->red
.length
= 5;
1152 var
->green
.offset
= 5;
1153 var
->green
.length
= 6;
1154 var
->blue
.length
= 5;
1156 case CRTC_PIX_WIDTH_24BPP
:
1157 var
->bits_per_pixel
= 24;
1158 var
->red
.offset
= 16;
1159 var
->red
.length
= 8;
1160 var
->green
.offset
= 8;
1161 var
->green
.length
= 8;
1162 var
->blue
.length
= 8;
1164 case CRTC_PIX_WIDTH_32BPP
:
1165 var
->bits_per_pixel
= 32;
1166 var
->red
.offset
= 16;
1167 var
->red
.length
= 8;
1168 var
->green
.offset
= 8;
1169 var
->green
.length
= 8;
1170 var
->blue
.length
= 8;
1171 var
->transp
.offset
= 24;
1172 var
->transp
.length
= 8;
1175 printk(KERN_ERR
"aty128fb: Invalid pixel width\n");
1183 static int aty128_crtc_to_var(const struct aty128_crtc
*crtc
,
1184 struct fb_var_screeninfo
*var
)
1186 u32 xres
, yres
, left
, right
, upper
, lower
, hslen
, vslen
, sync
;
1187 u32 h_total
, h_disp
, h_sync_strt
, h_sync_dly
, h_sync_wid
, h_sync_pol
;
1188 u32 v_total
, v_disp
, v_sync_strt
, v_sync_wid
, v_sync_pol
, c_sync
;
1191 /* fun with masking */
1192 h_total
= crtc
->h_total
& 0x1ff;
1193 h_disp
= (crtc
->h_total
>> 16) & 0xff;
1194 h_sync_strt
= (crtc
->h_sync_strt_wid
>> 3) & 0x1ff;
1195 h_sync_dly
= crtc
->h_sync_strt_wid
& 0x7;
1196 h_sync_wid
= (crtc
->h_sync_strt_wid
>> 16) & 0x3f;
1197 h_sync_pol
= (crtc
->h_sync_strt_wid
>> 23) & 0x1;
1198 v_total
= crtc
->v_total
& 0x7ff;
1199 v_disp
= (crtc
->v_total
>> 16) & 0x7ff;
1200 v_sync_strt
= crtc
->v_sync_strt_wid
& 0x7ff;
1201 v_sync_wid
= (crtc
->v_sync_strt_wid
>> 16) & 0x1f;
1202 v_sync_pol
= (crtc
->v_sync_strt_wid
>> 23) & 0x1;
1203 c_sync
= crtc
->gen_cntl
& CRTC_CSYNC_EN
? 1 : 0;
1204 pix_width
= crtc
->gen_cntl
& CRTC_PIX_WIDTH_MASK
;
1206 /* do conversions */
1207 xres
= (h_disp
+ 1) << 3;
1209 left
= ((h_total
- h_sync_strt
- h_sync_wid
) << 3) - h_sync_dly
;
1210 right
= ((h_sync_strt
- h_disp
) << 3) + h_sync_dly
;
1211 hslen
= h_sync_wid
<< 3;
1212 upper
= v_total
- v_sync_strt
- v_sync_wid
;
1213 lower
= v_sync_strt
- v_disp
;
1215 sync
= (h_sync_pol
? 0 : FB_SYNC_HOR_HIGH_ACT
) |
1216 (v_sync_pol
? 0 : FB_SYNC_VERT_HIGH_ACT
) |
1217 (c_sync
? FB_SYNC_COMP_HIGH_ACT
: 0);
1219 aty128_pix_width_to_var(pix_width
, var
);
1223 var
->xres_virtual
= crtc
->vxres
;
1224 var
->yres_virtual
= crtc
->vyres
;
1225 var
->xoffset
= crtc
->xoffset
;
1226 var
->yoffset
= crtc
->yoffset
;
1227 var
->left_margin
= left
;
1228 var
->right_margin
= right
;
1229 var
->upper_margin
= upper
;
1230 var
->lower_margin
= lower
;
1231 var
->hsync_len
= hslen
;
1232 var
->vsync_len
= vslen
;
1234 var
->vmode
= FB_VMODE_NONINTERLACED
;
1239 static void aty128_set_crt_enable(struct aty128fb_par
*par
, int on
)
1242 aty_st_le32(CRTC_EXT_CNTL
, aty_ld_le32(CRTC_EXT_CNTL
) | CRT_CRTC_ON
);
1243 aty_st_le32(DAC_CNTL
, (aty_ld_le32(DAC_CNTL
) | DAC_PALETTE2_SNOOP_EN
));
1245 aty_st_le32(CRTC_EXT_CNTL
, aty_ld_le32(CRTC_EXT_CNTL
) & ~CRT_CRTC_ON
);
1248 static void aty128_set_lcd_enable(struct aty128fb_par
*par
, int on
)
1251 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1252 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
1256 reg
= aty_ld_le32(LVDS_GEN_CNTL
);
1257 reg
|= LVDS_ON
| LVDS_EN
| LVDS_BLON
| LVDS_DIGION
;
1258 reg
&= ~LVDS_DISPLAY_DIS
;
1259 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1260 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1261 mutex_lock(&info
->bl_mutex
);
1263 down(&info
->bl_dev
->sem
);
1264 info
->bl_dev
->props
->update_status(info
->bl_dev
);
1265 up(&info
->bl_dev
->sem
);
1267 mutex_unlock(&info
->bl_mutex
);
1270 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1271 mutex_lock(&info
->bl_mutex
);
1273 down(&info
->bl_dev
->sem
);
1274 info
->bl_dev
->props
->brightness
= 0;
1275 info
->bl_dev
->props
->power
= FB_BLANK_POWERDOWN
;
1276 info
->bl_dev
->props
->update_status(info
->bl_dev
);
1277 up(&info
->bl_dev
->sem
);
1279 mutex_unlock(&info
->bl_mutex
);
1281 reg
= aty_ld_le32(LVDS_GEN_CNTL
);
1282 reg
|= LVDS_DISPLAY_DIS
;
1283 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1285 reg
&= ~(LVDS_ON
/*| LVDS_EN*/);
1286 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1290 static void aty128_set_pll(struct aty128_pll
*pll
, const struct aty128fb_par
*par
)
1294 unsigned char post_conv
[] = /* register values for post dividers */
1295 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1297 /* select PPLL_DIV_3 */
1298 aty_st_le32(CLOCK_CNTL_INDEX
, aty_ld_le32(CLOCK_CNTL_INDEX
) | (3 << 8));
1301 aty_st_pll(PPLL_CNTL
,
1302 aty_ld_pll(PPLL_CNTL
) | PPLL_RESET
| PPLL_ATOMIC_UPDATE_EN
);
1304 /* write the reference divider */
1305 aty_pll_wait_readupdate(par
);
1306 aty_st_pll(PPLL_REF_DIV
, par
->constants
.ref_divider
& 0x3ff);
1307 aty_pll_writeupdate(par
);
1309 div3
= aty_ld_pll(PPLL_DIV_3
);
1310 div3
&= ~PPLL_FB3_DIV_MASK
;
1311 div3
|= pll
->feedback_divider
;
1312 div3
&= ~PPLL_POST3_DIV_MASK
;
1313 div3
|= post_conv
[pll
->post_divider
] << 16;
1315 /* write feedback and post dividers */
1316 aty_pll_wait_readupdate(par
);
1317 aty_st_pll(PPLL_DIV_3
, div3
);
1318 aty_pll_writeupdate(par
);
1320 aty_pll_wait_readupdate(par
);
1321 aty_st_pll(HTOTAL_CNTL
, 0); /* no horiz crtc adjustment */
1322 aty_pll_writeupdate(par
);
1324 /* clear the reset, just in case */
1325 aty_st_pll(PPLL_CNTL
, aty_ld_pll(PPLL_CNTL
) & ~PPLL_RESET
);
1329 static int aty128_var_to_pll(u32 period_in_ps
, struct aty128_pll
*pll
,
1330 const struct aty128fb_par
*par
)
1332 const struct aty128_constants c
= par
->constants
;
1333 unsigned char post_dividers
[] = {1,2,4,8,3,6,12};
1335 u32 vclk
; /* in .01 MHz */
1339 vclk
= 100000000 / period_in_ps
; /* convert units to 10 kHz */
1341 /* adjust pixel clock if necessary */
1342 if (vclk
> c
.ppll_max
)
1344 if (vclk
* 12 < c
.ppll_min
)
1345 vclk
= c
.ppll_min
/12;
1347 /* now, find an acceptable divider */
1348 for (i
= 0; i
< sizeof(post_dividers
); i
++) {
1349 output_freq
= post_dividers
[i
] * vclk
;
1350 if (output_freq
>= c
.ppll_min
&& output_freq
<= c
.ppll_max
) {
1351 pll
->post_divider
= post_dividers
[i
];
1356 /* calculate feedback divider */
1357 n
= c
.ref_divider
* output_freq
;
1360 pll
->feedback_divider
= round_div(n
, d
);
1363 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1364 "vclk_per: %d\n", pll
->post_divider
,
1365 pll
->feedback_divider
, vclk
, output_freq
,
1366 c
.ref_divider
, period_in_ps
);
1372 static int aty128_pll_to_var(const struct aty128_pll
*pll
, struct fb_var_screeninfo
*var
)
1374 var
->pixclock
= 100000000 / pll
->vclk
;
1380 static void aty128_set_fifo(const struct aty128_ddafifo
*dsp
,
1381 const struct aty128fb_par
*par
)
1383 aty_st_le32(DDA_CONFIG
, dsp
->dda_config
);
1384 aty_st_le32(DDA_ON_OFF
, dsp
->dda_on_off
);
1388 static int aty128_ddafifo(struct aty128_ddafifo
*dsp
,
1389 const struct aty128_pll
*pll
,
1391 const struct aty128fb_par
*par
)
1393 const struct aty128_meminfo
*m
= par
->mem
;
1394 u32 xclk
= par
->constants
.xclk
;
1395 u32 fifo_width
= par
->constants
.fifo_width
;
1396 u32 fifo_depth
= par
->constants
.fifo_depth
;
1397 s32 x
, b
, p
, ron
, roff
;
1400 /* round up to multiple of 8 */
1401 bpp
= (depth
+7) & ~7;
1403 n
= xclk
* fifo_width
;
1404 d
= pll
->vclk
* bpp
;
1405 x
= round_div(n
, d
);
1408 3 * ((m
->Trcd
- 2 > 0) ? m
->Trcd
- 2 : 0) +
1427 x
= round_div(n
, d
);
1428 roff
= x
* (fifo_depth
- 4);
1430 if ((ron
+ m
->Rloop
) >= roff
) {
1431 printk(KERN_ERR
"aty128fb: Mode out of range!\n");
1435 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1436 p
, m
->Rloop
, x
, ron
, roff
);
1438 dsp
->dda_config
= p
<< 16 | m
->Rloop
<< 20 | x
;
1439 dsp
->dda_on_off
= ron
<< 16 | roff
;
1446 * This actually sets the video mode.
1448 static int aty128fb_set_par(struct fb_info
*info
)
1450 struct aty128fb_par
*par
= info
->par
;
1454 if ((err
= aty128_decode_var(&info
->var
, par
)) != 0)
1457 if (par
->blitter_may_be_busy
)
1460 /* clear all registers that may interfere with mode setting */
1461 aty_st_le32(OVR_CLR
, 0);
1462 aty_st_le32(OVR_WID_LEFT_RIGHT
, 0);
1463 aty_st_le32(OVR_WID_TOP_BOTTOM
, 0);
1464 aty_st_le32(OV0_SCALE_CNTL
, 0);
1465 aty_st_le32(MPP_TB_CONFIG
, 0);
1466 aty_st_le32(MPP_GP_CONFIG
, 0);
1467 aty_st_le32(SUBPIC_CNTL
, 0);
1468 aty_st_le32(VIPH_CONTROL
, 0);
1469 aty_st_le32(I2C_CNTL_1
, 0); /* turn off i2c */
1470 aty_st_le32(GEN_INT_CNTL
, 0); /* turn off interrupts */
1471 aty_st_le32(CAP0_TRIG_CNTL
, 0);
1472 aty_st_le32(CAP1_TRIG_CNTL
, 0);
1474 aty_st_8(CRTC_EXT_CNTL
+ 1, 4); /* turn video off */
1476 aty128_set_crtc(&par
->crtc
, par
);
1477 aty128_set_pll(&par
->pll
, par
);
1478 aty128_set_fifo(&par
->fifo_reg
, par
);
1480 config
= aty_ld_le32(CONFIG_CNTL
) & ~3;
1482 #if defined(__BIG_ENDIAN)
1483 if (par
->crtc
.bpp
== 32)
1484 config
|= 2; /* make aperture do 32 bit swapping */
1485 else if (par
->crtc
.bpp
== 16)
1486 config
|= 1; /* make aperture do 16 bit swapping */
1489 aty_st_le32(CONFIG_CNTL
, config
);
1490 aty_st_8(CRTC_EXT_CNTL
+ 1, 0); /* turn the video back on */
1492 info
->fix
.line_length
= (par
->crtc
.vxres
* par
->crtc
.bpp
) >> 3;
1493 info
->fix
.visual
= par
->crtc
.bpp
== 8 ? FB_VISUAL_PSEUDOCOLOR
1494 : FB_VISUAL_DIRECTCOLOR
;
1496 if (par
->chip_gen
== rage_M3
) {
1497 aty128_set_crt_enable(par
, par
->crt_on
);
1498 aty128_set_lcd_enable(par
, par
->lcd_on
);
1500 if (par
->accel_flags
& FB_ACCELF_TEXT
)
1501 aty128_init_engine(par
);
1503 #ifdef CONFIG_BOOTX_TEXT
1504 btext_update_display(info
->fix
.smem_start
,
1505 (((par
->crtc
.h_total
>>16) & 0xff)+1)*8,
1506 ((par
->crtc
.v_total
>>16) & 0x7ff)+1,
1508 par
->crtc
.vxres
*par
->crtc
.bpp
/8);
1509 #endif /* CONFIG_BOOTX_TEXT */
1515 * encode/decode the User Defined Part of the Display
1518 static int aty128_decode_var(struct fb_var_screeninfo
*var
, struct aty128fb_par
*par
)
1521 struct aty128_crtc crtc
;
1522 struct aty128_pll pll
;
1523 struct aty128_ddafifo fifo_reg
;
1525 if ((err
= aty128_var_to_crtc(var
, &crtc
, par
)))
1528 if ((err
= aty128_var_to_pll(var
->pixclock
, &pll
, par
)))
1531 if ((err
= aty128_ddafifo(&fifo_reg
, &pll
, crtc
.depth
, par
)))
1536 par
->fifo_reg
= fifo_reg
;
1537 par
->accel_flags
= var
->accel_flags
;
1543 static int aty128_encode_var(struct fb_var_screeninfo
*var
,
1544 const struct aty128fb_par
*par
)
1548 if ((err
= aty128_crtc_to_var(&par
->crtc
, var
)))
1551 if ((err
= aty128_pll_to_var(&par
->pll
, var
)))
1559 var
->accel_flags
= par
->accel_flags
;
1565 static int aty128fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
1567 struct aty128fb_par par
;
1570 par
= *(struct aty128fb_par
*)info
->par
;
1571 if ((err
= aty128_decode_var(var
, &par
)) != 0)
1573 aty128_encode_var(var
, &par
);
1579 * Pan or Wrap the Display
1581 static int aty128fb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*fb
)
1583 struct aty128fb_par
*par
= fb
->par
;
1584 u32 xoffset
, yoffset
;
1588 xres
= (((par
->crtc
.h_total
>> 16) & 0xff) + 1) << 3;
1589 yres
= ((par
->crtc
.v_total
>> 16) & 0x7ff) + 1;
1591 xoffset
= (var
->xoffset
+7) & ~7;
1592 yoffset
= var
->yoffset
;
1594 if (xoffset
+xres
> par
->crtc
.vxres
|| yoffset
+yres
> par
->crtc
.vyres
)
1597 par
->crtc
.xoffset
= xoffset
;
1598 par
->crtc
.yoffset
= yoffset
;
1600 offset
= ((yoffset
* par
->crtc
.vxres
+ xoffset
)*(par
->crtc
.bpp
>> 3)) & ~7;
1602 if (par
->crtc
.bpp
== 24)
1603 offset
+= 8 * (offset
% 3); /* Must be multiple of 8 and 3 */
1605 aty_st_le32(CRTC_OFFSET
, offset
);
1612 * Helper function to store a single palette register
1614 static void aty128_st_pal(u_int regno
, u_int red
, u_int green
, u_int blue
,
1615 struct aty128fb_par
*par
)
1617 if (par
->chip_gen
== rage_M3
) {
1619 /* Note: For now, on M3, we set palette on both heads, which may
1620 * be useless. Can someone with a M3 check this ?
1622 * This code would still be useful if using the second CRTC to
1626 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) | DAC_PALETTE_ACCESS_CNTL
);
1627 aty_st_8(PALETTE_INDEX
, regno
);
1628 aty_st_le32(PALETTE_DATA
, (red
<<16)|(green
<<8)|blue
);
1630 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) & ~DAC_PALETTE_ACCESS_CNTL
);
1633 aty_st_8(PALETTE_INDEX
, regno
);
1634 aty_st_le32(PALETTE_DATA
, (red
<<16)|(green
<<8)|blue
);
1637 static int aty128fb_sync(struct fb_info
*info
)
1639 struct aty128fb_par
*par
= info
->par
;
1641 if (par
->blitter_may_be_busy
)
1647 static int __devinit
aty128fb_setup(char *options
)
1651 if (!options
|| !*options
)
1654 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1655 if (!strncmp(this_opt
, "lcd:", 4)) {
1656 default_lcd_on
= simple_strtoul(this_opt
+4, NULL
, 0);
1658 } else if (!strncmp(this_opt
, "crt:", 4)) {
1659 default_crt_on
= simple_strtoul(this_opt
+4, NULL
, 0);
1663 if(!strncmp(this_opt
, "nomtrr", 6)) {
1668 #ifdef CONFIG_PPC_PMAC
1669 /* vmode and cmode deprecated */
1670 if (!strncmp(this_opt
, "vmode:", 6)) {
1671 unsigned int vmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1672 if (vmode
> 0 && vmode
<= VMODE_MAX
)
1673 default_vmode
= vmode
;
1675 } else if (!strncmp(this_opt
, "cmode:", 6)) {
1676 unsigned int cmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1680 default_cmode
= CMODE_8
;
1684 default_cmode
= CMODE_16
;
1688 default_cmode
= CMODE_32
;
1693 #endif /* CONFIG_PPC_PMAC */
1694 mode_option
= this_opt
;
1701 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1702 #define MAX_LEVEL 0xFF
1704 static struct backlight_properties aty128_bl_data
;
1706 static int aty128_bl_get_level_brightness(struct aty128fb_par
*par
,
1709 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
1712 /* Get and convert the value */
1713 mutex_lock(&info
->bl_mutex
);
1714 atylevel
= MAX_LEVEL
-
1715 (info
->bl_curve
[level
] * FB_BACKLIGHT_MAX
/ MAX_LEVEL
);
1716 mutex_unlock(&info
->bl_mutex
);
1720 else if (atylevel
> MAX_LEVEL
)
1721 atylevel
= MAX_LEVEL
;
1726 /* We turn off the LCD completely instead of just dimming the backlight.
1727 * This provides greater power saving and the display is useless without
1730 #define BACKLIGHT_LVDS_OFF
1731 /* That one prevents proper CRT output with LCD off */
1732 #undef BACKLIGHT_DAC_OFF
1734 static int aty128_bl_update_status(struct backlight_device
*bd
)
1736 struct aty128fb_par
*par
= class_get_devdata(&bd
->class_dev
);
1737 unsigned int reg
= aty_ld_le32(LVDS_GEN_CNTL
);
1740 if (bd
->props
->power
!= FB_BLANK_UNBLANK
||
1741 bd
->props
->fb_blank
!= FB_BLANK_UNBLANK
||
1745 level
= bd
->props
->brightness
;
1747 reg
|= LVDS_BL_MOD_EN
| LVDS_BLON
;
1750 if (!(reg
& LVDS_ON
)) {
1752 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1753 aty_ld_le32(LVDS_GEN_CNTL
);
1756 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1758 reg
&= ~LVDS_BL_MOD_LEVEL_MASK
;
1759 reg
|= (aty128_bl_get_level_brightness(par
, level
) << LVDS_BL_MOD_LEVEL_SHIFT
);
1760 #ifdef BACKLIGHT_LVDS_OFF
1761 reg
|= LVDS_ON
| LVDS_EN
;
1762 reg
&= ~LVDS_DISPLAY_DIS
;
1764 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1765 #ifdef BACKLIGHT_DAC_OFF
1766 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) & (~DAC_PDWN
));
1769 reg
&= ~LVDS_BL_MOD_LEVEL_MASK
;
1770 reg
|= (aty128_bl_get_level_brightness(par
, 0) << LVDS_BL_MOD_LEVEL_SHIFT
);
1771 #ifdef BACKLIGHT_LVDS_OFF
1772 reg
|= LVDS_DISPLAY_DIS
;
1773 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1774 aty_ld_le32(LVDS_GEN_CNTL
);
1776 reg
&= ~(LVDS_ON
| LVDS_EN
| LVDS_BLON
| LVDS_DIGION
);
1778 aty_st_le32(LVDS_GEN_CNTL
, reg
);
1779 #ifdef BACKLIGHT_DAC_OFF
1780 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) | DAC_PDWN
);
1787 static int aty128_bl_get_brightness(struct backlight_device
*bd
)
1789 return bd
->props
->brightness
;
1792 static struct backlight_properties aty128_bl_data
= {
1793 .owner
= THIS_MODULE
,
1794 .get_brightness
= aty128_bl_get_brightness
,
1795 .update_status
= aty128_bl_update_status
,
1796 .max_brightness
= (FB_BACKLIGHT_LEVELS
- 1),
1799 static void aty128_bl_init(struct aty128fb_par
*par
)
1801 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
1802 struct backlight_device
*bd
;
1805 /* Could be extended to Rage128Pro LVDS output too */
1806 if (par
->chip_gen
!= rage_M3
)
1809 #ifdef CONFIG_PMAC_BACKLIGHT
1810 if (!pmac_has_backlight_type("ati"))
1814 snprintf(name
, sizeof(name
), "aty128bl%d", info
->node
);
1816 bd
= backlight_device_register(name
, par
, &aty128_bl_data
);
1818 info
->bl_dev
= NULL
;
1819 printk("aty128: Backlight registration failed\n");
1823 mutex_lock(&info
->bl_mutex
);
1825 fb_bl_default_curve(info
, 0,
1826 63 * FB_BACKLIGHT_MAX
/ MAX_LEVEL
,
1827 219 * FB_BACKLIGHT_MAX
/ MAX_LEVEL
);
1828 mutex_unlock(&info
->bl_mutex
);
1831 bd
->props
->brightness
= aty128_bl_data
.max_brightness
;
1832 bd
->props
->power
= FB_BLANK_UNBLANK
;
1833 bd
->props
->update_status(bd
);
1836 #ifdef CONFIG_PMAC_BACKLIGHT
1837 mutex_lock(&pmac_backlight_mutex
);
1838 if (!pmac_backlight
)
1839 pmac_backlight
= bd
;
1840 mutex_unlock(&pmac_backlight_mutex
);
1843 printk("aty128: Backlight initialized (%s)\n", name
);
1851 static void aty128_bl_exit(struct aty128fb_par
*par
)
1853 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
1855 #ifdef CONFIG_PMAC_BACKLIGHT
1856 mutex_lock(&pmac_backlight_mutex
);
1859 mutex_lock(&info
->bl_mutex
);
1861 #ifdef CONFIG_PMAC_BACKLIGHT
1862 if (pmac_backlight
== info
->bl_dev
)
1863 pmac_backlight
= NULL
;
1866 backlight_device_unregister(info
->bl_dev
);
1867 info
->bl_dev
= NULL
;
1869 printk("aty128: Backlight unloaded\n");
1871 mutex_unlock(&info
->bl_mutex
);
1873 #ifdef CONFIG_PMAC_BACKLIGHT
1874 mutex_unlock(&pmac_backlight_mutex
);
1877 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1883 #ifdef CONFIG_PPC_PMAC
1884 static void aty128_early_resume(void *data
)
1886 struct aty128fb_par
*par
= data
;
1888 if (try_acquire_console_sem())
1890 aty128_do_resume(par
->pdev
);
1891 release_console_sem();
1893 #endif /* CONFIG_PPC_PMAC */
1895 static int __devinit
aty128_init(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1897 struct fb_info
*info
= pci_get_drvdata(pdev
);
1898 struct aty128fb_par
*par
= info
->par
;
1899 struct fb_var_screeninfo var
;
1900 char video_card
[DEVICE_NAME_SIZE
];
1904 if (!par
->vram_size
) /* may have already been probed */
1905 par
->vram_size
= aty_ld_le32(CONFIG_MEMSIZE
) & 0x03FFFFFF;
1907 /* Get the chip revision */
1908 chip_rev
= (aty_ld_le32(CONFIG_CNTL
) >> 16) & 0x1F;
1910 strcpy(video_card
, "Rage128 XX ");
1911 video_card
[8] = ent
->device
>> 8;
1912 video_card
[9] = ent
->device
& 0xFF;
1914 /* range check to make sure */
1915 if (ent
->driver_data
< ARRAY_SIZE(r128_family
))
1916 strncat(video_card
, r128_family
[ent
->driver_data
], sizeof(video_card
));
1918 printk(KERN_INFO
"aty128fb: %s [chip rev 0x%x] ", video_card
, chip_rev
);
1920 if (par
->vram_size
% (1024 * 1024) == 0)
1921 printk("%dM %s\n", par
->vram_size
/ (1024*1024), par
->mem
->name
);
1923 printk("%dk %s\n", par
->vram_size
/ 1024, par
->mem
->name
);
1925 par
->chip_gen
= ent
->driver_data
;
1928 info
->fbops
= &aty128fb_ops
;
1929 info
->flags
= FBINFO_FLAG_DEFAULT
;
1931 par
->lcd_on
= default_lcd_on
;
1932 par
->crt_on
= default_crt_on
;
1935 #ifdef CONFIG_PPC_PMAC
1936 if (machine_is(powermac
)) {
1937 /* Indicate sleep capability */
1938 if (par
->chip_gen
== rage_M3
) {
1939 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE
, NULL
, 0, 1);
1940 pmac_set_early_video_resume(aty128_early_resume
, par
);
1943 /* Find default mode */
1945 if (!mac_find_mode(&var
, info
, mode_option
, 8))
1948 if (default_vmode
<= 0 || default_vmode
> VMODE_MAX
)
1949 default_vmode
= VMODE_1024_768_60
;
1951 /* iMacs need that resolution
1952 * PowerMac2,1 first r128 iMacs
1953 * PowerMac2,2 summer 2000 iMacs
1954 * PowerMac4,1 january 2001 iMacs "flower power"
1956 if (machine_is_compatible("PowerMac2,1") ||
1957 machine_is_compatible("PowerMac2,2") ||
1958 machine_is_compatible("PowerMac4,1"))
1959 default_vmode
= VMODE_1024_768_75
;
1962 if (machine_is_compatible("PowerBook2,2"))
1963 default_vmode
= VMODE_800_600_60
;
1965 /* PowerBook Firewire (Pismo), iBook Dual USB */
1966 if (machine_is_compatible("PowerBook3,1") ||
1967 machine_is_compatible("PowerBook4,1"))
1968 default_vmode
= VMODE_1024_768_60
;
1970 /* PowerBook Titanium */
1971 if (machine_is_compatible("PowerBook3,2"))
1972 default_vmode
= VMODE_1152_768_60
;
1974 if (default_cmode
> 16)
1975 default_cmode
= CMODE_32
;
1976 else if (default_cmode
> 8)
1977 default_cmode
= CMODE_16
;
1979 default_cmode
= CMODE_8
;
1981 if (mac_vmode_to_var(default_vmode
, default_cmode
, &var
))
1985 #endif /* CONFIG_PPC_PMAC */
1988 if (fb_find_mode(&var
, info
, mode_option
, NULL
,
1989 0, &defaultmode
, 8) == 0)
1993 var
.accel_flags
&= ~FB_ACCELF_TEXT
;
1994 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1996 if (aty128fb_check_var(&var
, info
)) {
1997 printk(KERN_ERR
"aty128fb: Cannot set default mode.\n");
2001 /* setup the DAC the way we like it */
2002 dac
= aty_ld_le32(DAC_CNTL
);
2003 dac
|= (DAC_8BIT_EN
| DAC_RANGE_CNTL
);
2005 if (par
->chip_gen
== rage_M3
)
2006 dac
|= DAC_PALETTE2_SNOOP_EN
;
2007 aty_st_le32(DAC_CNTL
, dac
);
2009 /* turn off bus mastering, just in case */
2010 aty_st_le32(BUS_CNTL
, aty_ld_le32(BUS_CNTL
) | BUS_MASTER_DIS
);
2013 fb_alloc_cmap(&info
->cmap
, 256, 0);
2015 var
.activate
= FB_ACTIVATE_NOW
;
2017 aty128_init_engine(par
);
2019 if (register_framebuffer(info
) < 0)
2022 par
->pm_reg
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
2025 par
->lock_blank
= 0;
2027 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2028 aty128_bl_init(par
);
2031 printk(KERN_INFO
"fb%d: %s frame buffer device on %s\n",
2032 info
->node
, info
->fix
.id
, video_card
);
2034 return 1; /* success! */
2038 /* register a card ++ajoshi */
2039 static int __devinit
aty128_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2041 unsigned long fb_addr
, reg_addr
;
2042 struct aty128fb_par
*par
;
2043 struct fb_info
*info
;
2046 void __iomem
*bios
= NULL
;
2049 /* Enable device in PCI config */
2050 if ((err
= pci_enable_device(pdev
))) {
2051 printk(KERN_ERR
"aty128fb: Cannot enable PCI device: %d\n",
2056 fb_addr
= pci_resource_start(pdev
, 0);
2057 if (!request_mem_region(fb_addr
, pci_resource_len(pdev
, 0),
2059 printk(KERN_ERR
"aty128fb: cannot reserve frame "
2064 reg_addr
= pci_resource_start(pdev
, 2);
2065 if (!request_mem_region(reg_addr
, pci_resource_len(pdev
, 2),
2067 printk(KERN_ERR
"aty128fb: cannot reserve MMIO region\n");
2071 /* We have the resources. Now virtualize them */
2072 info
= framebuffer_alloc(sizeof(struct aty128fb_par
), &pdev
->dev
);
2074 printk(KERN_ERR
"aty128fb: can't alloc fb_info_aty128\n");
2079 info
->pseudo_palette
= par
->pseudo_palette
;
2080 info
->fix
= aty128fb_fix
;
2082 /* Virtualize mmio region */
2083 info
->fix
.mmio_start
= reg_addr
;
2084 par
->regbase
= ioremap(reg_addr
, pci_resource_len(pdev
, 2));
2088 /* Grab memory size from the card */
2089 // How does this relate to the resource length from the PCI hardware?
2090 par
->vram_size
= aty_ld_le32(CONFIG_MEMSIZE
) & 0x03FFFFFF;
2092 /* Virtualize the framebuffer */
2093 info
->screen_base
= ioremap(fb_addr
, par
->vram_size
);
2094 if (!info
->screen_base
)
2097 /* Set up info->fix */
2098 info
->fix
= aty128fb_fix
;
2099 info
->fix
.smem_start
= fb_addr
;
2100 info
->fix
.smem_len
= par
->vram_size
;
2101 info
->fix
.mmio_start
= reg_addr
;
2103 /* If we can't test scratch registers, something is seriously wrong */
2104 if (!register_test(par
)) {
2105 printk(KERN_ERR
"aty128fb: Can't write to video register!\n");
2110 bios
= aty128_map_ROM(par
, pdev
);
2113 bios
= aty128_find_mem_vbios(par
);
2116 printk(KERN_INFO
"aty128fb: BIOS not located, guessing timings.\n");
2118 printk(KERN_INFO
"aty128fb: Rage128 BIOS located\n");
2119 aty128_get_pllinfo(par
, bios
);
2120 pci_unmap_rom(pdev
, bios
);
2122 #endif /* __sparc__ */
2124 aty128_timings(par
);
2125 pci_set_drvdata(pdev
, info
);
2127 if (!aty128_init(pdev
, ent
))
2132 par
->mtrr
.vram
= mtrr_add(info
->fix
.smem_start
,
2133 par
->vram_size
, MTRR_TYPE_WRCOMB
, 1);
2134 par
->mtrr
.vram_valid
= 1;
2135 /* let there be speed */
2136 printk(KERN_INFO
"aty128fb: Rage128 MTRR set to ON\n");
2138 #endif /* CONFIG_MTRR */
2142 iounmap(info
->screen_base
);
2144 iounmap(par
->regbase
);
2146 framebuffer_release(info
);
2148 release_mem_region(pci_resource_start(pdev
, 2),
2149 pci_resource_len(pdev
, 2));
2151 release_mem_region(pci_resource_start(pdev
, 0),
2152 pci_resource_len(pdev
, 0));
2156 static void __devexit
aty128_remove(struct pci_dev
*pdev
)
2158 struct fb_info
*info
= pci_get_drvdata(pdev
);
2159 struct aty128fb_par
*par
;
2166 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2167 aty128_bl_exit(par
);
2170 unregister_framebuffer(info
);
2172 if (par
->mtrr
.vram_valid
)
2173 mtrr_del(par
->mtrr
.vram
, info
->fix
.smem_start
,
2175 #endif /* CONFIG_MTRR */
2176 iounmap(par
->regbase
);
2177 iounmap(info
->screen_base
);
2179 release_mem_region(pci_resource_start(pdev
, 0),
2180 pci_resource_len(pdev
, 0));
2181 release_mem_region(pci_resource_start(pdev
, 2),
2182 pci_resource_len(pdev
, 2));
2183 framebuffer_release(info
);
2185 #endif /* CONFIG_PCI */
2190 * Blank the display.
2192 static int aty128fb_blank(int blank
, struct fb_info
*fb
)
2194 struct aty128fb_par
*par
= fb
->par
;
2197 if (par
->lock_blank
|| par
->asleep
)
2200 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2201 if (machine_is(powermac
) && blank
) {
2202 down(&fb
->bl_dev
->sem
);
2203 fb
->bl_dev
->props
->power
= FB_BLANK_POWERDOWN
;
2204 fb
->bl_dev
->props
->update_status(fb
->bl_dev
);
2205 up(&fb
->bl_dev
->sem
);
2209 if (blank
& FB_BLANK_VSYNC_SUSPEND
)
2211 if (blank
& FB_BLANK_HSYNC_SUSPEND
)
2213 if (blank
& FB_BLANK_POWERDOWN
)
2216 aty_st_8(CRTC_EXT_CNTL
+1, state
);
2218 if (par
->chip_gen
== rage_M3
) {
2219 aty128_set_crt_enable(par
, par
->crt_on
&& !blank
);
2220 aty128_set_lcd_enable(par
, par
->lcd_on
&& !blank
);
2222 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2223 if (machine_is(powermac
) && !blank
) {
2224 down(&fb
->bl_dev
->sem
);
2225 fb
->bl_dev
->props
->power
= FB_BLANK_UNBLANK
;
2226 fb
->bl_dev
->props
->update_status(fb
->bl_dev
);
2227 up(&fb
->bl_dev
->sem
);
2234 * Set a single color register. The values supplied are already
2235 * rounded down to the hardware's capabilities (according to the
2236 * entries in the var structure). Return != 0 for invalid regno.
2238 static int aty128fb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
2239 u_int transp
, struct fb_info
*info
)
2241 struct aty128fb_par
*par
= info
->par
;
2244 || (par
->crtc
.depth
== 16 && regno
> 63)
2245 || (par
->crtc
.depth
== 15 && regno
> 31))
2254 u32
*pal
= info
->pseudo_palette
;
2256 switch (par
->crtc
.depth
) {
2258 pal
[regno
] = (regno
<< 10) | (regno
<< 5) | regno
;
2261 pal
[regno
] = (regno
<< 11) | (regno
<< 6) | regno
;
2264 pal
[regno
] = (regno
<< 16) | (regno
<< 8) | regno
;
2267 i
= (regno
<< 8) | regno
;
2268 pal
[regno
] = (i
<< 16) | i
;
2273 if (par
->crtc
.depth
== 16 && regno
> 0) {
2275 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2276 * have 32 slots for R and B values but 64 slots for G values.
2277 * Thus the R and B values go in one slot but the G value
2278 * goes in a different slot, and we have to avoid disturbing
2279 * the other fields in the slots we touch.
2281 par
->green
[regno
] = green
;
2283 par
->red
[regno
] = red
;
2284 par
->blue
[regno
] = blue
;
2285 aty128_st_pal(regno
* 8, red
, par
->green
[regno
*2],
2288 red
= par
->red
[regno
/2];
2289 blue
= par
->blue
[regno
/2];
2291 } else if (par
->crtc
.bpp
== 16)
2293 aty128_st_pal(regno
, red
, green
, blue
, par
);
2298 #define ATY_MIRROR_LCD_ON 0x00000001
2299 #define ATY_MIRROR_CRT_ON 0x00000002
2301 /* out param: u32* backlight value: 0 to 15 */
2302 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2303 /* in param: u32* backlight value: 0 to 15 */
2304 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2306 static int aty128fb_ioctl(struct fb_info
*info
, u_int cmd
, u_long arg
)
2308 struct aty128fb_par
*par
= info
->par
;
2313 case FBIO_ATY128_SET_MIRROR
:
2314 if (par
->chip_gen
!= rage_M3
)
2316 rc
= get_user(value
, (__u32 __user
*)arg
);
2319 par
->lcd_on
= (value
& 0x01) != 0;
2320 par
->crt_on
= (value
& 0x02) != 0;
2321 if (!par
->crt_on
&& !par
->lcd_on
)
2323 aty128_set_crt_enable(par
, par
->crt_on
);
2324 aty128_set_lcd_enable(par
, par
->lcd_on
);
2326 case FBIO_ATY128_GET_MIRROR
:
2327 if (par
->chip_gen
!= rage_M3
)
2329 value
= (par
->crt_on
<< 1) | par
->lcd_on
;
2330 return put_user(value
, (__u32 __user
*)arg
);
2337 * Accelerated functions
2340 static inline void aty128_rectcopy(int srcx
, int srcy
, int dstx
, int dsty
,
2341 u_int width
, u_int height
,
2342 struct fb_info_aty128
*par
)
2344 u32 save_dp_datatype
, save_dp_cntl
, dstval
;
2346 if (!width
|| !height
)
2349 dstval
= depth_to_dst(par
->current_par
.crtc
.depth
);
2350 if (dstval
== DST_24BPP
) {
2354 } else if (dstval
== -EINVAL
) {
2355 printk("aty128fb: invalid depth or RGBA\n");
2359 wait_for_fifo(2, par
);
2360 save_dp_datatype
= aty_ld_le32(DP_DATATYPE
);
2361 save_dp_cntl
= aty_ld_le32(DP_CNTL
);
2363 wait_for_fifo(6, par
);
2364 aty_st_le32(SRC_Y_X
, (srcy
<< 16) | srcx
);
2365 aty_st_le32(DP_MIX
, ROP3_SRCCOPY
| DP_SRC_RECT
);
2366 aty_st_le32(DP_CNTL
, DST_X_LEFT_TO_RIGHT
| DST_Y_TOP_TO_BOTTOM
);
2367 aty_st_le32(DP_DATATYPE
, save_dp_datatype
| dstval
| SRC_DSTCOLOR
);
2369 aty_st_le32(DST_Y_X
, (dsty
<< 16) | dstx
);
2370 aty_st_le32(DST_HEIGHT_WIDTH
, (height
<< 16) | width
);
2372 par
->blitter_may_be_busy
= 1;
2374 wait_for_fifo(2, par
);
2375 aty_st_le32(DP_DATATYPE
, save_dp_datatype
);
2376 aty_st_le32(DP_CNTL
, save_dp_cntl
);
2381 * Text mode accelerated functions
2384 static void fbcon_aty128_bmove(struct display
*p
, int sy
, int sx
, int dy
, int dx
,
2385 int height
, int width
)
2388 sy
*= fontheight(p
);
2390 dy
*= fontheight(p
);
2391 width
*= fontwidth(p
);
2392 height
*= fontheight(p
);
2394 aty128_rectcopy(sx
, sy
, dx
, dy
, width
, height
,
2395 (struct fb_info_aty128
*)p
->fb_info
);
2399 static void aty128_set_suspend(struct aty128fb_par
*par
, int suspend
)
2403 struct pci_dev
*pdev
= par
->pdev
;
2408 /* Set the chip into the appropriate suspend mode (we use D2,
2409 * D3 would require a complete re-initialisation of the chip,
2410 * including PCI config registers, clocks, AGP configuration, ...)
2413 /* Make sure CRTC2 is reset. Remove that the day we decide to
2414 * actually use CRTC2 and replace it with real code for disabling
2415 * the CRTC2 output during sleep
2417 aty_st_le32(CRTC2_GEN_CNTL
, aty_ld_le32(CRTC2_GEN_CNTL
) &
2420 /* Set the power management mode to be PCI based */
2421 /* Use this magic value for now */
2423 aty_st_pll(POWER_MANAGEMENT
, pmgt
);
2424 (void)aty_ld_pll(POWER_MANAGEMENT
);
2425 aty_st_le32(BUS_CNTL1
, 0x00000010);
2426 aty_st_le32(MEM_POWER_MISC
, 0x0c830000);
2428 pci_read_config_word(pdev
, par
->pm_reg
+PCI_PM_CTRL
, &pwr_command
);
2429 /* Switch PCI power management to D2 */
2430 pci_write_config_word(pdev
, par
->pm_reg
+PCI_PM_CTRL
,
2431 (pwr_command
& ~PCI_PM_CTRL_STATE_MASK
) | 2);
2432 pci_read_config_word(pdev
, par
->pm_reg
+PCI_PM_CTRL
, &pwr_command
);
2434 /* Switch back PCI power management to D0 */
2436 pci_write_config_word(pdev
, par
->pm_reg
+PCI_PM_CTRL
, 0);
2437 pci_read_config_word(pdev
, par
->pm_reg
+PCI_PM_CTRL
, &pwr_command
);
2442 static int aty128_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2444 struct fb_info
*info
= pci_get_drvdata(pdev
);
2445 struct aty128fb_par
*par
= info
->par
;
2447 /* We don't do anything but D2, for now we return 0, but
2448 * we may want to change that. How do we know if the BIOS
2449 * can properly take care of D3 ? Also, with swsusp, we
2450 * know we'll be rebooted, ...
2452 #ifndef CONFIG_PPC_PMAC
2453 /* HACK ALERT ! Once I find a proper way to say to each driver
2454 * individually what will happen with it's PCI slot, I'll change
2455 * that. On laptops, the AGP slot is just unclocked, so D2 is
2456 * expected, while on desktops, the card is powered off
2459 #endif /* CONFIG_PPC_PMAC */
2461 if (state
.event
== pdev
->dev
.power
.power_state
.event
)
2464 printk(KERN_DEBUG
"aty128fb: suspending...\n");
2466 acquire_console_sem();
2468 fb_set_suspend(info
, 1);
2470 /* Make sure engine is reset */
2472 aty128_reset_engine(par
);
2475 /* Blank display and LCD */
2476 aty128fb_blank(VESA_POWERDOWN
, info
);
2480 par
->lock_blank
= 1;
2482 #ifdef CONFIG_PPC_PMAC
2483 /* On powermac, we have hooks to properly suspend/resume AGP now,
2484 * use them here. We'll ultimately need some generic support here,
2485 * but the generic code isn't quite ready for that yet
2487 pmac_suspend_agp_for_card(pdev
);
2488 #endif /* CONFIG_PPC_PMAC */
2490 /* We need a way to make sure the fbdev layer will _not_ touch the
2491 * framebuffer before we put the chip to suspend state. On 2.4, I
2492 * used dummy fb ops, 2.5 need proper support for this at the
2495 if (state
.event
!= PM_EVENT_ON
)
2496 aty128_set_suspend(par
, 1);
2498 release_console_sem();
2500 pdev
->dev
.power
.power_state
= state
;
2505 static int aty128_do_resume(struct pci_dev
*pdev
)
2507 struct fb_info
*info
= pci_get_drvdata(pdev
);
2508 struct aty128fb_par
*par
= info
->par
;
2510 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_ON
)
2514 aty128_set_suspend(par
, 0);
2517 /* Restore display & engine */
2518 aty128_reset_engine(par
);
2520 aty128fb_set_par(info
);
2521 fb_pan_display(info
, &info
->var
);
2522 fb_set_cmap(&info
->cmap
, info
);
2525 fb_set_suspend(info
, 0);
2528 par
->lock_blank
= 0;
2529 aty128fb_blank(0, info
);
2531 #ifdef CONFIG_PPC_PMAC
2532 /* On powermac, we have hooks to properly suspend/resume AGP now,
2533 * use them here. We'll ultimately need some generic support here,
2534 * but the generic code isn't quite ready for that yet
2536 pmac_resume_agp_for_card(pdev
);
2537 #endif /* CONFIG_PPC_PMAC */
2539 pdev
->dev
.power
.power_state
= PMSG_ON
;
2541 printk(KERN_DEBUG
"aty128fb: resumed !\n");
2546 static int aty128_pci_resume(struct pci_dev
*pdev
)
2550 acquire_console_sem();
2551 rc
= aty128_do_resume(pdev
);
2552 release_console_sem();
2558 static int __devinit
aty128fb_init(void)
2561 char *option
= NULL
;
2563 if (fb_get_options("aty128fb", &option
))
2565 aty128fb_setup(option
);
2568 return pci_register_driver(&aty128fb_driver
);
2571 static void __exit
aty128fb_exit(void)
2573 pci_unregister_driver(&aty128fb_driver
);
2576 module_init(aty128fb_init
);
2578 module_exit(aty128fb_exit
);
2580 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2581 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2582 MODULE_LICENSE("GPL");
2583 module_param(mode_option
, charp
, 0);
2584 MODULE_PARM_DESC(mode_option
, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2586 module_param_named(nomtrr
, mtrr
, invbool
, 0);
2587 MODULE_PARM_DESC(nomtrr
, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");