include/asm-arm/cacheflush.h

   1 /*
   2  *  linux/include/asm-arm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/config.h>
  14 #include <linux/sched.h>
  15 #include <linux/mm.h>
  16
  17 #include <asm/glue.h>
  18 #include <asm/shmparam.h>
  19
  20 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  21
  22 /*
  23  *      Cache Model
  24  *      ===========
  25  */
  26 #undef _CACHE
  27 #undef MULTI_CACHE
  28
  29 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
  30 # ifdef _CACHE
  31 #  define MULTI_CACHE 1
  32 # else
  33 #  define _CACHE v3
  34 # endif
  35 #endif
  36
  37 #if defined(CONFIG_CPU_ARM720T)
  38 # ifdef _CACHE
  39 #  define MULTI_CACHE 1
  40 # else
  41 #  define _CACHE v4
  42 # endif
  43 #endif
  44
  45 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  46     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  47 # define MULTI_CACHE 1
  48 #endif
  49
  50 #if defined(CONFIG_CPU_ARM926T)
  51 # ifdef _CACHE
  52 #  define MULTI_CACHE 1
  53 # else
  54 #  define _CACHE arm926
  55 # endif
  56 #endif
  57
  58 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
  59 # ifdef _CACHE
  60 #  define MULTI_CACHE 1
  61 # else
  62 #  define _CACHE v4wb
  63 # endif
  64 #endif
  65
  66 #if defined(CONFIG_CPU_XSCALE)
  67 # ifdef _CACHE
  68 #  define MULTI_CACHE 1
  69 # else
  70 #  define _CACHE xscale
  71 # endif
  72 #endif
  73
  74 #if defined(CONFIG_CPU_XSC3)
  75 # ifdef _CACHE
  76 #  define MULTI_CACHE 1
  77 # else
  78 #  define _CACHE xsc3
  79 # endif
  80 #endif
  81
  82 #if defined(CONFIG_CPU_V6)
  83 //# ifdef _CACHE
  84 #  define MULTI_CACHE 1
  85 //# else
  86 //#  define _CACHE v6
  87 //# endif
  88 #endif
  89
  90 #if !defined(_CACHE) && !defined(MULTI_CACHE)
  91 #error Unknown cache maintainence model
  92 #endif
  93
  94 /*
  95  * This flag is used to indicate that the page pointed to by a pte
  96  * is dirty and requires cleaning before returning it to the user.
  97  */
  98 #define PG_dcache_dirty PG_arch_1
  99
 100 /*
 101  *      MM Cache Management
 102  *      ===================
 103  *
 104  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 105  *      implement these methods.
 106  *
 107  *      Start addresses are inclusive and end addresses are exclusive;
 108  *      start addresses should be rounded down, end addresses up.
 109  *
 110  *      See Documentation/cachetlb.txt for more information.
 111  *      Please note that the implementation of these, and the required
 112  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 113  *
 114  *      flush_cache_kern_all()
 115  *
 116  *              Unconditionally clean and invalidate the entire cache.
 117  *
 118  *      flush_cache_user_mm(mm)
 119  *
 120  *              Clean and invalidate all user space cache entries
 121  *              before a change of page tables.
 122  *
 123  *      flush_cache_user_range(start, end, flags)
 124  *
 125  *              Clean and invalidate a range of cache entries in the
 126  *              specified address space before a change of page tables.
 127  *              - start - user start address (inclusive, page aligned)
 128  *              - end   - user end address   (exclusive, page aligned)
 129  *              - flags - vma->vm_flags field
 130  *
 131  *      coherent_kern_range(start, end)
 132  *
 133  *              Ensure coherency between the Icache and the Dcache in the
 134  *              region described by start, end.  If you have non-snooping
 135  *              Harvard caches, you need to implement this function.
 136  *              - start  - virtual start address
 137  *              - end    - virtual end address
 138  *
 139  *      DMA Cache Coherency
 140  *      ===================
 141  *
 142  *      dma_inv_range(start, end)
 143  *
 144  *              Invalidate (discard) the specified virtual address range.
 145  *              May not write back any entries.  If 'start' or 'end'
 146  *              are not cache line aligned, those lines must be written
 147  *              back.
 148  *              - start  - virtual start address
 149  *              - end    - virtual end address
 150  *
 151  *      dma_clean_range(start, end)
 152  *
 153  *              Clean (write back) the specified virtual address range.
 154  *              - start  - virtual start address
 155  *              - end    - virtual end address
 156  *
 157  *      dma_flush_range(start, end)
 158  *
 159  *              Clean and invalidate the specified virtual address range.
 160  *              - start  - virtual start address
 161  *              - end    - virtual end address
 162  */
 163
 164 struct cpu_cache_fns {
 165         void (*flush_kern_all)(void);
 166         void (*flush_user_all)(void);
 167         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 168
 169         void (*coherent_kern_range)(unsigned long, unsigned long);
 170         void (*coherent_user_range)(unsigned long, unsigned long);
 171         void (*flush_kern_dcache_page)(void *);
 172
 173         void (*dma_inv_range)(unsigned long, unsigned long);
 174         void (*dma_clean_range)(unsigned long, unsigned long);
 175         void (*dma_flush_range)(unsigned long, unsigned long);
 176 };
 177
 178 /*
 179  * Select the calling method
 180  */
 181 #ifdef MULTI_CACHE
 182
 183 extern struct cpu_cache_fns cpu_cache;
 184
 185 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 186 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 187 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 188 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 189 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 190 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 191
 192 /*
 193  * These are private to the dma-mapping API.  Do not use directly.
 194  * Their sole purpose is to ensure that data held in the cache
 195  * is visible to DMA, or data written by DMA to system memory is
 196  * visible to the CPU.
 197  */
 198 #define dmac_inv_range                  cpu_cache.dma_inv_range
 199 #define dmac_clean_range                cpu_cache.dma_clean_range
 200 #define dmac_flush_range                cpu_cache.dma_flush_range
 201
 202 #else
 203
 204 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 205 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 206 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 207 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 208 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 209 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 210
 211 extern void __cpuc_flush_kern_all(void);
 212 extern void __cpuc_flush_user_all(void);
 213 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 214 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 215 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 216 extern void __cpuc_flush_dcache_page(void *);
 217
 218 /*
 219  * These are private to the dma-mapping API.  Do not use directly.
 220  * Their sole purpose is to ensure that data held in the cache
 221  * is visible to DMA, or data written by DMA to system memory is
 222  * visible to the CPU.
 223  */
 224 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 225 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 226 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 227
 228 extern void dmac_inv_range(unsigned long, unsigned long);
 229 extern void dmac_clean_range(unsigned long, unsigned long);
 230 extern void dmac_flush_range(unsigned long, unsigned long);
 231
 232 #endif
 233
 234 /*
 235  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 236  * vmalloc, ioremap etc) in kernel space for pages.  Since the
 237  * direct-mappings of these pages may contain cached data, we need
 238  * to do a full cache flush to ensure that writebacks don't corrupt
 239  * data placed into these pages via the new mappings.
 240  */
 241 #define flush_cache_vmap(start, end)            flush_cache_all()
 242 #define flush_cache_vunmap(start, end)          flush_cache_all()
 243
 244 /*
 245  * Copy user data from/to a page which is mapped into a different
 246  * processes address space.  Really, we want to allow our "user
 247  * space" model to handle this.
 248  */
 249 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 250         do {                                                    \
 251                 flush_cache_page(vma, vaddr, page_to_pfn(page));\
 252                 memcpy(dst, src, len);                          \
 253                 flush_dcache_page(page);                        \
 254         } while (0)
 255
 256 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 257         do {                                                    \
 258                 flush_cache_page(vma, vaddr, page_to_pfn(page));\
 259                 memcpy(dst, src, len);                          \
 260         } while (0)
 261
 262 /*
 263  * Convert calls to our calling convention.
 264  */
 265 #define flush_cache_all()               __cpuc_flush_kern_all()
 266 #ifndef CONFIG_CPU_CACHE_VIPT
 267 static inline void flush_cache_mm(struct mm_struct *mm)
 268 {
 269         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
 270                 __cpuc_flush_user_all();
 271 }
 272
 273 static inline void
 274 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 275 {
 276         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
 277                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 278                                         vma->vm_flags);
 279 }
 280
 281 static inline void
 282 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 283 {
 284         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 285                 unsigned long addr = user_addr & PAGE_MASK;
 286                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 287         }
 288 }
 289 #else
 290 extern void flush_cache_mm(struct mm_struct *mm);
 291 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 292 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
 293 #endif
 294
 295 /*
 296  * flush_cache_user_range is used when we want to ensure that the
 297  * Harvard caches are synchronised for the user space address range.
 298  * This is used for the ARM private sys_cacheflush system call.
 299  */
 300 #define flush_cache_user_range(vma,start,end) \
 301         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 302
 303 /*
 304  * Perform necessary cache operations to ensure that data previously
 305  * stored within this range of addresses can be executed by the CPU.
 306  */
 307 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 308
 309 /*
 310  * Perform necessary cache operations to ensure that the TLB will
 311  * see data written in the specified area.
 312  */
 313 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 314
 315 /*
 316  * flush_dcache_page is used when the kernel has written to the page
 317  * cache page at virtual address page->virtual.
 318  *
 319  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 320  * have userspace mappings, then we _must_ always clean + invalidate
 321  * the dcache entries associated with the kernel mapping.
 322  *
 323  * Otherwise we can defer the operation, and clean the cache when we are
 324  * about to change to user space.  This is the same method as used on SPARC64.
 325  * See update_mmu_cache for the user space part.
 326  */
 327 extern void flush_dcache_page(struct page *);
 328
 329 #define flush_dcache_mmap_lock(mapping) \
 330         write_lock_irq(&(mapping)->tree_lock)
 331 #define flush_dcache_mmap_unlock(mapping) \
 332         write_unlock_irq(&(mapping)->tree_lock)
 333
 334 #define flush_icache_user_range(vma,page,addr,len) \
 335         flush_dcache_page(page)
 336
 337 /*
 338  * We don't appear to need to do anything here.  In fact, if we did, we'd
 339  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 340  */
 341 #define flush_icache_page(vma,page)     do { } while (0)
 342
 343 #define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
 344 #define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
 345 #define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
 346 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
 347 #define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
 348
 349 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
 350
 351 #define cache_is_vivt()                 1
 352 #define cache_is_vipt()                 0
 353 #define cache_is_vipt_nonaliasing()     0
 354 #define cache_is_vipt_aliasing()        0
 355
 356 #elif defined(CONFIG_CPU_CACHE_VIPT)
 357
 358 #define cache_is_vivt()                 0
 359 #define cache_is_vipt()                 1
 360 #define cache_is_vipt_nonaliasing()                                     \
 361         ({                                                              \
 362                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 363                 __cacheid_vipt_nonaliasing(__val);                      \
 364         })
 365
 366 #define cache_is_vipt_aliasing()                                        \
 367         ({                                                              \
 368                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 369                 __cacheid_vipt_aliasing(__val);                         \
 370         })
 371
 372 #else
 373
 374 #define cache_is_vivt()                                                 \
 375         ({                                                              \
 376                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 377                 (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
 378         })
 379
 380 #define cache_is_vipt()                                                 \
 381         ({                                                              \
 382                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 383                 __cacheid_present(__val) && __cacheid_vipt(__val);      \
 384         })
 385
 386 #define cache_is_vipt_nonaliasing()                                     \
 387         ({                                                              \
 388                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 389                 __cacheid_present(__val) &&                             \
 390                  __cacheid_vipt_nonaliasing(__val);                     \
 391         })
 392
 393 #define cache_is_vipt_aliasing()                                        \
 394         ({                                                              \
 395                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 396                 __cacheid_present(__val) &&                             \
 397                  __cacheid_vipt_aliasing(__val);                        \
 398         })
 399
 400 #endif
 401
 402 #endif