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e1000: Remove unneeded and unwanted memsets
[linux-2.6/linux-loongson.git] / drivers / ata / sata_nv.c
blobd65ebfd7c7b220537d961a06725fecb6490cb7be
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "sata_nv"
46 #define DRV_VERSION "2.0"
47
48 enum {
49 NV_PORTS = 2,
50 NV_PIO_MASK = 0x1f,
51 NV_MWDMA_MASK = 0x07,
52 NV_UDMA_MASK = 0x7f,
53 NV_PORT0_SCR_REG_OFFSET = 0x00,
54 NV_PORT1_SCR_REG_OFFSET = 0x40,
55
56 /* INT_STATUS/ENABLE */
57 NV_INT_STATUS = 0x10,
58 NV_INT_ENABLE = 0x11,
59 NV_INT_STATUS_CK804 = 0x440,
60 NV_INT_ENABLE_CK804 = 0x441,
61
62 /* INT_STATUS/ENABLE bits */
63 NV_INT_DEV = 0x01,
64 NV_INT_PM = 0x02,
65 NV_INT_ADDED = 0x04,
66 NV_INT_REMOVED = 0x08,
67
68 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
69
70 NV_INT_ALL = 0x0f,
71 NV_INT_MASK = NV_INT_DEV |
72 NV_INT_ADDED | NV_INT_REMOVED,
73
74 /* INT_CONFIG */
75 NV_INT_CONFIG = 0x12,
76 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
77
78 // For PCI config register 20
79 NV_MCP_SATA_CFG_20 = 0x50,
80 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
81 };
82
83 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void nv_ck804_host_stop(struct ata_host *host);
85 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
86 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
87 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
88 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
89 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
90
91 static void nv_nf2_freeze(struct ata_port *ap);
92 static void nv_nf2_thaw(struct ata_port *ap);
93 static void nv_ck804_freeze(struct ata_port *ap);
94 static void nv_ck804_thaw(struct ata_port *ap);
95 static void nv_error_handler(struct ata_port *ap);
96
97 enum nv_host_type
98 {
99 GENERIC,
100 NFORCE2,
101 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
102 CK804
103 };
104
105 static const struct pci_device_id nv_pci_tbl[] = {
106 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
107 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
108 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
109 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
110 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
111 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
112 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
113 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
114 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
115 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
116 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
117 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
118 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
119 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
120 { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC }, /* MCP65 */
121 { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC }, /* MCP65 */
122 { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC }, /* MCP65 */
123 { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC }, /* MCP65 */
124 { PCI_VDEVICE(NVIDIA, 0x0550), GENERIC }, /* MCP67 */
125 { PCI_VDEVICE(NVIDIA, 0x0551), GENERIC }, /* MCP67 */
126 { PCI_VDEVICE(NVIDIA, 0x0552), GENERIC }, /* MCP67 */
127 { PCI_VDEVICE(NVIDIA, 0x0553), GENERIC }, /* MCP67 */
128 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
129 PCI_ANY_ID, PCI_ANY_ID,
130 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
131 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
132 PCI_ANY_ID, PCI_ANY_ID,
133 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
134
135 { } /* terminate list */
136 };
137
138 static struct pci_driver nv_pci_driver = {
139 .name = DRV_NAME,
140 .id_table = nv_pci_tbl,
141 .probe = nv_init_one,
142 .remove = ata_pci_remove_one,
143 };
144
145 static struct scsi_host_template nv_sht = {
146 .module = THIS_MODULE,
147 .name = DRV_NAME,
148 .ioctl = ata_scsi_ioctl,
149 .queuecommand = ata_scsi_queuecmd,
150 .can_queue = ATA_DEF_QUEUE,
151 .this_id = ATA_SHT_THIS_ID,
152 .sg_tablesize = LIBATA_MAX_PRD,
153 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
154 .emulated = ATA_SHT_EMULATED,
155 .use_clustering = ATA_SHT_USE_CLUSTERING,
156 .proc_name = DRV_NAME,
157 .dma_boundary = ATA_DMA_BOUNDARY,
158 .slave_configure = ata_scsi_slave_config,
159 .slave_destroy = ata_scsi_slave_destroy,
160 .bios_param = ata_std_bios_param,
161 };
162
163 static const struct ata_port_operations nv_generic_ops = {
164 .port_disable = ata_port_disable,
165 .tf_load = ata_tf_load,
166 .tf_read = ata_tf_read,
167 .exec_command = ata_exec_command,
168 .check_status = ata_check_status,
169 .dev_select = ata_std_dev_select,
170 .bmdma_setup = ata_bmdma_setup,
171 .bmdma_start = ata_bmdma_start,
172 .bmdma_stop = ata_bmdma_stop,
173 .bmdma_status = ata_bmdma_status,
174 .qc_prep = ata_qc_prep,
175 .qc_issue = ata_qc_issue_prot,
176 .freeze = ata_bmdma_freeze,
177 .thaw = ata_bmdma_thaw,
178 .error_handler = nv_error_handler,
179 .post_internal_cmd = ata_bmdma_post_internal_cmd,
180 .data_xfer = ata_pio_data_xfer,
181 .irq_handler = nv_generic_interrupt,
182 .irq_clear = ata_bmdma_irq_clear,
183 .scr_read = nv_scr_read,
184 .scr_write = nv_scr_write,
185 .port_start = ata_port_start,
186 .port_stop = ata_port_stop,
187 .host_stop = ata_pci_host_stop,
188 };
189
190 static const struct ata_port_operations nv_nf2_ops = {
191 .port_disable = ata_port_disable,
192 .tf_load = ata_tf_load,
193 .tf_read = ata_tf_read,
194 .exec_command = ata_exec_command,
195 .check_status = ata_check_status,
196 .dev_select = ata_std_dev_select,
197 .bmdma_setup = ata_bmdma_setup,
198 .bmdma_start = ata_bmdma_start,
199 .bmdma_stop = ata_bmdma_stop,
200 .bmdma_status = ata_bmdma_status,
201 .qc_prep = ata_qc_prep,
202 .qc_issue = ata_qc_issue_prot,
203 .freeze = nv_nf2_freeze,
204 .thaw = nv_nf2_thaw,
205 .error_handler = nv_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
207 .data_xfer = ata_pio_data_xfer,
208 .irq_handler = nv_nf2_interrupt,
209 .irq_clear = ata_bmdma_irq_clear,
210 .scr_read = nv_scr_read,
211 .scr_write = nv_scr_write,
212 .port_start = ata_port_start,
213 .port_stop = ata_port_stop,
214 .host_stop = ata_pci_host_stop,
215 };
216
217 static const struct ata_port_operations nv_ck804_ops = {
218 .port_disable = ata_port_disable,
219 .tf_load = ata_tf_load,
220 .tf_read = ata_tf_read,
221 .exec_command = ata_exec_command,
222 .check_status = ata_check_status,
223 .dev_select = ata_std_dev_select,
224 .bmdma_setup = ata_bmdma_setup,
225 .bmdma_start = ata_bmdma_start,
226 .bmdma_stop = ata_bmdma_stop,
227 .bmdma_status = ata_bmdma_status,
228 .qc_prep = ata_qc_prep,
229 .qc_issue = ata_qc_issue_prot,
230 .freeze = nv_ck804_freeze,
231 .thaw = nv_ck804_thaw,
232 .error_handler = nv_error_handler,
233 .post_internal_cmd = ata_bmdma_post_internal_cmd,
234 .data_xfer = ata_pio_data_xfer,
235 .irq_handler = nv_ck804_interrupt,
236 .irq_clear = ata_bmdma_irq_clear,
237 .scr_read = nv_scr_read,
238 .scr_write = nv_scr_write,
239 .port_start = ata_port_start,
240 .port_stop = ata_port_stop,
241 .host_stop = nv_ck804_host_stop,
242 };
243
244 static struct ata_port_info nv_port_info[] = {
245 /* generic */
246 {
247 .sht = &nv_sht,
248 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
249 .pio_mask = NV_PIO_MASK,
250 .mwdma_mask = NV_MWDMA_MASK,
251 .udma_mask = NV_UDMA_MASK,
252 .port_ops = &nv_generic_ops,
253 },
254 /* nforce2/3 */
255 {
256 .sht = &nv_sht,
257 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
258 .pio_mask = NV_PIO_MASK,
259 .mwdma_mask = NV_MWDMA_MASK,
260 .udma_mask = NV_UDMA_MASK,
261 .port_ops = &nv_nf2_ops,
262 },
263 /* ck804 */
264 {
265 .sht = &nv_sht,
266 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
267 .pio_mask = NV_PIO_MASK,
268 .mwdma_mask = NV_MWDMA_MASK,
269 .udma_mask = NV_UDMA_MASK,
270 .port_ops = &nv_ck804_ops,
271 },
272 };
273
274 MODULE_AUTHOR("NVIDIA");
275 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
276 MODULE_LICENSE("GPL");
277 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
278 MODULE_VERSION(DRV_VERSION);
279
280 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
281 {
282 struct ata_host *host = dev_instance;
283 unsigned int i;
284 unsigned int handled = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&host->lock, flags);
288
289 for (i = 0; i < host->n_ports; i++) {
290 struct ata_port *ap;
291
292 ap = host->ports[i];
293 if (ap &&
294 !(ap->flags & ATA_FLAG_DISABLED)) {
295 struct ata_queued_cmd *qc;
296
297 qc = ata_qc_from_tag(ap, ap->active_tag);
298 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
299 handled += ata_host_intr(ap, qc);
300 else
301 // No request pending? Clear interrupt status
302 // anyway, in case there's one pending.
303 ap->ops->check_status(ap);
304 }
305
306 }
307
308 spin_unlock_irqrestore(&host->lock, flags);
309
310 return IRQ_RETVAL(handled);
311 }
312
313 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
314 {
315 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
316 int handled;
317
318 /* freeze if hotplugged */
319 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
320 ata_port_freeze(ap);
321 return 1;
322 }
323
324 /* bail out if not our interrupt */
325 if (!(irq_stat & NV_INT_DEV))
326 return 0;
327
328 /* DEV interrupt w/ no active qc? */
329 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
330 ata_check_status(ap);
331 return 1;
332 }
333
334 /* handle interrupt */
335 handled = ata_host_intr(ap, qc);
336 if (unlikely(!handled)) {
337 /* spurious, clear it */
338 ata_check_status(ap);
339 }
340
341 return 1;
342 }
343
344 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
345 {
346 int i, handled = 0;
347
348 for (i = 0; i < host->n_ports; i++) {
349 struct ata_port *ap = host->ports[i];
350
351 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
352 handled += nv_host_intr(ap, irq_stat);
353
354 irq_stat >>= NV_INT_PORT_SHIFT;
355 }
356
357 return IRQ_RETVAL(handled);
358 }
359
360 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
361 {
362 struct ata_host *host = dev_instance;
363 u8 irq_stat;
364 irqreturn_t ret;
365
366 spin_lock(&host->lock);
367 irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
368 ret = nv_do_interrupt(host, irq_stat);
369 spin_unlock(&host->lock);
370
371 return ret;
372 }
373
374 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
375 {
376 struct ata_host *host = dev_instance;
377 u8 irq_stat;
378 irqreturn_t ret;
379
380 spin_lock(&host->lock);
381 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
382 ret = nv_do_interrupt(host, irq_stat);
383 spin_unlock(&host->lock);
384
385 return ret;
386 }
387
388 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
389 {
390 if (sc_reg > SCR_CONTROL)
391 return 0xffffffffU;
392
393 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
394 }
395
396 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
397 {
398 if (sc_reg > SCR_CONTROL)
399 return;
400
401 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
402 }
403
404 static void nv_nf2_freeze(struct ata_port *ap)
405 {
406 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
407 int shift = ap->port_no * NV_INT_PORT_SHIFT;
408 u8 mask;
409
410 mask = inb(scr_addr + NV_INT_ENABLE);
411 mask &= ~(NV_INT_ALL << shift);
412 outb(mask, scr_addr + NV_INT_ENABLE);
413 }
414
415 static void nv_nf2_thaw(struct ata_port *ap)
416 {
417 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
418 int shift = ap->port_no * NV_INT_PORT_SHIFT;
419 u8 mask;
420
421 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
422
423 mask = inb(scr_addr + NV_INT_ENABLE);
424 mask |= (NV_INT_MASK << shift);
425 outb(mask, scr_addr + NV_INT_ENABLE);
426 }
427
428 static void nv_ck804_freeze(struct ata_port *ap)
429 {
430 void __iomem *mmio_base = ap->host->mmio_base;
431 int shift = ap->port_no * NV_INT_PORT_SHIFT;
432 u8 mask;
433
434 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
435 mask &= ~(NV_INT_ALL << shift);
436 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
437 }
438
439 static void nv_ck804_thaw(struct ata_port *ap)
440 {
441 void __iomem *mmio_base = ap->host->mmio_base;
442 int shift = ap->port_no * NV_INT_PORT_SHIFT;
443 u8 mask;
444
445 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
446
447 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
448 mask |= (NV_INT_MASK << shift);
449 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
450 }
451
452 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
453 {
454 unsigned int dummy;
455
456 /* SATA hardreset fails to retrieve proper device signature on
457 * some controllers. Don't classify on hardreset. For more
458 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
459 */
460 return sata_std_hardreset(ap, &dummy);
461 }
462
463 static void nv_error_handler(struct ata_port *ap)
464 {
465 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
466 nv_hardreset, ata_std_postreset);
467 }
468
469 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
470 {
471 static int printed_version = 0;
472 struct ata_port_info *ppi[2];
473 struct ata_probe_ent *probe_ent;
474 int pci_dev_busy = 0;
475 int rc;
476 u32 bar;
477 unsigned long base;
478
479 // Make sure this is a SATA controller by counting the number of bars
480 // (NVIDIA SATA controllers will always have six bars). Otherwise,
481 // it's an IDE controller and we ignore it.
482 for (bar=0; bar<6; bar++)
483 if (pci_resource_start(pdev, bar) == 0)
484 return -ENODEV;
485
486 if (!printed_version++)
487 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
488
489 rc = pci_enable_device(pdev);
490 if (rc)
491 goto err_out;
492
493 rc = pci_request_regions(pdev, DRV_NAME);
494 if (rc) {
495 pci_dev_busy = 1;
496 goto err_out_disable;
497 }
498
499 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
500 if (rc)
501 goto err_out_regions;
502 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
503 if (rc)
504 goto err_out_regions;
505
506 rc = -ENOMEM;
507
508 ppi[0] = ppi[1] = &nv_port_info[ent->driver_data];
509 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
510 if (!probe_ent)
511 goto err_out_regions;
512
513 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
514 if (!probe_ent->mmio_base) {
515 rc = -EIO;
516 goto err_out_free_ent;
517 }
518
519 base = (unsigned long)probe_ent->mmio_base;
520
521 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
522 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
523
524 /* enable SATA space for CK804 */
525 if (ent->driver_data == CK804) {
526 u8 regval;
527
528 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
529 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
530 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
531 }
532
533 pci_set_master(pdev);
534
535 rc = ata_device_add(probe_ent);
536 if (rc != NV_PORTS)
537 goto err_out_iounmap;
538
539 kfree(probe_ent);
540
541 return 0;
542
543 err_out_iounmap:
544 pci_iounmap(pdev, probe_ent->mmio_base);
545 err_out_free_ent:
546 kfree(probe_ent);
547 err_out_regions:
548 pci_release_regions(pdev);
549 err_out_disable:
550 if (!pci_dev_busy)
551 pci_disable_device(pdev);
552 err_out:
553 return rc;
554 }
555
556 static void nv_ck804_host_stop(struct ata_host *host)
557 {
558 struct pci_dev *pdev = to_pci_dev(host->dev);
559 u8 regval;
560
561 /* disable SATA space for CK804 */
562 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
563 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
564 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
565
566 ata_pci_host_stop(host);
567 }
568
569 static int __init nv_init(void)
570 {
571 return pci_register_driver(&nv_pci_driver);
572 }
573
574 static void __exit nv_exit(void)
575 {
576 pci_unregister_driver(&nv_pci_driver);
577 }
578
579 module_init(nv_init);
580 module_exit(nv_exit);
linux kernel for loongson