Blackfin arch: update pm.c according to power management API change.
[linux-2.6/linux-loongson.git] / arch / blackfin / mach-common / irqpanic.c
blobf05e3dadaf335c0f28d8fe5c42ade7a514427f69
1 /*
2 * File: arch/blackfin/mach-common/irqpanic.c
3 * Based on:
4 * Author:
6 * Created: ?
7 * Description: panic kernel with dump information
9 * Modified: rgetz - added cache checking code 14Feb06
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/module.h>
31 #include <linux/kernel_stat.h>
32 #include <linux/sched.h>
33 #include <asm/traps.h>
34 #include <asm/blackfin.h>
36 #include "../oprofile/op_blackfin.h"
38 #ifdef CONFIG_DEBUG_ICACHE_CHECK
39 #define L1_ICACHE_START 0xffa10000
40 #define L1_ICACHE_END 0xffa13fff
41 void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text));
42 #endif
45 * irq_panic - calls panic with string setup
47 asmlinkage void irq_panic(int reason, struct pt_regs *regs)
49 int sig = 0;
50 siginfo_t info;
52 #ifdef CONFIG_DEBUG_ICACHE_CHECK
53 unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
54 unsigned short i, j, die;
55 unsigned int bad[10][6];
57 /* check entire cache for coherency
58 * Since printk is in cacheable memory,
59 * don't call it until you have checked everything
62 die = 0;
63 i = 0;
65 /* check icache */
67 for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
69 /* Grab various address bits for the itest_cmd fields */
70 cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
71 ((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
72 ((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
73 0); /* Access Tag, Read access */
75 SSYNC();
76 bfin_write_ITEST_COMMAND(cmd);
77 SSYNC();
78 tag = bfin_read_ITEST_DATA0();
79 SSYNC();
81 /* if tag is marked as valid, check it */
82 if (tag & 1) {
83 /* The icache is arranged in 4 groups of 64-bits */
84 for (j = 0; j < 32; j += 8) {
85 cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
86 (((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
87 (((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
88 4); /* Access Data, Read access */
90 SSYNC();
91 bfin_write_ITEST_COMMAND(cmd);
92 SSYNC();
94 cache_hi = bfin_read_ITEST_DATA1();
95 cache_lo = bfin_read_ITEST_DATA0();
97 pa = ((unsigned int *)((tag & 0xffffcc00) |
98 ((ca + j) & ~(0xffffcc00))));
101 * Debugging this, enable
103 * printk("addr: %08x %08x%08x | %08x%08x\n",
104 * ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
105 * cache_hi, cache_lo, *(pa+1), *pa);
108 if (cache_hi != *(pa + 1) || cache_lo != *pa) {
109 /* Since icache is not working, stay out of it, by not printing */
110 die = 1;
111 bad[i][0] = (ca + j);
112 bad[i][1] = cache_hi;
113 bad[i][2] = cache_lo;
114 bad[i][3] = ((tag & 0xffffcc00) |
115 ((ca + j) & ~(0xffffcc00)));
116 bad[i][4] = *(pa + 1);
117 bad[i][5] = *(pa);
118 i++;
123 if (die) {
124 printk(KERN_EMERG "icache coherency error\n");
125 for (j = 0; j <= i; j++) {
126 printk(KERN_EMERG
127 "cache address : %08x cache value : %08x%08x\n",
128 bad[j][0], bad[j][1], bad[j][2]);
129 printk(KERN_EMERG
130 "physical address: %08x SDRAM value : %08x%08x\n",
131 bad[j][3], bad[j][4], bad[j][5]);
133 panic("icache coherency error");
134 } else {
135 printk(KERN_EMERG "icache checked, and OK\n");
137 #endif
139 printk(KERN_EMERG "\n");
140 printk(KERN_EMERG "Exception: IRQ 0x%x entered\n", reason);
141 printk(KERN_EMERG " code=[0x%08lx], stack frame=0x%08lx, "
142 " bad PC=0x%08lx\n",
143 (unsigned long)regs->seqstat,
144 (unsigned long)regs,
145 (unsigned long)regs->pc);
146 if (reason == 0x5) {
147 printk(KERN_EMERG "----------- HARDWARE ERROR -----------\n");
149 /* There is only need to check for Hardware Errors, since other
150 * EXCEPTIONS are handled in TRAPS.c (MH)
152 switch (regs->seqstat & SEQSTAT_HWERRCAUSE) {
153 case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): /* System MMR Error */
154 info.si_code = BUS_ADRALN;
155 sig = SIGBUS;
156 printk(KERN_EMERG HWC_x2);
157 break;
158 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): /* External Memory Addressing Error */
159 info.si_code = BUS_ADRERR;
160 sig = SIGBUS;
161 printk(KERN_EMERG HWC_x3);
162 break;
163 case (SEQSTAT_HWERRCAUSE_PERF_FLOW): /* Performance Monitor Overflow */
164 printk(KERN_EMERG HWC_x12);
165 break;
166 case (SEQSTAT_HWERRCAUSE_RAISE_5): /* RAISE 5 instruction */
167 printk(KERN_EMERG HWC_x18);
168 break;
169 default: /* Reserved */
170 printk(KERN_EMERG HWC_default);
171 break;
175 regs->ipend = bfin_read_IPEND();
176 dump_bfin_regs(regs, (void *)regs->pc);
177 if (0 == (info.si_signo = sig) || 0 == user_mode(regs)) /* in kernelspace */
178 panic("Unhandled IRQ or exceptions!\n");
179 else { /* in userspace */
180 info.si_errno = 0;
181 info.si_addr = (void *)regs->pc;
182 force_sig_info(sig, &info, current);
186 #ifdef CONFIG_HARDWARE_PM
188 * call the handler of Performance overflow
190 asmlinkage void pm_overflow(int irq, struct pt_regs *regs)
192 pm_overflow_handler(irq, regs);
194 #endif