arch/mips/oprofile/op_model_mipsxx.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004, 05, 06 by Ralf Baechle
   7  * Copyright (C) 2005 by MIPS Technologies, Inc.
   8  */
   9 #include <linux/oprofile.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/smp.h>
  12 #include <asm/irq_regs.h>
  13
  14 #include "op_impl.h"
  15
  16 #define M_PERFCTL_EXL                   (1UL      <<  0)
  17 #define M_PERFCTL_KERNEL                (1UL      <<  1)
  18 #define M_PERFCTL_SUPERVISOR            (1UL      <<  2)
  19 #define M_PERFCTL_USER                  (1UL      <<  3)
  20 #define M_PERFCTL_INTERRUPT_ENABLE      (1UL      <<  4)
  21 #define M_PERFCTL_EVENT(event)          ((event)  << 5)
  22 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
  23 #define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
  24 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
  25 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
  26 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
  27 #define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
  28 #define M_PERFCTL_WIDE                  (1UL      << 30)
  29 #define M_PERFCTL_MORE                  (1UL      << 31)
  30
  31 #define M_COUNTER_OVERFLOW              (1UL      << 31)
  32
  33 #ifdef CONFIG_MIPS_MT_SMP
  34 #define WHAT    (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
  35 #else
  36 #define WHAT    0
  37 #endif
  38
  39 #define __define_perf_accessors(r, n, np)                               \
  40                                                                         \
  41 static inline unsigned int r_c0_ ## r ## n(void)                        \
  42 {                                                                       \
  43         unsigned int cpu = smp_processor_id();                          \
  44                                                                         \
  45         switch (cpu) {                                                  \
  46         case 0:                                                         \
  47                 return read_c0_ ## r ## n();                            \
  48         case 1:                                                         \
  49                 return read_c0_ ## r ## np();                           \
  50         default:                                                        \
  51                 BUG();                                                  \
  52         }                                                               \
  53         return 0;                                                       \
  54 }                                                                       \
  55                                                                         \
  56 static inline void w_c0_ ## r ## n(unsigned int value)                  \
  57 {                                                                       \
  58         unsigned int cpu = smp_processor_id();                          \
  59                                                                         \
  60         switch (cpu) {                                                  \
  61         case 0:                                                         \
  62                 write_c0_ ## r ## n(value);                             \
  63                 return;                                                 \
  64         case 1:                                                         \
  65                 write_c0_ ## r ## np(value);                            \
  66                 return;                                                 \
  67         default:                                                        \
  68                 BUG();                                                  \
  69         }                                                               \
  70         return;                                                         \
  71 }                                                                       \
  72
  73 __define_perf_accessors(perfcntr, 0, 2)
  74 __define_perf_accessors(perfcntr, 1, 3)
  75 __define_perf_accessors(perfcntr, 2, 2)
  76 __define_perf_accessors(perfcntr, 3, 2)
  77
  78 __define_perf_accessors(perfctrl, 0, 2)
  79 __define_perf_accessors(perfctrl, 1, 3)
  80 __define_perf_accessors(perfctrl, 2, 2)
  81 __define_perf_accessors(perfctrl, 3, 2)
  82
  83 struct op_mips_model op_model_mipsxx_ops;
  84
  85 static struct mipsxx_register_config {
  86         unsigned int control[4];
  87         unsigned int counter[4];
  88 } reg;
  89
  90 /* Compute all of the registers in preparation for enabling profiling.  */
  91
  92 static void mipsxx_reg_setup(struct op_counter_config *ctr)
  93 {
  94         unsigned int counters = op_model_mipsxx_ops.num_counters;
  95         int i;
  96
  97         /* Compute the performance counter control word.  */
  98         /* For now count kernel and user mode */
  99         for (i = 0; i < counters; i++) {
 100                 reg.control[i] = 0;
 101                 reg.counter[i] = 0;
 102
 103                 if (!ctr[i].enabled)
 104                         continue;
 105
 106                 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
 107                                  M_PERFCTL_INTERRUPT_ENABLE;
 108                 if (ctr[i].kernel)
 109                         reg.control[i] |= M_PERFCTL_KERNEL;
 110                 if (ctr[i].user)
 111                         reg.control[i] |= M_PERFCTL_USER;
 112                 if (ctr[i].exl)
 113                         reg.control[i] |= M_PERFCTL_EXL;
 114                 reg.counter[i] = 0x80000000 - ctr[i].count;
 115         }
 116 }
 117
 118 /* Program all of the registers in preparation for enabling profiling.  */
 119
 120 static void mipsxx_cpu_setup (void *args)
 121 {
 122         unsigned int counters = op_model_mipsxx_ops.num_counters;
 123
 124         switch (counters) {
 125         case 4:
 126                 w_c0_perfctrl3(0);
 127                 w_c0_perfcntr3(reg.counter[3]);
 128         case 3:
 129                 w_c0_perfctrl2(0);
 130                 w_c0_perfcntr2(reg.counter[2]);
 131         case 2:
 132                 w_c0_perfctrl1(0);
 133                 w_c0_perfcntr1(reg.counter[1]);
 134         case 1:
 135                 w_c0_perfctrl0(0);
 136                 w_c0_perfcntr0(reg.counter[0]);
 137         }
 138 }
 139
 140 /* Start all counters on current CPU */
 141 static void mipsxx_cpu_start(void *args)
 142 {
 143         unsigned int counters = op_model_mipsxx_ops.num_counters;
 144
 145         switch (counters) {
 146         case 4:
 147                 w_c0_perfctrl3(WHAT | reg.control[3]);
 148         case 3:
 149                 w_c0_perfctrl2(WHAT | reg.control[2]);
 150         case 2:
 151                 w_c0_perfctrl1(WHAT | reg.control[1]);
 152         case 1:
 153                 w_c0_perfctrl0(WHAT | reg.control[0]);
 154         }
 155 }
 156
 157 /* Stop all counters on current CPU */
 158 static void mipsxx_cpu_stop(void *args)
 159 {
 160         unsigned int counters = op_model_mipsxx_ops.num_counters;
 161
 162         switch (counters) {
 163         case 4:
 164                 w_c0_perfctrl3(0);
 165         case 3:
 166                 w_c0_perfctrl2(0);
 167         case 2:
 168                 w_c0_perfctrl1(0);
 169         case 1:
 170                 w_c0_perfctrl0(0);
 171         }
 172 }
 173
 174 static int mipsxx_perfcount_handler(void)
 175 {
 176         unsigned int counters = op_model_mipsxx_ops.num_counters;
 177         unsigned int control;
 178         unsigned int counter;
 179         int handled = 0;
 180
 181         switch (counters) {
 182 #define HANDLE_COUNTER(n)                                               \
 183         case n + 1:                                                     \
 184                 control = r_c0_perfctrl ## n();                         \
 185                 counter = r_c0_perfcntr ## n();                         \
 186                 if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&           \
 187                     (counter & M_COUNTER_OVERFLOW)) {                   \
 188                         oprofile_add_sample(get_irq_regs(), n);         \
 189                         w_c0_perfcntr ## n(reg.counter[n]);             \
 190                         handled = 1;                                    \
 191                 }
 192         HANDLE_COUNTER(3)
 193         HANDLE_COUNTER(2)
 194         HANDLE_COUNTER(1)
 195         HANDLE_COUNTER(0)
 196         }
 197
 198         return handled;
 199 }
 200
 201 #define M_CONFIG1_PC    (1 << 4)
 202
 203 static inline int __n_counters(void)
 204 {
 205         if (!(read_c0_config1() & M_CONFIG1_PC))
 206                 return 0;
 207         if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
 208                 return 1;
 209         if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
 210                 return 2;
 211         if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
 212                 return 3;
 213
 214         return 4;
 215 }
 216
 217 static inline int n_counters(void)
 218 {
 219         int counters = __n_counters();
 220
 221 #ifndef CONFIG_SMP
 222         if (current_cpu_data.cputype == CPU_34K)
 223                 return counters >> 1;
 224 #endif
 225
 226         return counters;
 227 }
 228
 229 static inline void reset_counters(int counters)
 230 {
 231         switch (counters) {
 232         case 4:
 233                 w_c0_perfctrl3(0);
 234                 w_c0_perfcntr3(0);
 235         case 3:
 236                 w_c0_perfctrl2(0);
 237                 w_c0_perfcntr2(0);
 238         case 2:
 239                 w_c0_perfctrl1(0);
 240                 w_c0_perfcntr1(0);
 241         case 1:
 242                 w_c0_perfctrl0(0);
 243                 w_c0_perfcntr0(0);
 244         }
 245 }
 246
 247 static int __init mipsxx_init(void)
 248 {
 249         int counters;
 250
 251         counters = n_counters();
 252         if (counters == 0) {
 253                 printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
 254                 return -ENODEV;
 255         }
 256
 257         reset_counters(counters);
 258
 259         op_model_mipsxx_ops.num_counters = counters;
 260         switch (current_cpu_data.cputype) {
 261         case CPU_20KC:
 262                 op_model_mipsxx_ops.cpu_type = "mips/20K";
 263                 break;
 264
 265         case CPU_24K:
 266                 op_model_mipsxx_ops.cpu_type = "mips/24K";
 267                 break;
 268
 269         case CPU_25KF:
 270                 op_model_mipsxx_ops.cpu_type = "mips/25K";
 271                 break;
 272
 273         case CPU_34K:
 274                 op_model_mipsxx_ops.cpu_type = "mips/34K";
 275                 break;
 276
 277         case CPU_74K:
 278                 op_model_mipsxx_ops.cpu_type = "mips/74K";
 279                 break;
 280
 281         case CPU_5KC:
 282                 op_model_mipsxx_ops.cpu_type = "mips/5K";
 283                 break;
 284
 285         case CPU_SB1:
 286         case CPU_SB1A:
 287                 op_model_mipsxx_ops.cpu_type = "mips/sb1";
 288                 break;
 289
 290         default:
 291                 printk(KERN_ERR "Profiling unsupported for this CPU\n");
 292
 293                 return -ENODEV;
 294         }
 295
 296         perf_irq = mipsxx_perfcount_handler;
 297
 298         return 0;
 299 }
 300
 301 static void mipsxx_exit(void)
 302 {
 303         reset_counters(op_model_mipsxx_ops.num_counters);
 304
 305         perf_irq = null_perf_irq;
 306 }
 307
 308 struct op_mips_model op_model_mipsxx_ops = {
 309         .reg_setup      = mipsxx_reg_setup,
 310         .cpu_setup      = mipsxx_cpu_setup,
 311         .init           = mipsxx_init,
 312         .exit           = mipsxx_exit,
 313         .cpu_start      = mipsxx_cpu_start,
 314         .cpu_stop       = mipsxx_cpu_stop,
 315 };