arch/mips/mips-boards/atlas/atlas_int.c

   1 /*
   2  * Copyright (C) 1999, 2000, 2006  MIPS Technologies, Inc.
   3  *      All rights reserved.
   4  *      Authors: Carsten Langgaard <carstenl@mips.com>
   5  *               Maciej W. Rozycki <macro@mips.com>
   6  *
   7  * ########################################################################
   8  *
   9  *  This program is free software; you can distribute it and/or modify it
  10  *  under the terms of the GNU General Public License (Version 2) as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, write to the Free Software Foundation, Inc.,
  20  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  21  *
  22  * ########################################################################
  23  *
  24  * Routines for generic manipulation of the interrupts found on the MIPS
  25  * Atlas board.
  26  *
  27  */
  28 #include <linux/compiler.h>
  29 #include <linux/init.h>
  30 #include <linux/irq.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kernel_stat.h>
  35
  36 #include <asm/gdb-stub.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_cpu.h>
  39 #include <asm/msc01_ic.h>
  40
  41 #include <asm/mips-boards/atlas.h>
  42 #include <asm/mips-boards/atlasint.h>
  43 #include <asm/mips-boards/generic.h>
  44
  45 static struct atlas_ictrl_regs *atlas_hw0_icregs;
  46
  47 #if 0
  48 #define DEBUG_INT(x...) printk(x)
  49 #else
  50 #define DEBUG_INT(x...)
  51 #endif
  52
  53 void disable_atlas_irq(unsigned int irq_nr)
  54 {
  55         atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
  56         iob();
  57 }
  58
  59 void enable_atlas_irq(unsigned int irq_nr)
  60 {
  61         atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
  62         iob();
  63 }
  64
  65 static unsigned int startup_atlas_irq(unsigned int irq)
  66 {
  67         enable_atlas_irq(irq);
  68         return 0; /* never anything pending */
  69 }
  70
  71 #define shutdown_atlas_irq      disable_atlas_irq
  72
  73 #define mask_and_ack_atlas_irq disable_atlas_irq
  74
  75 static void end_atlas_irq(unsigned int irq)
  76 {
  77         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  78                 enable_atlas_irq(irq);
  79 }
  80
  81 static struct irq_chip atlas_irq_type = {
  82         .typename = "Atlas",
  83         .startup = startup_atlas_irq,
  84         .shutdown = shutdown_atlas_irq,
  85         .enable = enable_atlas_irq,
  86         .disable = disable_atlas_irq,
  87         .ack = mask_and_ack_atlas_irq,
  88         .end = end_atlas_irq,
  89 };
  90
  91 static inline int ls1bit32(unsigned int x)
  92 {
  93         int b = 31, s;
  94
  95         s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
  96         s =  8; if (x <<  8 == 0) s = 0; b -= s; x <<= s;
  97         s =  4; if (x <<  4 == 0) s = 0; b -= s; x <<= s;
  98         s =  2; if (x <<  2 == 0) s = 0; b -= s; x <<= s;
  99         s =  1; if (x <<  1 == 0) s = 0; b -= s;
 100
 101         return b;
 102 }
 103
 104 static inline void atlas_hw0_irqdispatch(void)
 105 {
 106         unsigned long int_status;
 107         int irq;
 108
 109         int_status = atlas_hw0_icregs->intstatus;
 110
 111         /* if int_status == 0, then the interrupt has already been cleared */
 112         if (unlikely(int_status == 0))
 113                 return;
 114
 115         irq = ATLAS_INT_BASE + ls1bit32(int_status);
 116
 117         DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
 118
 119         do_IRQ(irq);
 120 }
 121
 122 static inline int clz(unsigned long x)
 123 {
 124         __asm__ (
 125         "       .set    push                                    \n"
 126         "       .set    mips32                                  \n"
 127         "       clz     %0, %1                                  \n"
 128         "       .set    pop                                     \n"
 129         : "=r" (x)
 130         : "r" (x));
 131
 132         return x;
 133 }
 134
 135 /*
 136  * Version of ffs that only looks at bits 12..15.
 137  */
 138 static inline unsigned int irq_ffs(unsigned int pending)
 139 {
 140 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 141         return -clz(pending) + 31 - CAUSEB_IP;
 142 #else
 143         unsigned int a0 = 7;
 144         unsigned int t0;
 145
 146         t0 = s0 & 0xf000;
 147         t0 = t0 < 1;
 148         t0 = t0 << 2;
 149         a0 = a0 - t0;
 150         s0 = s0 << t0;
 151
 152         t0 = s0 & 0xc000;
 153         t0 = t0 < 1;
 154         t0 = t0 << 1;
 155         a0 = a0 - t0;
 156         s0 = s0 << t0;
 157
 158         t0 = s0 & 0x8000;
 159         t0 = t0 < 1;
 160         //t0 = t0 << 2;
 161         a0 = a0 - t0;
 162         //s0 = s0 << t0;
 163
 164         return a0;
 165 #endif
 166 }
 167
 168 /*
 169  * IRQs on the Atlas board look basically like (all external interrupt
 170  * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
 171  *
 172  *      MIPS IRQ        Source
 173  *      --------        ------
 174  *             0        Software 0 (reschedule IPI on MT)
 175  *             1        Software 1 (remote call IPI on MT)
 176  *             2        Combined Atlas hardware interrupt (hw0)
 177  *             3        Hardware (ignored)
 178  *             4        Hardware (ignored)
 179  *             5        Hardware (ignored)
 180  *             6        Hardware (ignored)
 181  *             7        R4k timer (what we use)
 182  *
 183  * We handle the IRQ according to _our_ priority which is:
 184  *
 185  * Highest ----     R4k Timer
 186  * Lowest  ----     Software 0
 187  *
 188  * then we just return, if multiple IRQs are pending then we will just take
 189  * another exception, big deal.
 190  */
 191 asmlinkage void plat_irq_dispatch(void)
 192 {
 193         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 194         int irq;
 195
 196         irq = irq_ffs(pending);
 197
 198         if (irq == MIPSCPU_INT_ATLAS)
 199                 atlas_hw0_irqdispatch();
 200         else if (irq >= 0)
 201                 do_IRQ(MIPSCPU_INT_BASE + irq);
 202         else
 203                 spurious_interrupt();
 204 }
 205
 206 static inline void init_atlas_irqs (int base)
 207 {
 208         int i;
 209
 210         atlas_hw0_icregs = (struct atlas_ictrl_regs *)
 211                            ioremap(ATLAS_ICTRL_REGS_BASE,
 212                                    sizeof(struct atlas_ictrl_regs *));
 213
 214         /*
 215          * Mask out all interrupt by writing "1" to all bit position in
 216          * the interrupt reset reg.
 217          */
 218         atlas_hw0_icregs->intrsten = 0xffffffff;
 219
 220         for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) {
 221                 irq_desc[i].status      = IRQ_DISABLED;
 222                 irq_desc[i].action      = 0;
 223                 irq_desc[i].depth       = 1;
 224                 irq_desc[i].chip        = &atlas_irq_type;
 225                 spin_lock_init(&irq_desc[i].lock);
 226         }
 227 }
 228
 229 static struct irqaction atlasirq = {
 230         .handler = no_action,
 231         .name = "Atlas cascade"
 232 };
 233
 234 msc_irqmap_t __initdata msc_irqmap[] = {
 235         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 236         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 237 };
 238 int __initdata msc_nr_irqs = sizeof(msc_irqmap) / sizeof(*msc_irqmap);
 239
 240 msc_irqmap_t __initdata msc_eicirqmap[] = {
 241         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 242         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 243         {MSC01E_INT_ATLAS,              MSC01_IRQ_LEVEL, 0},
 244         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 245         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 246         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 247         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 248 };
 249 int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap) / sizeof(*msc_eicirqmap);
 250
 251 void __init arch_init_irq(void)
 252 {
 253         init_atlas_irqs(ATLAS_INT_BASE);
 254
 255         if (!cpu_has_veic)
 256                 mips_cpu_irq_init(MIPSCPU_INT_BASE);
 257
 258         switch(mips_revision_corid) {
 259         case MIPS_REVISION_CORID_CORE_MSC:
 260         case MIPS_REVISION_CORID_CORE_FPGA2:
 261         case MIPS_REVISION_CORID_CORE_FPGA3:
 262         case MIPS_REVISION_CORID_CORE_24K:
 263         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 264                 if (cpu_has_veic)
 265                         init_msc_irqs (MSC01E_INT_BASE,
 266                                        msc_eicirqmap, msc_nr_eicirqs);
 267                 else
 268                         init_msc_irqs (MSC01C_INT_BASE,
 269                                        msc_irqmap, msc_nr_irqs);
 270         }
 271
 272
 273         if (cpu_has_veic) {
 274                 set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
 275                 setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
 276         } else if (cpu_has_vint) {
 277                 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
 278 #ifdef CONFIG_MIPS_MT_SMTC
 279                 setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
 280                                 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
 281 #else /* Not SMTC */
 282                 setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
 283 #endif /* CONFIG_MIPS_MT_SMTC */
 284         } else
 285                 setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
 286 }