[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
[linux-2.6/linux-loongson.git] / arch / mips / gt64120 / ev64120 / irq.c
blobed4d82b9a24a95e43576c54979017380bfaf2448
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Code to handle irqs on GT64120A boards
4 * Derived from mips/orion and Cort <cort@fsmlabs.com>
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/errno.h>
31 #include <linux/init.h>
32 #include <linux/kernel_stat.h>
33 #include <linux/module.h>
34 #include <linux/signal.h>
35 #include <linux/sched.h>
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/timex.h>
40 #include <linux/slab.h>
41 #include <linux/random.h>
42 #include <linux/bitops.h>
43 #include <asm/bootinfo.h>
44 #include <asm/io.h>
45 #include <asm/mipsregs.h>
46 #include <asm/system.h>
47 #include <asm/gt64120.h>
49 asmlinkage void plat_irq_dispatch(void)
51 unsigned int pending = read_c0_status() & read_c0_cause();
53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
54 do_IRQ(4);
55 else if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(GT_INTA);
57 else if (pending & STATUSF_IP5) /* int3 hardware line */
58 do_IRQ(GT_INTD);
59 else if (pending & STATUSF_IP6) /* int4 hardware line */
60 do_IRQ(6);
61 else if (pending & STATUSF_IP7) /* compare int */
62 do_IRQ(7);
63 else
64 spurious_interrupt();
67 static void disable_ev64120_irq(unsigned int irq_nr)
69 unsigned long flags;
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10);
74 } else {
75 clear_c0_status(1 << (irq_nr + 8));
77 local_irq_restore(flags);
80 static void enable_ev64120_irq(unsigned int irq_nr)
82 unsigned long flags;
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10);
87 else
88 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
92 static unsigned int startup_ev64120_irq(unsigned int irq)
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
98 #define shutdown_ev64120_irq disable_ev64120_irq
99 #define mask_and_ack_ev64120_irq disable_ev64120_irq
101 static void end_ev64120_irq(unsigned int irq)
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
104 enable_ev64120_irq(irq);
107 static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120",
109 .startup = startup_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq,
111 .enable = enable_ev64120_irq,
112 .disable = disable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq,
115 .set_affinity = NULL
118 void gt64120_irq_setup(void)
121 * Clear all of the interrupts while we change the able around a bit.
123 clear_c0_status(ST0_IM);
125 local_irq_disable();
128 * Enable timer. Other interrupts will be enabled as they are
129 * registered.
131 set_c0_status(IE_IRQ2);
134 void __init arch_init_irq(void)
136 int i;
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
147 gt64120_irq_setup();