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[PATCH] misc NULL noise
[linux-2.6/linux-loongson.git] / drivers / ata / sata_promise.c
blob2339813ce9f646caf678172bbb85e045d157f2c7
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.00"
49
50
51 enum {
52 PDC_MMIO_BAR = 3,
53
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
75
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
81
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
86
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
90
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
93
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
98
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
100 ATA_FLAG_MMIO |
101 ATA_FLAG_PIO_POLLING,
102
103 /* hp->flags bits */
104 PDC_FLAG_GEN_II = (1 << 0),
105 };
106
107
108 struct pdc_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 };
112
113 struct pdc_host_priv {
114 unsigned long flags;
115 unsigned long port_flags[ATA_MAX_PORTS];
116 };
117
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static int pdc_port_start(struct ata_port *ap);
123 static void pdc_qc_prep(struct ata_queued_cmd *qc);
124 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
125 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
126 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
127 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
128 static void pdc_irq_clear(struct ata_port *ap);
129 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
130 static void pdc_freeze(struct ata_port *ap);
131 static void pdc_thaw(struct ata_port *ap);
132 static void pdc_error_handler(struct ata_port *ap);
133 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
134
135
136 static struct scsi_host_template pdc_ata_sht = {
137 .module = THIS_MODULE,
138 .name = DRV_NAME,
139 .ioctl = ata_scsi_ioctl,
140 .queuecommand = ata_scsi_queuecmd,
141 .can_queue = ATA_DEF_QUEUE,
142 .this_id = ATA_SHT_THIS_ID,
143 .sg_tablesize = LIBATA_MAX_PRD,
144 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
145 .emulated = ATA_SHT_EMULATED,
146 .use_clustering = ATA_SHT_USE_CLUSTERING,
147 .proc_name = DRV_NAME,
148 .dma_boundary = ATA_DMA_BOUNDARY,
149 .slave_configure = ata_scsi_slave_config,
150 .slave_destroy = ata_scsi_slave_destroy,
151 .bios_param = ata_std_bios_param,
152 };
153
154 static const struct ata_port_operations pdc_sata_ops = {
155 .port_disable = ata_port_disable,
156 .tf_load = pdc_tf_load_mmio,
157 .tf_read = ata_tf_read,
158 .check_status = ata_check_status,
159 .exec_command = pdc_exec_command_mmio,
160 .dev_select = ata_std_dev_select,
161 .check_atapi_dma = pdc_check_atapi_dma,
162
163 .qc_prep = pdc_qc_prep,
164 .qc_issue = pdc_qc_issue_prot,
165 .freeze = pdc_freeze,
166 .thaw = pdc_thaw,
167 .error_handler = pdc_error_handler,
168 .post_internal_cmd = pdc_post_internal_cmd,
169 .data_xfer = ata_data_xfer,
170 .irq_handler = pdc_interrupt,
171 .irq_clear = pdc_irq_clear,
172 .irq_on = ata_irq_on,
173 .irq_ack = ata_irq_ack,
174
175 .scr_read = pdc_sata_scr_read,
176 .scr_write = pdc_sata_scr_write,
177 .port_start = pdc_port_start,
178 };
179
180 /* First-generation chips need a more restrictive ->check_atapi_dma op */
181 static const struct ata_port_operations pdc_old_sata_ops = {
182 .port_disable = ata_port_disable,
183 .tf_load = pdc_tf_load_mmio,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = pdc_exec_command_mmio,
187 .dev_select = ata_std_dev_select,
188 .check_atapi_dma = pdc_old_check_atapi_dma,
189
190 .qc_prep = pdc_qc_prep,
191 .qc_issue = pdc_qc_issue_prot,
192 .freeze = pdc_freeze,
193 .thaw = pdc_thaw,
194 .error_handler = pdc_error_handler,
195 .post_internal_cmd = pdc_post_internal_cmd,
196 .data_xfer = ata_data_xfer,
197 .irq_handler = pdc_interrupt,
198 .irq_clear = pdc_irq_clear,
199 .irq_on = ata_irq_on,
200 .irq_ack = ata_irq_ack,
201
202 .scr_read = pdc_sata_scr_read,
203 .scr_write = pdc_sata_scr_write,
204 .port_start = pdc_port_start,
205 };
206
207 static const struct ata_port_operations pdc_pata_ops = {
208 .port_disable = ata_port_disable,
209 .tf_load = pdc_tf_load_mmio,
210 .tf_read = ata_tf_read,
211 .check_status = ata_check_status,
212 .exec_command = pdc_exec_command_mmio,
213 .dev_select = ata_std_dev_select,
214 .check_atapi_dma = pdc_check_atapi_dma,
215
216 .qc_prep = pdc_qc_prep,
217 .qc_issue = pdc_qc_issue_prot,
218 .freeze = pdc_freeze,
219 .thaw = pdc_thaw,
220 .error_handler = pdc_error_handler,
221 .post_internal_cmd = pdc_post_internal_cmd,
222 .data_xfer = ata_data_xfer,
223 .irq_handler = pdc_interrupt,
224 .irq_clear = pdc_irq_clear,
225 .irq_on = ata_irq_on,
226 .irq_ack = ata_irq_ack,
227
228 .port_start = pdc_port_start,
229 };
230
231 static const struct ata_port_info pdc_port_info[] = {
232 /* board_2037x */
233 {
234 .sht = &pdc_ata_sht,
235 .flags = PDC_COMMON_FLAGS,
236 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */
238 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
239 .port_ops = &pdc_old_sata_ops,
240 },
241
242 /* board_20319 */
243 {
244 .sht = &pdc_ata_sht,
245 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
246 .pio_mask = 0x1f, /* pio0-4 */
247 .mwdma_mask = 0x07, /* mwdma0-2 */
248 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
249 .port_ops = &pdc_old_sata_ops,
250 },
251
252 /* board_20619 */
253 {
254 .sht = &pdc_ata_sht,
255 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &pdc_pata_ops,
260 },
261
262 /* board_2057x */
263 {
264 .sht = &pdc_ata_sht,
265 .flags = PDC_COMMON_FLAGS,
266 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
269 .port_ops = &pdc_sata_ops,
270 },
271
272 /* board_40518 */
273 {
274 .sht = &pdc_ata_sht,
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
276 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
279 .port_ops = &pdc_sata_ops,
280 },
281 };
282
283 static const struct pci_device_id pdc_ata_pci_tbl[] = {
284 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
285 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
294
295 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
296 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
297 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
298 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
300 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
301
302 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
303
304 { } /* terminate list */
305 };
306
307
308 static struct pci_driver pdc_ata_pci_driver = {
309 .name = DRV_NAME,
310 .id_table = pdc_ata_pci_tbl,
311 .probe = pdc_ata_init_one,
312 .remove = ata_pci_remove_one,
313 };
314
315
316 static int pdc_port_start(struct ata_port *ap)
317 {
318 struct device *dev = ap->host->dev;
319 struct pdc_host_priv *hp = ap->host->private_data;
320 struct pdc_port_priv *pp;
321 int rc;
322
323 /* fix up port flags and cable type for SATA+PATA chips */
324 ap->flags |= hp->port_flags[ap->port_no];
325 if (ap->flags & ATA_FLAG_SATA)
326 ap->cbl = ATA_CBL_SATA;
327
328 rc = ata_port_start(ap);
329 if (rc)
330 return rc;
331
332 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
333 if (!pp)
334 return -ENOMEM;
335
336 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
337 if (!pp->pkt)
338 return -ENOMEM;
339
340 ap->private_data = pp;
341
342 /* fix up PHYMODE4 align timing */
343 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
344 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
345 unsigned int tmp;
346
347 tmp = readl(mmio + 0x014);
348 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
349 writel(tmp, mmio + 0x014);
350 }
351
352 return 0;
353 }
354
355 static void pdc_reset_port(struct ata_port *ap)
356 {
357 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
358 unsigned int i;
359 u32 tmp;
360
361 for (i = 11; i > 0; i--) {
362 tmp = readl(mmio);
363 if (tmp & PDC_RESET)
364 break;
365
366 udelay(100);
367
368 tmp |= PDC_RESET;
369 writel(tmp, mmio);
370 }
371
372 tmp &= ~PDC_RESET;
373 writel(tmp, mmio);
374 readl(mmio); /* flush */
375 }
376
377 static void pdc_pata_cbl_detect(struct ata_port *ap)
378 {
379 u8 tmp;
380 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
381
382 tmp = readb(mmio);
383
384 if (tmp & 0x01) {
385 ap->cbl = ATA_CBL_PATA40;
386 ap->udma_mask &= ATA_UDMA_MASK_40C;
387 } else
388 ap->cbl = ATA_CBL_PATA80;
389 }
390
391 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
392 {
393 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
394 return 0xffffffffU;
395 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
396 }
397
398
399 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
400 u32 val)
401 {
402 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
403 return;
404 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
405 }
406
407 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
408 {
409 struct ata_port *ap = qc->ap;
410 dma_addr_t sg_table = ap->prd_dma;
411 unsigned int cdb_len = qc->dev->cdb_len;
412 u8 *cdb = qc->cdb;
413 struct pdc_port_priv *pp = ap->private_data;
414 u8 *buf = pp->pkt;
415 u32 *buf32 = (u32 *) buf;
416 unsigned int dev_sel, feature, nbytes;
417
418 /* set control bits (byte 0), zero delay seq id (byte 3),
419 * and seq id (byte 2)
420 */
421 switch (qc->tf.protocol) {
422 case ATA_PROT_ATAPI_DMA:
423 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
424 buf32[0] = cpu_to_le32(PDC_PKT_READ);
425 else
426 buf32[0] = 0;
427 break;
428 case ATA_PROT_ATAPI_NODATA:
429 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
430 break;
431 default:
432 BUG();
433 break;
434 }
435 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
436 buf32[2] = 0; /* no next-packet */
437
438 /* select drive */
439 if (sata_scr_valid(ap)) {
440 dev_sel = PDC_DEVICE_SATA;
441 } else {
442 dev_sel = ATA_DEVICE_OBS;
443 if (qc->dev->devno != 0)
444 dev_sel |= ATA_DEV1;
445 }
446 buf[12] = (1 << 5) | ATA_REG_DEVICE;
447 buf[13] = dev_sel;
448 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
449 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
450
451 buf[16] = (1 << 5) | ATA_REG_NSECT;
452 buf[17] = 0x00;
453 buf[18] = (1 << 5) | ATA_REG_LBAL;
454 buf[19] = 0x00;
455
456 /* set feature and byte counter registers */
457 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
458 feature = PDC_FEATURE_ATAPI_PIO;
459 /* set byte counter register to real transfer byte count */
460 nbytes = qc->nbytes;
461 if (nbytes > 0xffff)
462 nbytes = 0xffff;
463 } else {
464 feature = PDC_FEATURE_ATAPI_DMA;
465 /* set byte counter register to 0 */
466 nbytes = 0;
467 }
468 buf[20] = (1 << 5) | ATA_REG_FEATURE;
469 buf[21] = feature;
470 buf[22] = (1 << 5) | ATA_REG_BYTEL;
471 buf[23] = nbytes & 0xFF;
472 buf[24] = (1 << 5) | ATA_REG_BYTEH;
473 buf[25] = (nbytes >> 8) & 0xFF;
474
475 /* send ATAPI packet command 0xA0 */
476 buf[26] = (1 << 5) | ATA_REG_CMD;
477 buf[27] = ATA_CMD_PACKET;
478
479 /* select drive and check DRQ */
480 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
481 buf[29] = dev_sel;
482
483 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
484 BUG_ON(cdb_len & ~0x1E);
485
486 /* append the CDB as the final part */
487 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
488 memcpy(buf+31, cdb, cdb_len);
489 }
490
491 static void pdc_qc_prep(struct ata_queued_cmd *qc)
492 {
493 struct pdc_port_priv *pp = qc->ap->private_data;
494 unsigned int i;
495
496 VPRINTK("ENTER\n");
497
498 switch (qc->tf.protocol) {
499 case ATA_PROT_DMA:
500 ata_qc_prep(qc);
501 /* fall through */
502
503 case ATA_PROT_NODATA:
504 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
505 qc->dev->devno, pp->pkt);
506
507 if (qc->tf.flags & ATA_TFLAG_LBA48)
508 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
509 else
510 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
511
512 pdc_pkt_footer(&qc->tf, pp->pkt, i);
513 break;
514
515 case ATA_PROT_ATAPI:
516 ata_qc_prep(qc);
517 break;
518
519 case ATA_PROT_ATAPI_DMA:
520 ata_qc_prep(qc);
521 /*FALLTHROUGH*/
522 case ATA_PROT_ATAPI_NODATA:
523 pdc_atapi_pkt(qc);
524 break;
525
526 default:
527 break;
528 }
529 }
530
531 static void pdc_freeze(struct ata_port *ap)
532 {
533 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
534 u32 tmp;
535
536 tmp = readl(mmio + PDC_CTLSTAT);
537 tmp |= PDC_IRQ_DISABLE;
538 tmp &= ~PDC_DMA_ENABLE;
539 writel(tmp, mmio + PDC_CTLSTAT);
540 readl(mmio + PDC_CTLSTAT); /* flush */
541 }
542
543 static void pdc_thaw(struct ata_port *ap)
544 {
545 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
546 u32 tmp;
547
548 /* clear IRQ */
549 readl(mmio + PDC_INT_SEQMASK);
550
551 /* turn IRQ back on */
552 tmp = readl(mmio + PDC_CTLSTAT);
553 tmp &= ~PDC_IRQ_DISABLE;
554 writel(tmp, mmio + PDC_CTLSTAT);
555 readl(mmio + PDC_CTLSTAT); /* flush */
556 }
557
558 static int pdc_pre_reset(struct ata_port *ap)
559 {
560 if (!sata_scr_valid(ap))
561 pdc_pata_cbl_detect(ap);
562 return ata_std_prereset(ap);
563 }
564
565 static void pdc_error_handler(struct ata_port *ap)
566 {
567 ata_reset_fn_t hardreset;
568
569 if (!(ap->pflags & ATA_PFLAG_FROZEN))
570 pdc_reset_port(ap);
571
572 hardreset = NULL;
573 if (sata_scr_valid(ap))
574 hardreset = sata_std_hardreset;
575
576 /* perform recovery */
577 ata_do_eh(ap, pdc_pre_reset, ata_std_softreset, hardreset,
578 ata_std_postreset);
579 }
580
581 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
582 {
583 struct ata_port *ap = qc->ap;
584
585 if (qc->flags & ATA_QCFLAG_FAILED)
586 qc->err_mask |= AC_ERR_OTHER;
587
588 /* make DMA engine forget about the failed command */
589 if (qc->err_mask)
590 pdc_reset_port(ap);
591 }
592
593 static inline unsigned int pdc_host_intr( struct ata_port *ap,
594 struct ata_queued_cmd *qc)
595 {
596 unsigned int handled = 0;
597 u32 tmp;
598 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
599
600 tmp = readl(mmio);
601 if (tmp & PDC_ERR_MASK) {
602 qc->err_mask |= AC_ERR_DEV;
603 pdc_reset_port(ap);
604 }
605
606 switch (qc->tf.protocol) {
607 case ATA_PROT_DMA:
608 case ATA_PROT_NODATA:
609 case ATA_PROT_ATAPI_DMA:
610 case ATA_PROT_ATAPI_NODATA:
611 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
612 ata_qc_complete(qc);
613 handled = 1;
614 break;
615
616 default:
617 ap->stats.idle_irq++;
618 break;
619 }
620
621 return handled;
622 }
623
624 static void pdc_irq_clear(struct ata_port *ap)
625 {
626 struct ata_host *host = ap->host;
627 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
628
629 readl(mmio + PDC_INT_SEQMASK);
630 }
631
632 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
633 {
634 struct ata_host *host = dev_instance;
635 struct ata_port *ap;
636 u32 mask = 0;
637 unsigned int i, tmp;
638 unsigned int handled = 0;
639 void __iomem *mmio_base;
640
641 VPRINTK("ENTER\n");
642
643 if (!host || !host->iomap[PDC_MMIO_BAR]) {
644 VPRINTK("QUICK EXIT\n");
645 return IRQ_NONE;
646 }
647
648 mmio_base = host->iomap[PDC_MMIO_BAR];
649
650 /* reading should also clear interrupts */
651 mask = readl(mmio_base + PDC_INT_SEQMASK);
652
653 if (mask == 0xffffffff) {
654 VPRINTK("QUICK EXIT 2\n");
655 return IRQ_NONE;
656 }
657
658 spin_lock(&host->lock);
659
660 mask &= 0xffff; /* only 16 tags possible */
661 if (!mask) {
662 VPRINTK("QUICK EXIT 3\n");
663 goto done_irq;
664 }
665
666 writel(mask, mmio_base + PDC_INT_SEQMASK);
667
668 for (i = 0; i < host->n_ports; i++) {
669 VPRINTK("port %u\n", i);
670 ap = host->ports[i];
671 tmp = mask & (1 << (i + 1));
672 if (tmp && ap &&
673 !(ap->flags & ATA_FLAG_DISABLED)) {
674 struct ata_queued_cmd *qc;
675
676 qc = ata_qc_from_tag(ap, ap->active_tag);
677 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
678 handled += pdc_host_intr(ap, qc);
679 }
680 }
681
682 VPRINTK("EXIT\n");
683
684 done_irq:
685 spin_unlock(&host->lock);
686 return IRQ_RETVAL(handled);
687 }
688
689 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
690 {
691 struct ata_port *ap = qc->ap;
692 struct pdc_port_priv *pp = ap->private_data;
693 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
694 unsigned int port_no = ap->port_no;
695 u8 seq = (u8) (port_no + 1);
696
697 VPRINTK("ENTER, ap %p\n", ap);
698
699 writel(0x00000001, mmio + (seq * 4));
700 readl(mmio + (seq * 4)); /* flush */
701
702 pp->pkt[2] = seq;
703 wmb(); /* flush PRD, pkt writes */
704 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
705 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
706 }
707
708 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
709 {
710 switch (qc->tf.protocol) {
711 case ATA_PROT_ATAPI_NODATA:
712 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
713 break;
714 /*FALLTHROUGH*/
715 case ATA_PROT_ATAPI_DMA:
716 case ATA_PROT_DMA:
717 case ATA_PROT_NODATA:
718 pdc_packet_start(qc);
719 return 0;
720
721 default:
722 break;
723 }
724
725 return ata_qc_issue_prot(qc);
726 }
727
728 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
729 {
730 WARN_ON (tf->protocol == ATA_PROT_DMA ||
731 tf->protocol == ATA_PROT_NODATA);
732 ata_tf_load(ap, tf);
733 }
734
735
736 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
737 {
738 WARN_ON (tf->protocol == ATA_PROT_DMA ||
739 tf->protocol == ATA_PROT_NODATA);
740 ata_exec_command(ap, tf);
741 }
742
743 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
744 {
745 u8 *scsicmd = qc->scsicmd->cmnd;
746 int pio = 1; /* atapi dma off by default */
747
748 /* Whitelist commands that may use DMA. */
749 switch (scsicmd[0]) {
750 case WRITE_12:
751 case WRITE_10:
752 case WRITE_6:
753 case READ_12:
754 case READ_10:
755 case READ_6:
756 case 0xad: /* READ_DVD_STRUCTURE */
757 case 0xbe: /* READ_CD */
758 pio = 0;
759 }
760 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
761 if (scsicmd[0] == WRITE_10) {
762 unsigned int lba;
763 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
764 if (lba >= 0xFFFF4FA2)
765 pio = 1;
766 }
767 return pio;
768 }
769
770 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
771 {
772 struct ata_port *ap = qc->ap;
773
774 /* First generation chips cannot use ATAPI DMA on SATA ports */
775 if (sata_scr_valid(ap))
776 return 1;
777 return pdc_check_atapi_dma(qc);
778 }
779
780 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
781 void __iomem *scr_addr)
782 {
783 port->cmd_addr = base;
784 port->data_addr = base;
785 port->feature_addr =
786 port->error_addr = base + 0x4;
787 port->nsect_addr = base + 0x8;
788 port->lbal_addr = base + 0xc;
789 port->lbam_addr = base + 0x10;
790 port->lbah_addr = base + 0x14;
791 port->device_addr = base + 0x18;
792 port->command_addr =
793 port->status_addr = base + 0x1c;
794 port->altstatus_addr =
795 port->ctl_addr = base + 0x38;
796 port->scr_addr = scr_addr;
797 }
798
799
800 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
801 {
802 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
803 struct pdc_host_priv *hp = pe->private_data;
804 int hotplug_offset;
805 u32 tmp;
806
807 if (hp->flags & PDC_FLAG_GEN_II)
808 hotplug_offset = PDC2_SATA_PLUG_CSR;
809 else
810 hotplug_offset = PDC_SATA_PLUG_CSR;
811
812 /*
813 * Except for the hotplug stuff, this is voodoo from the
814 * Promise driver. Label this entire section
815 * "TODO: figure out why we do this"
816 */
817
818 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
819 tmp = readl(mmio + PDC_FLASH_CTL);
820 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
821 if (!(hp->flags & PDC_FLAG_GEN_II))
822 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
823 writel(tmp, mmio + PDC_FLASH_CTL);
824
825 /* clear plug/unplug flags for all ports */
826 tmp = readl(mmio + hotplug_offset);
827 writel(tmp | 0xff, mmio + hotplug_offset);
828
829 /* mask plug/unplug ints */
830 tmp = readl(mmio + hotplug_offset);
831 writel(tmp | 0xff0000, mmio + hotplug_offset);
832
833 /* don't initialise TBG or SLEW on 2nd generation chips */
834 if (hp->flags & PDC_FLAG_GEN_II)
835 return;
836
837 /* reduce TBG clock to 133 Mhz. */
838 tmp = readl(mmio + PDC_TBG_MODE);
839 tmp &= ~0x30000; /* clear bit 17, 16*/
840 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
841 writel(tmp, mmio + PDC_TBG_MODE);
842
843 readl(mmio + PDC_TBG_MODE); /* flush */
844 msleep(10);
845
846 /* adjust slew rate control register. */
847 tmp = readl(mmio + PDC_SLEW_CTL);
848 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
849 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
850 writel(tmp, mmio + PDC_SLEW_CTL);
851 }
852
853 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
854 {
855 static int printed_version;
856 struct ata_probe_ent *probe_ent;
857 struct pdc_host_priv *hp;
858 void __iomem *base;
859 unsigned int board_idx = (unsigned int) ent->driver_data;
860 int rc;
861 u8 tmp;
862
863 if (!printed_version++)
864 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
865
866 rc = pcim_enable_device(pdev);
867 if (rc)
868 return rc;
869
870 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
871 if (rc == -EBUSY)
872 pcim_pin_device(pdev);
873 if (rc)
874 return rc;
875
876 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
877 if (rc)
878 return rc;
879 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
880 if (rc)
881 return rc;
882
883 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
884 if (probe_ent == NULL)
885 return -ENOMEM;
886
887 probe_ent->dev = pci_dev_to_dev(pdev);
888 INIT_LIST_HEAD(&probe_ent->node);
889
890 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
891 if (hp == NULL)
892 return -ENOMEM;
893
894 probe_ent->private_data = hp;
895
896 probe_ent->sht = pdc_port_info[board_idx].sht;
897 probe_ent->port_flags = pdc_port_info[board_idx].flags;
898 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
899 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
900 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
901 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
902
903 probe_ent->irq = pdev->irq;
904 probe_ent->irq_flags = IRQF_SHARED;
905 probe_ent->iomap = pcim_iomap_table(pdev);
906
907 base = probe_ent->iomap[PDC_MMIO_BAR];
908
909 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
910 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
911
912 /* notice 4-port boards */
913 switch (board_idx) {
914 case board_40518:
915 hp->flags |= PDC_FLAG_GEN_II;
916 /* Fall through */
917 case board_20319:
918 probe_ent->n_ports = 4;
919 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
920 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
921 break;
922 case board_2057x:
923 hp->flags |= PDC_FLAG_GEN_II;
924 /* Fall through */
925 case board_2037x:
926 /* TX2plus boards also have a PATA port */
927 tmp = readb(base + PDC_FLASH_CTL+1);
928 if (!(tmp & 0x80)) {
929 probe_ent->n_ports = 3;
930 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
931 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
932 printk(KERN_INFO DRV_NAME " PATA port found\n");
933 } else
934 probe_ent->n_ports = 2;
935 hp->port_flags[0] = ATA_FLAG_SATA;
936 hp->port_flags[1] = ATA_FLAG_SATA;
937 break;
938 case board_20619:
939 probe_ent->n_ports = 4;
940 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
941 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
942 break;
943 default:
944 BUG();
945 break;
946 }
947
948 pci_set_master(pdev);
949
950 /* initialize adapter */
951 pdc_host_init(board_idx, probe_ent);
952
953 if (!ata_device_add(probe_ent))
954 return -ENODEV;
955
956 devm_kfree(&pdev->dev, probe_ent);
957 return 0;
958 }
959
960
961 static int __init pdc_ata_init(void)
962 {
963 return pci_register_driver(&pdc_ata_pci_driver);
964 }
965
966
967 static void __exit pdc_ata_exit(void)
968 {
969 pci_unregister_driver(&pdc_ata_pci_driver);
970 }
971
972
973 MODULE_AUTHOR("Jeff Garzik");
974 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
975 MODULE_LICENSE("GPL");
976 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
977 MODULE_VERSION(DRV_VERSION);
978
979 module_init(pdc_ata_init);
980 module_exit(pdc_ata_exit);
linux kernel for loongson