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[POWERPC] Fix debug printks for 32-bit resources in the PCI code
[linux-2.6/linux-loongson.git] / arch / powerpc / kernel / pci_32.c
blob2f54cd81dea571ce82468d82361ae0a67e397f3e
1 /*
2 * Common pmac/prep/chrp pci routines. -- Cort
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/pci.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
16
17 #include <asm/processor.h>
18 #include <asm/io.h>
19 #include <asm/prom.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
25
26 #undef DEBUG
27
28 #ifdef DEBUG
29 #define DBG(x...) printk(x)
30 #else
31 #define DBG(x...)
32 #endif
33
34 unsigned long isa_io_base = 0;
35 unsigned long isa_mem_base = 0;
36 unsigned long pci_dram_offset = 0;
37 int pcibios_assign_bus_offset = 1;
38
39 void pcibios_make_OF_bus_map(void);
40
41 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
42 static int probe_resource(struct pci_bus *parent, struct resource *pr,
43 struct resource *res, struct resource **conflict);
44 static void update_bridge_base(struct pci_bus *bus, int i);
45 static void pcibios_fixup_resources(struct pci_dev* dev);
46 static void fixup_broken_pcnet32(struct pci_dev* dev);
47 static int reparent_resources(struct resource *parent, struct resource *res);
48 static void fixup_cpc710_pci64(struct pci_dev* dev);
49 #ifdef CONFIG_PPC_OF
50 static u8* pci_to_OF_bus_map;
51 #endif
52
53 /* By default, we don't re-assign bus numbers. We do this only on
54 * some pmacs
55 */
56 int pci_assign_all_buses;
57
58 struct pci_controller* hose_head;
59 struct pci_controller** hose_tail = &hose_head;
60
61 static int pci_bus_count;
62
63 static void
64 fixup_broken_pcnet32(struct pci_dev* dev)
65 {
66 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
67 dev->vendor = PCI_VENDOR_ID_AMD;
68 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
69 }
70 }
71 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
72
73 static void
74 fixup_cpc710_pci64(struct pci_dev* dev)
75 {
76 /* Hide the PCI64 BARs from the kernel as their content doesn't
77 * fit well in the resource management
78 */
79 dev->resource[0].start = dev->resource[0].end = 0;
80 dev->resource[0].flags = 0;
81 dev->resource[1].start = dev->resource[1].end = 0;
82 dev->resource[1].flags = 0;
83 }
84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
85
86 static void
87 pcibios_fixup_resources(struct pci_dev *dev)
88 {
89 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
90 int i;
91 unsigned long offset;
92
93 if (!hose) {
94 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
95 return;
96 }
97 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
98 struct resource *res = dev->resource + i;
99 if (!res->flags)
100 continue;
101 if (res->end == 0xffffffff) {
102 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
103 pci_name(dev), i, (u64)res->start, (u64)res->end);
104 res->end -= res->start;
105 res->start = 0;
106 res->flags |= IORESOURCE_UNSET;
107 continue;
108 }
109 offset = 0;
110 if (res->flags & IORESOURCE_MEM) {
111 offset = hose->pci_mem_offset;
112 } else if (res->flags & IORESOURCE_IO) {
113 offset = (unsigned long) hose->io_base_virt
114 - isa_io_base;
115 }
116 if (offset != 0) {
117 res->start += offset;
118 res->end += offset;
119 DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
120 i, res->flags, pci_name(dev),
121 (u64)res->start - offset, (u64)res->start);
122 }
123 }
124
125 /* Call machine specific resource fixup */
126 if (ppc_md.pcibios_fixup_resources)
127 ppc_md.pcibios_fixup_resources(dev);
128 }
129 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
130
131 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
132 struct resource *res)
133 {
134 unsigned long offset = 0;
135 struct pci_controller *hose = dev->sysdata;
136
137 if (hose && res->flags & IORESOURCE_IO)
138 offset = (unsigned long)hose->io_base_virt - isa_io_base;
139 else if (hose && res->flags & IORESOURCE_MEM)
140 offset = hose->pci_mem_offset;
141 region->start = res->start - offset;
142 region->end = res->end - offset;
143 }
144 EXPORT_SYMBOL(pcibios_resource_to_bus);
145
146 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
147 struct pci_bus_region *region)
148 {
149 unsigned long offset = 0;
150 struct pci_controller *hose = dev->sysdata;
151
152 if (hose && res->flags & IORESOURCE_IO)
153 offset = (unsigned long)hose->io_base_virt - isa_io_base;
154 else if (hose && res->flags & IORESOURCE_MEM)
155 offset = hose->pci_mem_offset;
156 res->start = region->start + offset;
157 res->end = region->end + offset;
158 }
159 EXPORT_SYMBOL(pcibios_bus_to_resource);
160
161 /*
162 * We need to avoid collisions with `mirrored' VGA ports
163 * and other strange ISA hardware, so we always want the
164 * addresses to be allocated in the 0x000-0x0ff region
165 * modulo 0x400.
166 *
167 * Why? Because some silly external IO cards only decode
168 * the low 10 bits of the IO address. The 0x00-0xff region
169 * is reserved for motherboard devices that decode all 16
170 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
171 * but we want to try to avoid allocating at 0x2900-0x2bff
172 * which might have be mirrored at 0x0100-0x03ff..
173 */
174 void pcibios_align_resource(void *data, struct resource *res,
175 resource_size_t size, resource_size_t align)
176 {
177 struct pci_dev *dev = data;
178
179 if (res->flags & IORESOURCE_IO) {
180 resource_size_t start = res->start;
181
182 if (size > 0x100) {
183 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
184 " (%lld bytes)\n", pci_name(dev),
185 dev->resource - res, (unsigned long long)size);
186 }
187
188 if (start & 0x300) {
189 start = (start + 0x3ff) & ~0x3ff;
190 res->start = start;
191 }
192 }
193 }
194 EXPORT_SYMBOL(pcibios_align_resource);
195
196 /*
197 * Handle resources of PCI devices. If the world were perfect, we could
198 * just allocate all the resource regions and do nothing more. It isn't.
199 * On the other hand, we cannot just re-allocate all devices, as it would
200 * require us to know lots of host bridge internals. So we attempt to
201 * keep as much of the original configuration as possible, but tweak it
202 * when it's found to be wrong.
203 *
204 * Known BIOS problems we have to work around:
205 * - I/O or memory regions not configured
206 * - regions configured, but not enabled in the command register
207 * - bogus I/O addresses above 64K used
208 * - expansion ROMs left enabled (this may sound harmless, but given
209 * the fact the PCI specs explicitly allow address decoders to be
210 * shared between expansion ROMs and other resource regions, it's
211 * at least dangerous)
212 *
213 * Our solution:
214 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
215 * This gives us fixed barriers on where we can allocate.
216 * (2) Allocate resources for all enabled devices. If there is
217 * a collision, just mark the resource as unallocated. Also
218 * disable expansion ROMs during this step.
219 * (3) Try to allocate resources for disabled devices. If the
220 * resources were assigned correctly, everything goes well,
221 * if they weren't, they won't disturb allocation of other
222 * resources.
223 * (4) Assign new addresses to resources which were either
224 * not configured at all or misconfigured. If explicitly
225 * requested by the user, configure expansion ROM address
226 * as well.
227 */
228
229 static void __init
230 pcibios_allocate_bus_resources(struct list_head *bus_list)
231 {
232 struct pci_bus *bus;
233 int i;
234 struct resource *res, *pr;
235
236 /* Depth-First Search on bus tree */
237 list_for_each_entry(bus, bus_list, node) {
238 for (i = 0; i < 4; ++i) {
239 if ((res = bus->resource[i]) == NULL || !res->flags
240 || res->start > res->end)
241 continue;
242 if (bus->parent == NULL)
243 pr = (res->flags & IORESOURCE_IO)?
244 &ioport_resource: &iomem_resource;
245 else {
246 pr = pci_find_parent_resource(bus->self, res);
247 if (pr == res) {
248 /* this happens when the generic PCI
249 * code (wrongly) decides that this
250 * bridge is transparent -- paulus
251 */
252 continue;
253 }
254 }
255
256 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
257 (u64)res->start, (u64)res->end, res->flags, pr);
258 if (pr) {
259 if (request_resource(pr, res) == 0)
260 continue;
261 /*
262 * Must be a conflict with an existing entry.
263 * Move that entry (or entries) under the
264 * bridge resource and try again.
265 */
266 if (reparent_resources(pr, res) == 0)
267 continue;
268 }
269 printk(KERN_ERR "PCI: Cannot allocate resource region "
270 "%d of PCI bridge %d\n", i, bus->number);
271 if (pci_relocate_bridge_resource(bus, i))
272 bus->resource[i] = NULL;
273 }
274 pcibios_allocate_bus_resources(&bus->children);
275 }
276 }
277
278 /*
279 * Reparent resource children of pr that conflict with res
280 * under res, and make res replace those children.
281 */
282 static int __init
283 reparent_resources(struct resource *parent, struct resource *res)
284 {
285 struct resource *p, **pp;
286 struct resource **firstpp = NULL;
287
288 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
289 if (p->end < res->start)
290 continue;
291 if (res->end < p->start)
292 break;
293 if (p->start < res->start || p->end > res->end)
294 return -1; /* not completely contained */
295 if (firstpp == NULL)
296 firstpp = pp;
297 }
298 if (firstpp == NULL)
299 return -1; /* didn't find any conflicting entries? */
300 res->parent = parent;
301 res->child = *firstpp;
302 res->sibling = *pp;
303 *firstpp = res;
304 *pp = NULL;
305 for (p = res->child; p != NULL; p = p->sibling) {
306 p->parent = res;
307 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
308 p->name, (u64)p->start, (u64)p->end, res->name);
309 }
310 return 0;
311 }
312
313 /*
314 * A bridge has been allocated a range which is outside the range
315 * of its parent bridge, so it needs to be moved.
316 */
317 static int __init
318 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
319 {
320 struct resource *res, *pr, *conflict;
321 unsigned long try, size;
322 int j;
323 struct pci_bus *parent = bus->parent;
324
325 if (parent == NULL) {
326 /* shouldn't ever happen */
327 printk(KERN_ERR "PCI: can't move host bridge resource\n");
328 return -1;
329 }
330 res = bus->resource[i];
331 if (res == NULL)
332 return -1;
333 pr = NULL;
334 for (j = 0; j < 4; j++) {
335 struct resource *r = parent->resource[j];
336 if (!r)
337 continue;
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
339 continue;
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
341 pr = r;
342 break;
343 }
344 if (res->flags & IORESOURCE_PREFETCH)
345 pr = r;
346 }
347 if (pr == NULL)
348 return -1;
349 size = res->end - res->start;
350 if (pr->start > pr->end || size > pr->end - pr->start)
351 return -1;
352 try = pr->end;
353 for (;;) {
354 res->start = try - size;
355 res->end = try;
356 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
357 break;
358 if (conflict->start <= pr->start + size)
359 return -1;
360 try = conflict->start - 1;
361 }
362 if (request_resource(pr, res)) {
363 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
364 (u64)res->start, (u64)res->end);
365 return -1; /* "can't happen" */
366 }
367 update_bridge_base(bus, i);
368 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
369 bus->number, i, (unsigned long long)res->start,
370 (unsigned long long)res->end);
371 return 0;
372 }
373
374 static int __init
375 probe_resource(struct pci_bus *parent, struct resource *pr,
376 struct resource *res, struct resource **conflict)
377 {
378 struct pci_bus *bus;
379 struct pci_dev *dev;
380 struct resource *r;
381 int i;
382
383 for (r = pr->child; r != NULL; r = r->sibling) {
384 if (r->end >= res->start && res->end >= r->start) {
385 *conflict = r;
386 return 1;
387 }
388 }
389 list_for_each_entry(bus, &parent->children, node) {
390 for (i = 0; i < 4; ++i) {
391 if ((r = bus->resource[i]) == NULL)
392 continue;
393 if (!r->flags || r->start > r->end || r == res)
394 continue;
395 if (pci_find_parent_resource(bus->self, r) != pr)
396 continue;
397 if (r->end >= res->start && res->end >= r->start) {
398 *conflict = r;
399 return 1;
400 }
401 }
402 }
403 list_for_each_entry(dev, &parent->devices, bus_list) {
404 for (i = 0; i < 6; ++i) {
405 r = &dev->resource[i];
406 if (!r->flags || (r->flags & IORESOURCE_UNSET))
407 continue;
408 if (pci_find_parent_resource(dev, r) != pr)
409 continue;
410 if (r->end >= res->start && res->end >= r->start) {
411 *conflict = r;
412 return 1;
413 }
414 }
415 }
416 return 0;
417 }
418
419 static void __init
420 update_bridge_base(struct pci_bus *bus, int i)
421 {
422 struct resource *res = bus->resource[i];
423 u8 io_base_lo, io_limit_lo;
424 u16 mem_base, mem_limit;
425 u16 cmd;
426 unsigned long start, end, off;
427 struct pci_dev *dev = bus->self;
428 struct pci_controller *hose = dev->sysdata;
429
430 if (!hose) {
431 printk("update_bridge_base: no hose?\n");
432 return;
433 }
434 pci_read_config_word(dev, PCI_COMMAND, &cmd);
435 pci_write_config_word(dev, PCI_COMMAND,
436 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
437 if (res->flags & IORESOURCE_IO) {
438 off = (unsigned long) hose->io_base_virt - isa_io_base;
439 start = res->start - off;
440 end = res->end - off;
441 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
442 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
443 if (end > 0xffff)
444 io_base_lo |= PCI_IO_RANGE_TYPE_32;
445 else
446 io_base_lo |= PCI_IO_RANGE_TYPE_16;
447 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
448 start >> 16);
449 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
450 end >> 16);
451 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
452 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
453
454 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
455 == IORESOURCE_MEM) {
456 off = hose->pci_mem_offset;
457 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
458 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
459 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
460 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
461
462 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
463 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
464 off = hose->pci_mem_offset;
465 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
466 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
467 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
468 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
469
470 } else {
471 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
472 pci_name(dev), i, res->flags);
473 }
474 pci_write_config_word(dev, PCI_COMMAND, cmd);
475 }
476
477 static inline void alloc_resource(struct pci_dev *dev, int idx)
478 {
479 struct resource *pr, *r = &dev->resource[idx];
480
481 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
482 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
483 pr = pci_find_parent_resource(dev, r);
484 if (!pr || request_resource(pr, r) < 0) {
485 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
486 " of device %s\n", idx, pci_name(dev));
487 if (pr)
488 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
489 pr, (u64)pr->start, (u64)pr->end, pr->flags);
490 /* We'll assign a new address later */
491 r->flags |= IORESOURCE_UNSET;
492 r->end -= r->start;
493 r->start = 0;
494 }
495 }
496
497 static void __init
498 pcibios_allocate_resources(int pass)
499 {
500 struct pci_dev *dev = NULL;
501 int idx, disabled;
502 u16 command;
503 struct resource *r;
504
505 for_each_pci_dev(dev) {
506 pci_read_config_word(dev, PCI_COMMAND, &command);
507 for (idx = 0; idx < 6; idx++) {
508 r = &dev->resource[idx];
509 if (r->parent) /* Already allocated */
510 continue;
511 if (!r->flags || (r->flags & IORESOURCE_UNSET))
512 continue; /* Not assigned at all */
513 if (r->flags & IORESOURCE_IO)
514 disabled = !(command & PCI_COMMAND_IO);
515 else
516 disabled = !(command & PCI_COMMAND_MEMORY);
517 if (pass == disabled)
518 alloc_resource(dev, idx);
519 }
520 if (pass)
521 continue;
522 r = &dev->resource[PCI_ROM_RESOURCE];
523 if (r->flags & IORESOURCE_ROM_ENABLE) {
524 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
525 u32 reg;
526 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
527 r->flags &= ~IORESOURCE_ROM_ENABLE;
528 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
529 pci_write_config_dword(dev, dev->rom_base_reg,
530 reg & ~PCI_ROM_ADDRESS_ENABLE);
531 }
532 }
533 }
534
535 static void __init
536 pcibios_assign_resources(void)
537 {
538 struct pci_dev *dev = NULL;
539 int idx;
540 struct resource *r;
541
542 for_each_pci_dev(dev) {
543 int class = dev->class >> 8;
544
545 /* Don't touch classless devices and host bridges */
546 if (!class || class == PCI_CLASS_BRIDGE_HOST)
547 continue;
548
549 for (idx = 0; idx < 6; idx++) {
550 r = &dev->resource[idx];
551
552 /*
553 * We shall assign a new address to this resource,
554 * either because the BIOS (sic) forgot to do so
555 * or because we have decided the old address was
556 * unusable for some reason.
557 */
558 if ((r->flags & IORESOURCE_UNSET) && r->end &&
559 (!ppc_md.pcibios_enable_device_hook ||
560 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
561 r->flags &= ~IORESOURCE_UNSET;
562 pci_assign_resource(dev, idx);
563 }
564 }
565
566 #if 0 /* don't assign ROMs */
567 r = &dev->resource[PCI_ROM_RESOURCE];
568 r->end -= r->start;
569 r->start = 0;
570 if (r->end)
571 pci_assign_resource(dev, PCI_ROM_RESOURCE);
572 #endif
573 }
574 }
575
576
577 int
578 pcibios_enable_resources(struct pci_dev *dev, int mask)
579 {
580 u16 cmd, old_cmd;
581 int idx;
582 struct resource *r;
583
584 pci_read_config_word(dev, PCI_COMMAND, &cmd);
585 old_cmd = cmd;
586 for (idx=0; idx<6; idx++) {
587 /* Only set up the requested stuff */
588 if (!(mask & (1<<idx)))
589 continue;
590
591 r = &dev->resource[idx];
592 if (r->flags & IORESOURCE_UNSET) {
593 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
594 return -EINVAL;
595 }
596 if (r->flags & IORESOURCE_IO)
597 cmd |= PCI_COMMAND_IO;
598 if (r->flags & IORESOURCE_MEM)
599 cmd |= PCI_COMMAND_MEMORY;
600 }
601 if (dev->resource[PCI_ROM_RESOURCE].start)
602 cmd |= PCI_COMMAND_MEMORY;
603 if (cmd != old_cmd) {
604 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
605 pci_write_config_word(dev, PCI_COMMAND, cmd);
606 }
607 return 0;
608 }
609
610 static int next_controller_index;
611
612 struct pci_controller * __init
613 pcibios_alloc_controller(void)
614 {
615 struct pci_controller *hose;
616
617 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
618 memset(hose, 0, sizeof(struct pci_controller));
619
620 *hose_tail = hose;
621 hose_tail = &hose->next;
622
623 hose->index = next_controller_index++;
624
625 return hose;
626 }
627
628 #ifdef CONFIG_PPC_OF
629 /*
630 * Functions below are used on OpenFirmware machines.
631 */
632 static void
633 make_one_node_map(struct device_node* node, u8 pci_bus)
634 {
635 const int *bus_range;
636 int len;
637
638 if (pci_bus >= pci_bus_count)
639 return;
640 bus_range = get_property(node, "bus-range", &len);
641 if (bus_range == NULL || len < 2 * sizeof(int)) {
642 printk(KERN_WARNING "Can't get bus-range for %s, "
643 "assuming it starts at 0\n", node->full_name);
644 pci_to_OF_bus_map[pci_bus] = 0;
645 } else
646 pci_to_OF_bus_map[pci_bus] = bus_range[0];
647
648 for (node=node->child; node != 0;node = node->sibling) {
649 struct pci_dev* dev;
650 const unsigned int *class_code, *reg;
651
652 class_code = get_property(node, "class-code", NULL);
653 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
654 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
655 continue;
656 reg = get_property(node, "reg", NULL);
657 if (!reg)
658 continue;
659 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
660 if (!dev || !dev->subordinate)
661 continue;
662 make_one_node_map(node, dev->subordinate->number);
663 }
664 }
665
666 void
667 pcibios_make_OF_bus_map(void)
668 {
669 int i;
670 struct pci_controller* hose;
671 struct property *map_prop;
672
673 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
674 if (!pci_to_OF_bus_map) {
675 printk(KERN_ERR "Can't allocate OF bus map !\n");
676 return;
677 }
678
679 /* We fill the bus map with invalid values, that helps
680 * debugging.
681 */
682 for (i=0; i<pci_bus_count; i++)
683 pci_to_OF_bus_map[i] = 0xff;
684
685 /* For each hose, we begin searching bridges */
686 for(hose=hose_head; hose; hose=hose->next) {
687 struct device_node* node;
688 node = (struct device_node *)hose->arch_data;
689 if (!node)
690 continue;
691 make_one_node_map(node, hose->first_busno);
692 }
693 map_prop = of_find_property(find_path_device("/"),
694 "pci-OF-bus-map", NULL);
695 if (map_prop) {
696 BUG_ON(pci_bus_count > map_prop->length);
697 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
698 }
699 #ifdef DEBUG
700 printk("PCI->OF bus map:\n");
701 for (i=0; i<pci_bus_count; i++) {
702 if (pci_to_OF_bus_map[i] == 0xff)
703 continue;
704 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
705 }
706 #endif
707 }
708
709 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
710
711 static struct device_node*
712 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
713 {
714 struct device_node* sub_node;
715
716 for (; node != 0;node = node->sibling) {
717 const unsigned int *class_code;
718
719 if (filter(node, data))
720 return node;
721
722 /* For PCI<->PCI bridges or CardBus bridges, we go down
723 * Note: some OFs create a parent node "multifunc-device" as
724 * a fake root for all functions of a multi-function device,
725 * we go down them as well.
726 */
727 class_code = get_property(node, "class-code", NULL);
728 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
729 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
730 strcmp(node->name, "multifunc-device"))
731 continue;
732 sub_node = scan_OF_pci_childs(node->child, filter, data);
733 if (sub_node)
734 return sub_node;
735 }
736 return NULL;
737 }
738
739 static int
740 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
741 {
742 const unsigned int *reg;
743 u8* fdata = (u8*)data;
744
745 reg = get_property(node, "reg", NULL);
746 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
747 && ((reg[0] >> 16) & 0xff) == fdata[0])
748 return 1;
749 return 0;
750 }
751
752 static struct device_node*
753 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
754 {
755 u8 filter_data[2] = {bus, dev_fn};
756
757 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
758 }
759
760 /*
761 * Scans the OF tree for a device node matching a PCI device
762 */
763 struct device_node *
764 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
765 {
766 struct pci_controller *hose;
767 struct device_node *node;
768 int busnr;
769
770 if (!have_of)
771 return NULL;
772
773 /* Lookup the hose */
774 busnr = bus->number;
775 hose = pci_bus_to_hose(busnr);
776 if (!hose)
777 return NULL;
778
779 /* Check it has an OF node associated */
780 node = (struct device_node *) hose->arch_data;
781 if (!node)
782 return NULL;
783
784 /* Fixup bus number according to what OF think it is. */
785 #ifdef CONFIG_PPC_PMAC
786 /* The G5 need a special case here. Basically, we don't remap all
787 * busses on it so we don't create the pci-OF-map. However, we do
788 * remap the AGP bus and so have to deal with it. A future better
789 * fix has to be done by making the remapping per-host and always
790 * filling the pci_to_OF map. --BenH
791 */
792 if (machine_is(powermac) && busnr >= 0xf0)
793 busnr -= 0xf0;
794 else
795 #endif
796 if (pci_to_OF_bus_map)
797 busnr = pci_to_OF_bus_map[busnr];
798 if (busnr == 0xff)
799 return NULL;
800
801 /* Now, lookup childs of the hose */
802 return scan_OF_childs_for_device(node->child, busnr, devfn);
803 }
804 EXPORT_SYMBOL(pci_busdev_to_OF_node);
805
806 struct device_node*
807 pci_device_to_OF_node(struct pci_dev *dev)
808 {
809 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
810 }
811 EXPORT_SYMBOL(pci_device_to_OF_node);
812
813 /* This routine is meant to be used early during boot, when the
814 * PCI bus numbers have not yet been assigned, and you need to
815 * issue PCI config cycles to an OF device.
816 * It could also be used to "fix" RTAS config cycles if you want
817 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
818 * config cycles.
819 */
820 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
821 {
822 if (!have_of)
823 return NULL;
824 while(node) {
825 struct pci_controller* hose;
826 for (hose=hose_head;hose;hose=hose->next)
827 if (hose->arch_data == node)
828 return hose;
829 node=node->parent;
830 }
831 return NULL;
832 }
833
834 static int
835 find_OF_pci_device_filter(struct device_node* node, void* data)
836 {
837 return ((void *)node == data);
838 }
839
840 /*
841 * Returns the PCI device matching a given OF node
842 */
843 int
844 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
845 {
846 const unsigned int *reg;
847 struct pci_controller* hose;
848 struct pci_dev* dev = NULL;
849
850 if (!have_of)
851 return -ENODEV;
852 /* Make sure it's really a PCI device */
853 hose = pci_find_hose_for_OF_device(node);
854 if (!hose || !hose->arch_data)
855 return -ENODEV;
856 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
857 find_OF_pci_device_filter, (void *)node))
858 return -ENODEV;
859 reg = get_property(node, "reg", NULL);
860 if (!reg)
861 return -ENODEV;
862 *bus = (reg[0] >> 16) & 0xff;
863 *devfn = ((reg[0] >> 8) & 0xff);
864
865 /* Ok, here we need some tweak. If we have already renumbered
866 * all busses, we can't rely on the OF bus number any more.
867 * the pci_to_OF_bus_map is not enough as several PCI busses
868 * may match the same OF bus number.
869 */
870 if (!pci_to_OF_bus_map)
871 return 0;
872
873 for_each_pci_dev(dev)
874 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
875 dev->devfn == *devfn) {
876 *bus = dev->bus->number;
877 pci_dev_put(dev);
878 return 0;
879 }
880
881 return -ENODEV;
882 }
883 EXPORT_SYMBOL(pci_device_from_OF_node);
884
885 void __init
886 pci_process_bridge_OF_ranges(struct pci_controller *hose,
887 struct device_node *dev, int primary)
888 {
889 static unsigned int static_lc_ranges[256] __initdata;
890 const unsigned int *dt_ranges;
891 unsigned int *lc_ranges, *ranges, *prev, size;
892 int rlen = 0, orig_rlen;
893 int memno = 0;
894 struct resource *res;
895 int np, na = prom_n_addr_cells(dev);
896 np = na + 5;
897
898 /* First we try to merge ranges to fix a problem with some pmacs
899 * that can have more than 3 ranges, fortunately using contiguous
900 * addresses -- BenH
901 */
902 dt_ranges = get_property(dev, "ranges", &rlen);
903 if (!dt_ranges)
904 return;
905 /* Sanity check, though hopefully that never happens */
906 if (rlen > sizeof(static_lc_ranges)) {
907 printk(KERN_WARNING "OF ranges property too large !\n");
908 rlen = sizeof(static_lc_ranges);
909 }
910 lc_ranges = static_lc_ranges;
911 memcpy(lc_ranges, dt_ranges, rlen);
912 orig_rlen = rlen;
913
914 /* Let's work on a copy of the "ranges" property instead of damaging
915 * the device-tree image in memory
916 */
917 ranges = lc_ranges;
918 prev = NULL;
919 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
920 if (prev) {
921 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
922 (prev[2] + prev[na+4]) == ranges[2] &&
923 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
924 prev[na+4] += ranges[na+4];
925 ranges[0] = 0;
926 ranges += np;
927 continue;
928 }
929 }
930 prev = ranges;
931 ranges += np;
932 }
933
934 /*
935 * The ranges property is laid out as an array of elements,
936 * each of which comprises:
937 * cells 0 - 2: a PCI address
938 * cells 3 or 3+4: a CPU physical address
939 * (size depending on dev->n_addr_cells)
940 * cells 4+5 or 5+6: the size of the range
941 */
942 ranges = lc_ranges;
943 rlen = orig_rlen;
944 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
945 res = NULL;
946 size = ranges[na+4];
947 switch ((ranges[0] >> 24) & 0x3) {
948 case 1: /* I/O space */
949 if (ranges[2] != 0)
950 break;
951 hose->io_base_phys = ranges[na+2];
952 /* limit I/O space to 16MB */
953 if (size > 0x01000000)
954 size = 0x01000000;
955 hose->io_base_virt = ioremap(ranges[na+2], size);
956 if (primary)
957 isa_io_base = (unsigned long) hose->io_base_virt;
958 res = &hose->io_resource;
959 res->flags = IORESOURCE_IO;
960 res->start = ranges[2];
961 DBG("PCI: IO 0x%llx -> 0x%llx\n",
962 (u64)res->start, (u64)res->start + size - 1);
963 break;
964 case 2: /* memory space */
965 memno = 0;
966 if (ranges[1] == 0 && ranges[2] == 0
967 && ranges[na+4] <= (16 << 20)) {
968 /* 1st 16MB, i.e. ISA memory area */
969 if (primary)
970 isa_mem_base = ranges[na+2];
971 memno = 1;
972 }
973 while (memno < 3 && hose->mem_resources[memno].flags)
974 ++memno;
975 if (memno == 0)
976 hose->pci_mem_offset = ranges[na+2] - ranges[2];
977 if (memno < 3) {
978 res = &hose->mem_resources[memno];
979 res->flags = IORESOURCE_MEM;
980 if(ranges[0] & 0x40000000)
981 res->flags |= IORESOURCE_PREFETCH;
982 res->start = ranges[na+2];
983 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
984 (u64)res->start, (u64)res->start + size - 1);
985 }
986 break;
987 }
988 if (res != NULL) {
989 res->name = dev->full_name;
990 res->end = res->start + size - 1;
991 res->parent = NULL;
992 res->sibling = NULL;
993 res->child = NULL;
994 }
995 ranges += np;
996 }
997 }
998
999 /* We create the "pci-OF-bus-map" property now so it appears in the
1000 * /proc device tree
1001 */
1002 void __init
1003 pci_create_OF_bus_map(void)
1004 {
1005 struct property* of_prop;
1006
1007 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1008 if (of_prop && find_path_device("/")) {
1009 memset(of_prop, -1, sizeof(struct property) + 256);
1010 of_prop->name = "pci-OF-bus-map";
1011 of_prop->length = 256;
1012 of_prop->value = (unsigned char *)&of_prop[1];
1013 prom_add_property(find_path_device("/"), of_prop);
1014 }
1015 }
1016
1017 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1018 {
1019 struct pci_dev *pdev;
1020 struct device_node *np;
1021
1022 pdev = to_pci_dev (dev);
1023 np = pci_device_to_OF_node(pdev);
1024 if (np == NULL || np->full_name == NULL)
1025 return 0;
1026 return sprintf(buf, "%s", np->full_name);
1027 }
1028 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1029
1030 #else /* CONFIG_PPC_OF */
1031 void pcibios_make_OF_bus_map(void)
1032 {
1033 }
1034 #endif /* CONFIG_PPC_OF */
1035
1036 /* Add sysfs properties */
1037 void pcibios_add_platform_entries(struct pci_dev *pdev)
1038 {
1039 #ifdef CONFIG_PPC_OF
1040 device_create_file(&pdev->dev, &dev_attr_devspec);
1041 #endif /* CONFIG_PPC_OF */
1042 }
1043
1044
1045 #ifdef CONFIG_PPC_PMAC
1046 /*
1047 * This set of routines checks for PCI<->PCI bridges that have closed
1048 * IO resources and have child devices. It tries to re-open an IO
1049 * window on them.
1050 *
1051 * This is a _temporary_ fix to workaround a problem with Apple's OF
1052 * closing IO windows on P2P bridges when the OF drivers of cards
1053 * below this bridge don't claim any IO range (typically ATI or
1054 * Adaptec).
1055 *
1056 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1057 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1058 * ordering when creating the host bus resources, and maybe a few more
1059 * minor tweaks
1060 */
1061
1062 /* Initialize bridges with base/limit values we have collected */
1063 static void __init
1064 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1065 {
1066 struct pci_dev *bridge = bus->self;
1067 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1068 u32 l;
1069 u16 w;
1070 struct resource res;
1071
1072 if (bus->resource[0] == NULL)
1073 return;
1074 res = *(bus->resource[0]);
1075
1076 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1077 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1078 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1079 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
1080
1081 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1082 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1083 l &= 0xffff000f;
1084 l |= (res.start >> 8) & 0x00f0;
1085 l |= res.end & 0xf000;
1086 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1087
1088 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1089 l = (res.start >> 16) | (res.end & 0xffff0000);
1090 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1091 }
1092
1093 pci_read_config_word(bridge, PCI_COMMAND, &w);
1094 w |= PCI_COMMAND_IO;
1095 pci_write_config_word(bridge, PCI_COMMAND, w);
1096
1097 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1098 if (enable_vga) {
1099 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1100 w |= PCI_BRIDGE_CTL_VGA;
1101 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1102 }
1103 #endif
1104 }
1105
1106 /* This function is pretty basic and actually quite broken for the
1107 * general case, it's enough for us right now though. It's supposed
1108 * to tell us if we need to open an IO range at all or not and what
1109 * size.
1110 */
1111 static int __init
1112 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1113 {
1114 struct pci_dev *dev;
1115 int i;
1116 int rc = 0;
1117
1118 #define push_end(res, mask) do { \
1119 BUG_ON((mask+1) & mask); \
1120 res->end = (res->end + mask) | mask; \
1121 } while (0)
1122
1123 list_for_each_entry(dev, &bus->devices, bus_list) {
1124 u16 class = dev->class >> 8;
1125
1126 if (class == PCI_CLASS_DISPLAY_VGA ||
1127 class == PCI_CLASS_NOT_DEFINED_VGA)
1128 *found_vga = 1;
1129 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1130 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1131 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1132 push_end(res, 0xfff);
1133
1134 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1135 struct resource *r;
1136 unsigned long r_size;
1137
1138 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1139 && i >= PCI_BRIDGE_RESOURCES)
1140 continue;
1141 r = &dev->resource[i];
1142 r_size = r->end - r->start;
1143 if (r_size < 0xfff)
1144 r_size = 0xfff;
1145 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1146 rc = 1;
1147 push_end(res, r_size);
1148 }
1149 }
1150 }
1151
1152 return rc;
1153 }
1154
1155 /* Here we scan all P2P bridges of a given level that have a closed
1156 * IO window. Note that the test for the presence of a VGA card should
1157 * be improved to take into account already configured P2P bridges,
1158 * currently, we don't see them and might end up configuring 2 bridges
1159 * with VGA pass through enabled
1160 */
1161 static void __init
1162 do_fixup_p2p_level(struct pci_bus *bus)
1163 {
1164 struct pci_bus *b;
1165 int i, parent_io;
1166 int has_vga = 0;
1167
1168 for (parent_io=0; parent_io<4; parent_io++)
1169 if (bus->resource[parent_io]
1170 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1171 break;
1172 if (parent_io >= 4)
1173 return;
1174
1175 list_for_each_entry(b, &bus->children, node) {
1176 struct pci_dev *d = b->self;
1177 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1178 struct resource *res = b->resource[0];
1179 struct resource tmp_res;
1180 unsigned long max;
1181 int found_vga = 0;
1182
1183 memset(&tmp_res, 0, sizeof(tmp_res));
1184 tmp_res.start = bus->resource[parent_io]->start;
1185
1186 /* We don't let low addresses go through that closed P2P bridge, well,
1187 * that may not be necessary but I feel safer that way
1188 */
1189 if (tmp_res.start == 0)
1190 tmp_res.start = 0x1000;
1191
1192 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1193 res != bus->resource[parent_io] &&
1194 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1195 check_for_io_childs(b, &tmp_res, &found_vga)) {
1196 u8 io_base_lo;
1197
1198 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1199
1200 if (found_vga) {
1201 if (has_vga) {
1202 printk(KERN_WARNING "Skipping VGA, already active"
1203 " on bus segment\n");
1204 found_vga = 0;
1205 } else
1206 has_vga = 1;
1207 }
1208 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1209
1210 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1211 max = ((unsigned long) hose->io_base_virt
1212 - isa_io_base) + 0xffffffff;
1213 else
1214 max = ((unsigned long) hose->io_base_virt
1215 - isa_io_base) + 0xffff;
1216
1217 *res = tmp_res;
1218 res->flags = IORESOURCE_IO;
1219 res->name = b->name;
1220
1221 /* Find a resource in the parent where we can allocate */
1222 for (i = 0 ; i < 4; i++) {
1223 struct resource *r = bus->resource[i];
1224 if (!r)
1225 continue;
1226 if ((r->flags & IORESOURCE_IO) == 0)
1227 continue;
1228 DBG("Trying to allocate from %016llx, size %016llx from parent"
1229 " res %d: %016llx -> %016llx\n",
1230 res->start, res->end, i, r->start, r->end);
1231
1232 if (allocate_resource(r, res, res->end + 1, res->start, max,
1233 res->end + 1, NULL, NULL) < 0) {
1234 DBG("Failed !\n");
1235 continue;
1236 }
1237 do_update_p2p_io_resource(b, found_vga);
1238 break;
1239 }
1240 }
1241 do_fixup_p2p_level(b);
1242 }
1243 }
1244
1245 static void
1246 pcibios_fixup_p2p_bridges(void)
1247 {
1248 struct pci_bus *b;
1249
1250 list_for_each_entry(b, &pci_root_buses, node)
1251 do_fixup_p2p_level(b);
1252 }
1253
1254 #endif /* CONFIG_PPC_PMAC */
1255
1256 static int __init
1257 pcibios_init(void)
1258 {
1259 struct pci_controller *hose;
1260 struct pci_bus *bus;
1261 int next_busno;
1262
1263 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1264
1265 /* Scan all of the recorded PCI controllers. */
1266 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1267 if (pci_assign_all_buses)
1268 hose->first_busno = next_busno;
1269 hose->last_busno = 0xff;
1270 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1271 hose->ops, hose);
1272 if (bus)
1273 pci_bus_add_devices(bus);
1274 hose->last_busno = bus->subordinate;
1275 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1276 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1277 }
1278 pci_bus_count = next_busno;
1279
1280 /* OpenFirmware based machines need a map of OF bus
1281 * numbers vs. kernel bus numbers since we may have to
1282 * remap them.
1283 */
1284 if (pci_assign_all_buses && have_of)
1285 pcibios_make_OF_bus_map();
1286
1287 /* Call machine dependent fixup */
1288 if (ppc_md.pcibios_fixup)
1289 ppc_md.pcibios_fixup();
1290
1291 /* Allocate and assign resources */
1292 pcibios_allocate_bus_resources(&pci_root_buses);
1293 pcibios_allocate_resources(0);
1294 pcibios_allocate_resources(1);
1295 #ifdef CONFIG_PPC_PMAC
1296 pcibios_fixup_p2p_bridges();
1297 #endif /* CONFIG_PPC_PMAC */
1298 pcibios_assign_resources();
1299
1300 /* Call machine dependent post-init code */
1301 if (ppc_md.pcibios_after_init)
1302 ppc_md.pcibios_after_init();
1303
1304 return 0;
1305 }
1306
1307 subsys_initcall(pcibios_init);
1308
1309 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1310 unsigned long start, unsigned long size)
1311 {
1312 return start;
1313 }
1314
1315 void __init pcibios_fixup_bus(struct pci_bus *bus)
1316 {
1317 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1318 unsigned long io_offset;
1319 struct resource *res;
1320 struct pci_dev *dev;
1321 int i;
1322
1323 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1324 if (bus->parent == NULL) {
1325 /* This is a host bridge - fill in its resources */
1326 hose->bus = bus;
1327
1328 bus->resource[0] = res = &hose->io_resource;
1329 if (!res->flags) {
1330 if (io_offset)
1331 printk(KERN_ERR "I/O resource not set for host"
1332 " bridge %d\n", hose->index);
1333 res->start = 0;
1334 res->end = IO_SPACE_LIMIT;
1335 res->flags = IORESOURCE_IO;
1336 }
1337 res->start += io_offset;
1338 res->end += io_offset;
1339
1340 for (i = 0; i < 3; ++i) {
1341 res = &hose->mem_resources[i];
1342 if (!res->flags) {
1343 if (i > 0)
1344 continue;
1345 printk(KERN_ERR "Memory resource not set for "
1346 "host bridge %d\n", hose->index);
1347 res->start = hose->pci_mem_offset;
1348 res->end = ~0U;
1349 res->flags = IORESOURCE_MEM;
1350 }
1351 bus->resource[i+1] = res;
1352 }
1353 } else {
1354 /* This is a subordinate bridge */
1355 pci_read_bridge_bases(bus);
1356
1357 for (i = 0; i < 4; ++i) {
1358 if ((res = bus->resource[i]) == NULL)
1359 continue;
1360 if (!res->flags)
1361 continue;
1362 if (io_offset && (res->flags & IORESOURCE_IO)) {
1363 res->start += io_offset;
1364 res->end += io_offset;
1365 } else if (hose->pci_mem_offset
1366 && (res->flags & IORESOURCE_MEM)) {
1367 res->start += hose->pci_mem_offset;
1368 res->end += hose->pci_mem_offset;
1369 }
1370 }
1371 }
1372
1373 /* Platform specific bus fixups */
1374 if (ppc_md.pcibios_fixup_bus)
1375 ppc_md.pcibios_fixup_bus(bus);
1376
1377 /* Read default IRQs and fixup if necessary */
1378 list_for_each_entry(dev, &bus->devices, bus_list) {
1379 pci_read_irq_line(dev);
1380 if (ppc_md.pci_irq_fixup)
1381 ppc_md.pci_irq_fixup(dev);
1382 }
1383 }
1384
1385 char __init *pcibios_setup(char *str)
1386 {
1387 return str;
1388 }
1389
1390 /* the next one is stolen from the alpha port... */
1391 void __init
1392 pcibios_update_irq(struct pci_dev *dev, int irq)
1393 {
1394 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1395 /* XXX FIXME - update OF device tree node interrupt property */
1396 }
1397
1398 #ifdef CONFIG_PPC_MERGE
1399 /* XXX This is a copy of the ppc64 version. This is temporary until we start
1400 * merging the 2 PCI layers
1401 */
1402 /*
1403 * Reads the interrupt pin to determine if interrupt is use by card.
1404 * If the interrupt is used, then gets the interrupt line from the
1405 * openfirmware and sets it in the pci_dev and pci_config line.
1406 */
1407 int pci_read_irq_line(struct pci_dev *pci_dev)
1408 {
1409 struct of_irq oirq;
1410 unsigned int virq;
1411
1412 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1413
1414 /* Try to get a mapping from the device-tree */
1415 if (of_irq_map_pci(pci_dev, &oirq)) {
1416 u8 line, pin;
1417
1418 /* If that fails, lets fallback to what is in the config
1419 * space and map that through the default controller. We
1420 * also set the type to level low since that's what PCI
1421 * interrupts are. If your platform does differently, then
1422 * either provide a proper interrupt tree or don't use this
1423 * function.
1424 */
1425 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1426 return -1;
1427 if (pin == 0)
1428 return -1;
1429 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1430 line == 0xff) {
1431 return -1;
1432 }
1433 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1434
1435 virq = irq_create_mapping(NULL, line);
1436 if (virq != NO_IRQ)
1437 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1438 } else {
1439 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1440 oirq.size, oirq.specifier[0], oirq.controller->full_name);
1441
1442 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1443 oirq.size);
1444 }
1445 if(virq == NO_IRQ) {
1446 DBG(" -> failed to map !\n");
1447 return -1;
1448 }
1449 pci_dev->irq = virq;
1450 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1451
1452 return 0;
1453 }
1454 EXPORT_SYMBOL(pci_read_irq_line);
1455 #endif /* CONFIG_PPC_MERGE */
1456
1457 int pcibios_enable_device(struct pci_dev *dev, int mask)
1458 {
1459 u16 cmd, old_cmd;
1460 int idx;
1461 struct resource *r;
1462
1463 if (ppc_md.pcibios_enable_device_hook)
1464 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1465 return -EINVAL;
1466
1467 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1468 old_cmd = cmd;
1469 for (idx=0; idx<6; idx++) {
1470 r = &dev->resource[idx];
1471 if (r->flags & IORESOURCE_UNSET) {
1472 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1473 return -EINVAL;
1474 }
1475 if (r->flags & IORESOURCE_IO)
1476 cmd |= PCI_COMMAND_IO;
1477 if (r->flags & IORESOURCE_MEM)
1478 cmd |= PCI_COMMAND_MEMORY;
1479 }
1480 if (cmd != old_cmd) {
1481 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1482 pci_name(dev), old_cmd, cmd);
1483 pci_write_config_word(dev, PCI_COMMAND, cmd);
1484 }
1485 return 0;
1486 }
1487
1488 struct pci_controller*
1489 pci_bus_to_hose(int bus)
1490 {
1491 struct pci_controller* hose = hose_head;
1492
1493 for (; hose; hose = hose->next)
1494 if (bus >= hose->first_busno && bus <= hose->last_busno)
1495 return hose;
1496 return NULL;
1497 }
1498
1499 void __iomem *
1500 pci_bus_io_base(unsigned int bus)
1501 {
1502 struct pci_controller *hose;
1503
1504 hose = pci_bus_to_hose(bus);
1505 if (!hose)
1506 return NULL;
1507 return hose->io_base_virt;
1508 }
1509
1510 unsigned long
1511 pci_bus_io_base_phys(unsigned int bus)
1512 {
1513 struct pci_controller *hose;
1514
1515 hose = pci_bus_to_hose(bus);
1516 if (!hose)
1517 return 0;
1518 return hose->io_base_phys;
1519 }
1520
1521 unsigned long
1522 pci_bus_mem_base_phys(unsigned int bus)
1523 {
1524 struct pci_controller *hose;
1525
1526 hose = pci_bus_to_hose(bus);
1527 if (!hose)
1528 return 0;
1529 return hose->pci_mem_offset;
1530 }
1531
1532 unsigned long
1533 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1534 {
1535 /* Hack alert again ! See comments in chrp_pci.c
1536 */
1537 struct pci_controller* hose =
1538 (struct pci_controller *)pdev->sysdata;
1539 if (hose && res->flags & IORESOURCE_MEM)
1540 return res->start - hose->pci_mem_offset;
1541 /* We may want to do something with IOs here... */
1542 return res->start;
1543 }
1544
1545
1546 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1547 unsigned long *offset,
1548 enum pci_mmap_state mmap_state)
1549 {
1550 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1551 unsigned long io_offset = 0;
1552 int i, res_bit;
1553
1554 if (hose == 0)
1555 return NULL; /* should never happen */
1556
1557 /* If memory, add on the PCI bridge address offset */
1558 if (mmap_state == pci_mmap_mem) {
1559 *offset += hose->pci_mem_offset;
1560 res_bit = IORESOURCE_MEM;
1561 } else {
1562 io_offset = hose->io_base_virt - (void __iomem *)_IO_BASE;
1563 *offset += io_offset;
1564 res_bit = IORESOURCE_IO;
1565 }
1566
1567 /*
1568 * Check that the offset requested corresponds to one of the
1569 * resources of the device.
1570 */
1571 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1572 struct resource *rp = &dev->resource[i];
1573 int flags = rp->flags;
1574
1575 /* treat ROM as memory (should be already) */
1576 if (i == PCI_ROM_RESOURCE)
1577 flags |= IORESOURCE_MEM;
1578
1579 /* Active and same type? */
1580 if ((flags & res_bit) == 0)
1581 continue;
1582
1583 /* In the range of this resource? */
1584 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1585 continue;
1586
1587 /* found it! construct the final physical address */
1588 if (mmap_state == pci_mmap_io)
1589 *offset += hose->io_base_phys - io_offset;
1590 return rp;
1591 }
1592
1593 return NULL;
1594 }
1595
1596 /*
1597 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1598 * device mapping.
1599 */
1600 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1601 pgprot_t protection,
1602 enum pci_mmap_state mmap_state,
1603 int write_combine)
1604 {
1605 unsigned long prot = pgprot_val(protection);
1606
1607 /* Write combine is always 0 on non-memory space mappings. On
1608 * memory space, if the user didn't pass 1, we check for a
1609 * "prefetchable" resource. This is a bit hackish, but we use
1610 * this to workaround the inability of /sysfs to provide a write
1611 * combine bit
1612 */
1613 if (mmap_state != pci_mmap_mem)
1614 write_combine = 0;
1615 else if (write_combine == 0) {
1616 if (rp->flags & IORESOURCE_PREFETCH)
1617 write_combine = 1;
1618 }
1619
1620 /* XXX would be nice to have a way to ask for write-through */
1621 prot |= _PAGE_NO_CACHE;
1622 if (write_combine)
1623 prot &= ~_PAGE_GUARDED;
1624 else
1625 prot |= _PAGE_GUARDED;
1626
1627 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev),
1628 (unsigned long long)rp->start, prot);
1629
1630 return __pgprot(prot);
1631 }
1632
1633 /*
1634 * This one is used by /dev/mem and fbdev who have no clue about the
1635 * PCI device, it tries to find the PCI device first and calls the
1636 * above routine
1637 */
1638 pgprot_t pci_phys_mem_access_prot(struct file *file,
1639 unsigned long pfn,
1640 unsigned long size,
1641 pgprot_t protection)
1642 {
1643 struct pci_dev *pdev = NULL;
1644 struct resource *found = NULL;
1645 unsigned long prot = pgprot_val(protection);
1646 unsigned long offset = pfn << PAGE_SHIFT;
1647 int i;
1648
1649 if (page_is_ram(pfn))
1650 return prot;
1651
1652 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1653
1654 for_each_pci_dev(pdev) {
1655 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1656 struct resource *rp = &pdev->resource[i];
1657 int flags = rp->flags;
1658
1659 /* Active and same type? */
1660 if ((flags & IORESOURCE_MEM) == 0)
1661 continue;
1662 /* In the range of this resource? */
1663 if (offset < (rp->start & PAGE_MASK) ||
1664 offset > rp->end)
1665 continue;
1666 found = rp;
1667 break;
1668 }
1669 if (found)
1670 break;
1671 }
1672 if (found) {
1673 if (found->flags & IORESOURCE_PREFETCH)
1674 prot &= ~_PAGE_GUARDED;
1675 pci_dev_put(pdev);
1676 }
1677
1678 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1679
1680 return __pgprot(prot);
1681 }
1682
1683
1684 /*
1685 * Perform the actual remap of the pages for a PCI device mapping, as
1686 * appropriate for this architecture. The region in the process to map
1687 * is described by vm_start and vm_end members of VMA, the base physical
1688 * address is found in vm_pgoff.
1689 * The pci device structure is provided so that architectures may make mapping
1690 * decisions on a per-device or per-bus basis.
1691 *
1692 * Returns a negative error code on failure, zero on success.
1693 */
1694 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1695 enum pci_mmap_state mmap_state,
1696 int write_combine)
1697 {
1698 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1699 struct resource *rp;
1700 int ret;
1701
1702 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1703 if (rp == NULL)
1704 return -EINVAL;
1705
1706 vma->vm_pgoff = offset >> PAGE_SHIFT;
1707 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1708 vma->vm_page_prot,
1709 mmap_state, write_combine);
1710
1711 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1712 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1713
1714 return ret;
1715 }
1716
1717 /* Obsolete functions. Should be removed once the symbios driver
1718 * is fixed
1719 */
1720 unsigned long
1721 phys_to_bus(unsigned long pa)
1722 {
1723 struct pci_controller *hose;
1724 int i;
1725
1726 for (hose = hose_head; hose; hose = hose->next) {
1727 for (i = 0; i < 3; ++i) {
1728 if (pa >= hose->mem_resources[i].start
1729 && pa <= hose->mem_resources[i].end) {
1730 /*
1731 * XXX the hose->pci_mem_offset really
1732 * only applies to mem_resources[0].
1733 * We need a way to store an offset for
1734 * the others. -- paulus
1735 */
1736 if (i == 0)
1737 pa -= hose->pci_mem_offset;
1738 return pa;
1739 }
1740 }
1741 }
1742 /* hmmm, didn't find it */
1743 return 0;
1744 }
1745
1746 unsigned long
1747 pci_phys_to_bus(unsigned long pa, int busnr)
1748 {
1749 struct pci_controller* hose = pci_bus_to_hose(busnr);
1750 if (!hose)
1751 return pa;
1752 return pa - hose->pci_mem_offset;
1753 }
1754
1755 unsigned long
1756 pci_bus_to_phys(unsigned int ba, int busnr)
1757 {
1758 struct pci_controller* hose = pci_bus_to_hose(busnr);
1759 if (!hose)
1760 return ba;
1761 return ba + hose->pci_mem_offset;
1762 }
1763
1764 /* Provide information on locations of various I/O regions in physical
1765 * memory. Do this on a per-card basis so that we choose the right
1766 * root bridge.
1767 * Note that the returned IO or memory base is a physical address
1768 */
1769
1770 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1771 {
1772 struct pci_controller* hose;
1773 long result = -EOPNOTSUPP;
1774
1775 /* Argh ! Please forgive me for that hack, but that's the
1776 * simplest way to get existing XFree to not lockup on some
1777 * G5 machines... So when something asks for bus 0 io base
1778 * (bus 0 is HT root), we return the AGP one instead.
1779 */
1780 #ifdef CONFIG_PPC_PMAC
1781 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1782 if (bus == 0)
1783 bus = 0xf0;
1784 #endif /* CONFIG_PPC_PMAC */
1785
1786 hose = pci_bus_to_hose(bus);
1787 if (!hose)
1788 return -ENODEV;
1789
1790 switch (which) {
1791 case IOBASE_BRIDGE_NUMBER:
1792 return (long)hose->first_busno;
1793 case IOBASE_MEMORY:
1794 return (long)hose->pci_mem_offset;
1795 case IOBASE_IO:
1796 return (long)hose->io_base_phys;
1797 case IOBASE_ISA_IO:
1798 return (long)isa_io_base;
1799 case IOBASE_ISA_MEM:
1800 return (long)isa_mem_base;
1801 }
1802
1803 return result;
1804 }
1805
1806 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1807 const struct resource *rsrc,
1808 resource_size_t *start, resource_size_t *end)
1809 {
1810 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1811 unsigned long offset = 0;
1812
1813 if (hose == NULL)
1814 return;
1815
1816 if (rsrc->flags & IORESOURCE_IO)
1817 offset = (void __iomem *)_IO_BASE - hose->io_base_virt
1818 + hose->io_base_phys;
1819
1820 *start = rsrc->start + offset;
1821 *end = rsrc->end + offset;
1822 }
1823
1824 void __init
1825 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1826 int flags, char *name)
1827 {
1828 res->start = start;
1829 res->end = end;
1830 res->flags = flags;
1831 res->name = name;
1832 res->parent = NULL;
1833 res->sibling = NULL;
1834 res->child = NULL;
1835 }
1836
1837 unsigned long pci_address_to_pio(phys_addr_t address)
1838 {
1839 struct pci_controller* hose = hose_head;
1840
1841 for (; hose; hose = hose->next) {
1842 unsigned int size = hose->io_resource.end -
1843 hose->io_resource.start + 1;
1844 if (address >= hose->io_base_phys &&
1845 address < (hose->io_base_phys + size)) {
1846 unsigned long base =
1847 (unsigned long)hose->io_base_virt - _IO_BASE;
1848 return base + (address - hose->io_base_phys);
1849 }
1850 }
1851 return (unsigned int)-1;
1852 }
1853 EXPORT_SYMBOL(pci_address_to_pio);
1854
1855 /*
1856 * Null PCI config access functions, for the case when we can't
1857 * find a hose.
1858 */
1859 #define NULL_PCI_OP(rw, size, type) \
1860 static int \
1861 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1862 { \
1863 return PCIBIOS_DEVICE_NOT_FOUND; \
1864 }
1865
1866 static int
1867 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1868 int len, u32 *val)
1869 {
1870 return PCIBIOS_DEVICE_NOT_FOUND;
1871 }
1872
1873 static int
1874 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1875 int len, u32 val)
1876 {
1877 return PCIBIOS_DEVICE_NOT_FOUND;
1878 }
1879
1880 static struct pci_ops null_pci_ops =
1881 {
1882 null_read_config,
1883 null_write_config
1884 };
1885
1886 /*
1887 * These functions are used early on before PCI scanning is done
1888 * and all of the pci_dev and pci_bus structures have been created.
1889 */
1890 static struct pci_bus *
1891 fake_pci_bus(struct pci_controller *hose, int busnr)
1892 {
1893 static struct pci_bus bus;
1894
1895 if (hose == 0) {
1896 hose = pci_bus_to_hose(busnr);
1897 if (hose == 0)
1898 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1899 }
1900 bus.number = busnr;
1901 bus.sysdata = hose;
1902 bus.ops = hose? hose->ops: &null_pci_ops;
1903 return &bus;
1904 }
1905
1906 #define EARLY_PCI_OP(rw, size, type) \
1907 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1908 int devfn, int offset, type value) \
1909 { \
1910 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1911 devfn, offset, value); \
1912 }
1913
1914 EARLY_PCI_OP(read, byte, u8 *)
1915 EARLY_PCI_OP(read, word, u16 *)
1916 EARLY_PCI_OP(read, dword, u32 *)
1917 EARLY_PCI_OP(write, byte, u8)
1918 EARLY_PCI_OP(write, word, u16)
1919 EARLY_PCI_OP(write, dword, u32)
linux kernel for loongson