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drm: move to kref per-master structures.
[linux-2.6/linux-loongson.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob7b37a49063775332dd88daa738517c9fbdfb4305
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #include "radeon_microcode.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45
46 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
47 {
48 u32 ret;
49 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
50 ret = RADEON_READ(R520_MC_IND_DATA);
51 RADEON_WRITE(R520_MC_IND_INDEX, 0);
52 return ret;
53 }
54
55 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56 {
57 u32 ret;
58 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
59 ret = RADEON_READ(RS480_NB_MC_DATA);
60 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
61 return ret;
62 }
63
64 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65 {
66 u32 ret;
67 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
68 ret = RADEON_READ(RS690_MC_DATA);
69 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
70 return ret;
71 }
72
73 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
74 {
75 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
76 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
77 return RS690_READ_MCIND(dev_priv, addr);
78 else
79 return RS480_READ_MCIND(dev_priv, addr);
80 }
81
82 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
83 {
84
85 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
86 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
87 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
88 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
89 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
90 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
91 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
92 else
93 return RADEON_READ(RADEON_MC_FB_LOCATION);
94 }
95
96 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
97 {
98 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
99 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
100 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
101 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
102 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
103 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
104 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
105 else
106 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
107 }
108
109 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
110 {
111 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
112 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
113 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
114 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
115 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
116 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
117 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
118 else
119 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
120 }
121
122 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
123 {
124 u32 agp_base_hi = upper_32_bits(agp_base);
125 u32 agp_base_lo = agp_base & 0xffffffff;
126
127 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
128 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
130 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
131 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
133 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
134 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
135 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
136 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
137 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
138 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
139 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
140 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
141 } else {
142 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
143 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
144 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
145 }
146 }
147
148 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
149 {
150 drm_radeon_private_t *dev_priv = dev->dev_private;
151
152 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
153 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
154 }
155
156 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
157 {
158 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
159 return RADEON_READ(RADEON_PCIE_DATA);
160 }
161
162 #if RADEON_FIFO_DEBUG
163 static void radeon_status(drm_radeon_private_t * dev_priv)
164 {
165 printk("%s:\n", __func__);
166 printk("RBBM_STATUS = 0x%08x\n",
167 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
168 printk("CP_RB_RTPR = 0x%08x\n",
169 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
170 printk("CP_RB_WTPR = 0x%08x\n",
171 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
172 printk("AIC_CNTL = 0x%08x\n",
173 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
174 printk("AIC_STAT = 0x%08x\n",
175 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
176 printk("AIC_PT_BASE = 0x%08x\n",
177 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
178 printk("TLB_ADDR = 0x%08x\n",
179 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
180 printk("TLB_DATA = 0x%08x\n",
181 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
182 }
183 #endif
184
185 /* ================================================================
186 * Engine, FIFO control
187 */
188
189 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
190 {
191 u32 tmp;
192 int i;
193
194 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
195
196 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
197 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
198 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
199 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
200
201 for (i = 0; i < dev_priv->usec_timeout; i++) {
202 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
203 & RADEON_RB3D_DC_BUSY)) {
204 return 0;
205 }
206 DRM_UDELAY(1);
207 }
208 } else {
209 /* don't flush or purge cache here or lockup */
210 return 0;
211 }
212
213 #if RADEON_FIFO_DEBUG
214 DRM_ERROR("failed!\n");
215 radeon_status(dev_priv);
216 #endif
217 return -EBUSY;
218 }
219
220 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
221 {
222 int i;
223
224 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
225
226 for (i = 0; i < dev_priv->usec_timeout; i++) {
227 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
228 & RADEON_RBBM_FIFOCNT_MASK);
229 if (slots >= entries)
230 return 0;
231 DRM_UDELAY(1);
232 }
233 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
234 RADEON_READ(RADEON_RBBM_STATUS),
235 RADEON_READ(R300_VAP_CNTL_STATUS));
236
237 #if RADEON_FIFO_DEBUG
238 DRM_ERROR("failed!\n");
239 radeon_status(dev_priv);
240 #endif
241 return -EBUSY;
242 }
243
244 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
245 {
246 int i, ret;
247
248 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
249
250 ret = radeon_do_wait_for_fifo(dev_priv, 64);
251 if (ret)
252 return ret;
253
254 for (i = 0; i < dev_priv->usec_timeout; i++) {
255 if (!(RADEON_READ(RADEON_RBBM_STATUS)
256 & RADEON_RBBM_ACTIVE)) {
257 radeon_do_pixcache_flush(dev_priv);
258 return 0;
259 }
260 DRM_UDELAY(1);
261 }
262 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
263 RADEON_READ(RADEON_RBBM_STATUS),
264 RADEON_READ(R300_VAP_CNTL_STATUS));
265
266 #if RADEON_FIFO_DEBUG
267 DRM_ERROR("failed!\n");
268 radeon_status(dev_priv);
269 #endif
270 return -EBUSY;
271 }
272
273 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
274 {
275 uint32_t gb_tile_config, gb_pipe_sel = 0;
276
277 /* RS4xx/RS6xx/R4xx/R5xx */
278 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
279 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
280 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
281 } else {
282 /* R3xx */
283 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
284 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
285 dev_priv->num_gb_pipes = 2;
286 } else {
287 /* R3Vxx */
288 dev_priv->num_gb_pipes = 1;
289 }
290 }
291 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
292
293 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
294
295 switch (dev_priv->num_gb_pipes) {
296 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
297 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
298 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
299 default:
300 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
301 }
302
303 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
304 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
305 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
306 }
307 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
308 radeon_do_wait_for_idle(dev_priv);
309 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
310 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
311 R300_DC_AUTOFLUSH_ENABLE |
312 R300_DC_DC_DISABLE_IGNORE_PE));
313
314
315 }
316
317 /* ================================================================
318 * CP control, initialization
319 */
320
321 /* Load the microcode for the CP */
322 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
323 {
324 int i;
325 DRM_DEBUG("\n");
326
327 radeon_do_wait_for_idle(dev_priv);
328
329 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
330 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
335 DRM_INFO("Loading R100 Microcode\n");
336 for (i = 0; i < 256; i++) {
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
338 R100_cp_microcode[i][1]);
339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
340 R100_cp_microcode[i][0]);
341 }
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
346 DRM_INFO("Loading R200 Microcode\n");
347 for (i = 0; i < 256; i++) {
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
349 R200_cp_microcode[i][1]);
350 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
351 R200_cp_microcode[i][0]);
352 }
353 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
359 DRM_INFO("Loading R300 Microcode\n");
360 for (i = 0; i < 256; i++) {
361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
362 R300_cp_microcode[i][1]);
363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
364 R300_cp_microcode[i][0]);
365 }
366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
368 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
369 DRM_INFO("Loading R400 Microcode\n");
370 for (i = 0; i < 256; i++) {
371 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
372 R420_cp_microcode[i][1]);
373 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
374 R420_cp_microcode[i][0]);
375 }
376 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
378 DRM_INFO("Loading RS690/RS740 Microcode\n");
379 for (i = 0; i < 256; i++) {
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
381 RS690_cp_microcode[i][1]);
382 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
383 RS690_cp_microcode[i][0]);
384 }
385 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
391 DRM_INFO("Loading R500 Microcode\n");
392 for (i = 0; i < 256; i++) {
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
394 R520_cp_microcode[i][1]);
395 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
396 R520_cp_microcode[i][0]);
397 }
398 }
399 }
400
401 /* Flush any pending commands to the CP. This should only be used just
402 * prior to a wait for idle, as it informs the engine that the command
403 * stream is ending.
404 */
405 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
406 {
407 DRM_DEBUG("\n");
408 #if 0
409 u32 tmp;
410
411 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
412 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
413 #endif
414 }
415
416 /* Wait for the CP to go idle.
417 */
418 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
419 {
420 RING_LOCALS;
421 DRM_DEBUG("\n");
422
423 BEGIN_RING(6);
424
425 RADEON_PURGE_CACHE();
426 RADEON_PURGE_ZCACHE();
427 RADEON_WAIT_UNTIL_IDLE();
428
429 ADVANCE_RING();
430 COMMIT_RING();
431
432 return radeon_do_wait_for_idle(dev_priv);
433 }
434
435 /* Start the Command Processor.
436 */
437 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
438 {
439 RING_LOCALS;
440 DRM_DEBUG("\n");
441
442 radeon_do_wait_for_idle(dev_priv);
443
444 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
445
446 dev_priv->cp_running = 1;
447
448 BEGIN_RING(8);
449 /* isync can only be written through cp on r5xx write it here */
450 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
451 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
452 RADEON_ISYNC_ANY3D_IDLE2D |
453 RADEON_ISYNC_WAIT_IDLEGUI |
454 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
455 RADEON_PURGE_CACHE();
456 RADEON_PURGE_ZCACHE();
457 RADEON_WAIT_UNTIL_IDLE();
458 ADVANCE_RING();
459 COMMIT_RING();
460
461 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
462 }
463
464 /* Reset the Command Processor. This will not flush any pending
465 * commands, so you must wait for the CP command stream to complete
466 * before calling this routine.
467 */
468 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
469 {
470 u32 cur_read_ptr;
471 DRM_DEBUG("\n");
472
473 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
474 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
475 SET_RING_HEAD(dev_priv, cur_read_ptr);
476 dev_priv->ring.tail = cur_read_ptr;
477 }
478
479 /* Stop the Command Processor. This will not flush any pending
480 * commands, so you must flush the command stream and wait for the CP
481 * to go idle before calling this routine.
482 */
483 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
484 {
485 DRM_DEBUG("\n");
486
487 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
488
489 dev_priv->cp_running = 0;
490 }
491
492 /* Reset the engine. This will stop the CP if it is running.
493 */
494 static int radeon_do_engine_reset(struct drm_device * dev)
495 {
496 drm_radeon_private_t *dev_priv = dev->dev_private;
497 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
498 DRM_DEBUG("\n");
499
500 radeon_do_pixcache_flush(dev_priv);
501
502 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
503 /* may need something similar for newer chips */
504 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
505 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
506
507 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
508 RADEON_FORCEON_MCLKA |
509 RADEON_FORCEON_MCLKB |
510 RADEON_FORCEON_YCLKA |
511 RADEON_FORCEON_YCLKB |
512 RADEON_FORCEON_MC |
513 RADEON_FORCEON_AIC));
514 }
515
516 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
517
518 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
519 RADEON_SOFT_RESET_CP |
520 RADEON_SOFT_RESET_HI |
521 RADEON_SOFT_RESET_SE |
522 RADEON_SOFT_RESET_RE |
523 RADEON_SOFT_RESET_PP |
524 RADEON_SOFT_RESET_E2 |
525 RADEON_SOFT_RESET_RB));
526 RADEON_READ(RADEON_RBBM_SOFT_RESET);
527 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
528 ~(RADEON_SOFT_RESET_CP |
529 RADEON_SOFT_RESET_HI |
530 RADEON_SOFT_RESET_SE |
531 RADEON_SOFT_RESET_RE |
532 RADEON_SOFT_RESET_PP |
533 RADEON_SOFT_RESET_E2 |
534 RADEON_SOFT_RESET_RB)));
535 RADEON_READ(RADEON_RBBM_SOFT_RESET);
536
537 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
538 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
539 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
540 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
541 }
542
543 /* setup the raster pipes */
544 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
545 radeon_init_pipes(dev_priv);
546
547 /* Reset the CP ring */
548 radeon_do_cp_reset(dev_priv);
549
550 /* The CP is no longer running after an engine reset */
551 dev_priv->cp_running = 0;
552
553 /* Reset any pending vertex, indirect buffers */
554 radeon_freelist_reset(dev);
555
556 return 0;
557 }
558
559 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
560 drm_radeon_private_t * dev_priv)
561 {
562 u32 ring_start, cur_read_ptr;
563 u32 tmp;
564
565 /* Initialize the memory controller. With new memory map, the fb location
566 * is not changed, it should have been properly initialized already. Part
567 * of the problem is that the code below is bogus, assuming the GART is
568 * always appended to the fb which is not necessarily the case
569 */
570 if (!dev_priv->new_memmap)
571 radeon_write_fb_location(dev_priv,
572 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
573 | (dev_priv->fb_location >> 16));
574
575 #if __OS_HAS_AGP
576 if (dev_priv->flags & RADEON_IS_AGP) {
577 radeon_write_agp_base(dev_priv, dev->agp->base);
578
579 radeon_write_agp_location(dev_priv,
580 (((dev_priv->gart_vm_start - 1 +
581 dev_priv->gart_size) & 0xffff0000) |
582 (dev_priv->gart_vm_start >> 16)));
583
584 ring_start = (dev_priv->cp_ring->offset
585 - dev->agp->base
586 + dev_priv->gart_vm_start);
587 } else
588 #endif
589 ring_start = (dev_priv->cp_ring->offset
590 - (unsigned long)dev->sg->virtual
591 + dev_priv->gart_vm_start);
592
593 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
594
595 /* Set the write pointer delay */
596 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
597
598 /* Initialize the ring buffer's read and write pointers */
599 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
600 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
601 SET_RING_HEAD(dev_priv, cur_read_ptr);
602 dev_priv->ring.tail = cur_read_ptr;
603
604 #if __OS_HAS_AGP
605 if (dev_priv->flags & RADEON_IS_AGP) {
606 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
607 dev_priv->ring_rptr->offset
608 - dev->agp->base + dev_priv->gart_vm_start);
609 } else
610 #endif
611 {
612 struct drm_sg_mem *entry = dev->sg;
613 unsigned long tmp_ofs, page_ofs;
614
615 tmp_ofs = dev_priv->ring_rptr->offset -
616 (unsigned long)dev->sg->virtual;
617 page_ofs = tmp_ofs >> PAGE_SHIFT;
618
619 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
620 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
621 (unsigned long)entry->busaddr[page_ofs],
622 entry->handle + tmp_ofs);
623 }
624
625 /* Set ring buffer size */
626 #ifdef __BIG_ENDIAN
627 RADEON_WRITE(RADEON_CP_RB_CNTL,
628 RADEON_BUF_SWAP_32BIT |
629 (dev_priv->ring.fetch_size_l2ow << 18) |
630 (dev_priv->ring.rptr_update_l2qw << 8) |
631 dev_priv->ring.size_l2qw);
632 #else
633 RADEON_WRITE(RADEON_CP_RB_CNTL,
634 (dev_priv->ring.fetch_size_l2ow << 18) |
635 (dev_priv->ring.rptr_update_l2qw << 8) |
636 dev_priv->ring.size_l2qw);
637 #endif
638
639
640 /* Initialize the scratch register pointer. This will cause
641 * the scratch register values to be written out to memory
642 * whenever they are updated.
643 *
644 * We simply put this behind the ring read pointer, this works
645 * with PCI GART as well as (whatever kind of) AGP GART
646 */
647 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
648 + RADEON_SCRATCH_REG_OFFSET);
649
650 dev_priv->scratch = ((__volatile__ u32 *)
651 dev_priv->ring_rptr->handle +
652 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
653
654 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
655
656 /* Turn on bus mastering */
657 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
658 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
659 /* rs600/rs690/rs740 */
660 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
661 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
662 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
663 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
664 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
665 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
666 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
667 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
668 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
669 } /* PCIE cards appears to not need this */
670
671 dev_priv->scratch[0] = 0;
672 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
673
674 dev_priv->scratch[1] = 0;
675 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
676
677 dev_priv->scratch[2] = 0;
678 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
679
680 radeon_do_wait_for_idle(dev_priv);
681
682 /* Sync everything up */
683 RADEON_WRITE(RADEON_ISYNC_CNTL,
684 (RADEON_ISYNC_ANY2D_IDLE3D |
685 RADEON_ISYNC_ANY3D_IDLE2D |
686 RADEON_ISYNC_WAIT_IDLEGUI |
687 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
688
689 }
690
691 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
692 {
693 u32 tmp;
694
695 /* Start with assuming that writeback doesn't work */
696 dev_priv->writeback_works = 0;
697
698 /* Writeback doesn't seem to work everywhere, test it here and possibly
699 * enable it if it appears to work
700 */
701 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
702 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
703
704 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
705 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
706 0xdeadbeef)
707 break;
708 DRM_UDELAY(1);
709 }
710
711 if (tmp < dev_priv->usec_timeout) {
712 dev_priv->writeback_works = 1;
713 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
714 } else {
715 dev_priv->writeback_works = 0;
716 DRM_INFO("writeback test failed\n");
717 }
718 if (radeon_no_wb == 1) {
719 dev_priv->writeback_works = 0;
720 DRM_INFO("writeback forced off\n");
721 }
722
723 if (!dev_priv->writeback_works) {
724 /* Disable writeback to avoid unnecessary bus master transfer */
725 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
726 RADEON_RB_NO_UPDATE);
727 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
728 }
729 }
730
731 /* Enable or disable IGP GART on the chip */
732 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
733 {
734 u32 temp;
735
736 if (on) {
737 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
738 dev_priv->gart_vm_start,
739 (long)dev_priv->gart_info.bus_addr,
740 dev_priv->gart_size);
741
742 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
743 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
744 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
745 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
746 RS690_BLOCK_GFX_D3_EN));
747 else
748 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
749
750 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
751 RS480_VA_SIZE_32MB));
752
753 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
754 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
755 RS480_TLB_ENABLE |
756 RS480_GTW_LAC_EN |
757 RS480_1LEVEL_GART));
758
759 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
760 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
761 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
762
763 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
764 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
765 RS480_REQ_TYPE_SNOOP_DIS));
766
767 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
768
769 dev_priv->gart_size = 32*1024*1024;
770 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
771 0xffff0000) | (dev_priv->gart_vm_start >> 16));
772
773 radeon_write_agp_location(dev_priv, temp);
774
775 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
776 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
777 RS480_VA_SIZE_32MB));
778
779 do {
780 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
781 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
782 break;
783 DRM_UDELAY(1);
784 } while (1);
785
786 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
787 RS480_GART_CACHE_INVALIDATE);
788
789 do {
790 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
791 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
792 break;
793 DRM_UDELAY(1);
794 } while (1);
795
796 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
797 } else {
798 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
799 }
800 }
801
802 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
803 {
804 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
805 if (on) {
806
807 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
808 dev_priv->gart_vm_start,
809 (long)dev_priv->gart_info.bus_addr,
810 dev_priv->gart_size);
811 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
812 dev_priv->gart_vm_start);
813 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
814 dev_priv->gart_info.bus_addr);
815 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
816 dev_priv->gart_vm_start);
817 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
818 dev_priv->gart_vm_start +
819 dev_priv->gart_size - 1);
820
821 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
822
823 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
824 RADEON_PCIE_TX_GART_EN);
825 } else {
826 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
827 tmp & ~RADEON_PCIE_TX_GART_EN);
828 }
829 }
830
831 /* Enable or disable PCI GART on the chip */
832 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
833 {
834 u32 tmp;
835
836 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
837 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
838 (dev_priv->flags & RADEON_IS_IGPGART)) {
839 radeon_set_igpgart(dev_priv, on);
840 return;
841 }
842
843 if (dev_priv->flags & RADEON_IS_PCIE) {
844 radeon_set_pciegart(dev_priv, on);
845 return;
846 }
847
848 tmp = RADEON_READ(RADEON_AIC_CNTL);
849
850 if (on) {
851 RADEON_WRITE(RADEON_AIC_CNTL,
852 tmp | RADEON_PCIGART_TRANSLATE_EN);
853
854 /* set PCI GART page-table base address
855 */
856 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
857
858 /* set address range for PCI address translate
859 */
860 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
861 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
862 + dev_priv->gart_size - 1);
863
864 /* Turn off AGP aperture -- is this required for PCI GART?
865 */
866 radeon_write_agp_location(dev_priv, 0xffffffc0);
867 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
868 } else {
869 RADEON_WRITE(RADEON_AIC_CNTL,
870 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
871 }
872 }
873
874 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
875 struct drm_file *file_priv)
876 {
877 drm_radeon_private_t *dev_priv = dev->dev_private;
878 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
879
880 DRM_DEBUG("\n");
881
882 /* if we require new memory map but we don't have it fail */
883 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
884 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
885 radeon_do_cleanup_cp(dev);
886 return -EINVAL;
887 }
888
889 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
890 DRM_DEBUG("Forcing AGP card to PCI mode\n");
891 dev_priv->flags &= ~RADEON_IS_AGP;
892 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
893 && !init->is_pci) {
894 DRM_DEBUG("Restoring AGP flag\n");
895 dev_priv->flags |= RADEON_IS_AGP;
896 }
897
898 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
899 DRM_ERROR("PCI GART memory not allocated!\n");
900 radeon_do_cleanup_cp(dev);
901 return -EINVAL;
902 }
903
904 dev_priv->usec_timeout = init->usec_timeout;
905 if (dev_priv->usec_timeout < 1 ||
906 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
907 DRM_DEBUG("TIMEOUT problem!\n");
908 radeon_do_cleanup_cp(dev);
909 return -EINVAL;
910 }
911
912 /* Enable vblank on CRTC1 for older X servers
913 */
914 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
915
916 switch(init->func) {
917 case RADEON_INIT_R200_CP:
918 dev_priv->microcode_version = UCODE_R200;
919 break;
920 case RADEON_INIT_R300_CP:
921 dev_priv->microcode_version = UCODE_R300;
922 break;
923 default:
924 dev_priv->microcode_version = UCODE_R100;
925 }
926
927 dev_priv->do_boxes = 0;
928 dev_priv->cp_mode = init->cp_mode;
929
930 /* We don't support anything other than bus-mastering ring mode,
931 * but the ring can be in either AGP or PCI space for the ring
932 * read pointer.
933 */
934 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
935 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
936 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
937 radeon_do_cleanup_cp(dev);
938 return -EINVAL;
939 }
940
941 switch (init->fb_bpp) {
942 case 16:
943 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
944 break;
945 case 32:
946 default:
947 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
948 break;
949 }
950 dev_priv->front_offset = init->front_offset;
951 dev_priv->front_pitch = init->front_pitch;
952 dev_priv->back_offset = init->back_offset;
953 dev_priv->back_pitch = init->back_pitch;
954
955 switch (init->depth_bpp) {
956 case 16:
957 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
958 break;
959 case 32:
960 default:
961 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
962 break;
963 }
964 dev_priv->depth_offset = init->depth_offset;
965 dev_priv->depth_pitch = init->depth_pitch;
966
967 /* Hardware state for depth clears. Remove this if/when we no
968 * longer clear the depth buffer with a 3D rectangle. Hard-code
969 * all values to prevent unwanted 3D state from slipping through
970 * and screwing with the clear operation.
971 */
972 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
973 (dev_priv->color_fmt << 10) |
974 (dev_priv->microcode_version ==
975 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
976
977 dev_priv->depth_clear.rb3d_zstencilcntl =
978 (dev_priv->depth_fmt |
979 RADEON_Z_TEST_ALWAYS |
980 RADEON_STENCIL_TEST_ALWAYS |
981 RADEON_STENCIL_S_FAIL_REPLACE |
982 RADEON_STENCIL_ZPASS_REPLACE |
983 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
984
985 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
986 RADEON_BFACE_SOLID |
987 RADEON_FFACE_SOLID |
988 RADEON_FLAT_SHADE_VTX_LAST |
989 RADEON_DIFFUSE_SHADE_FLAT |
990 RADEON_ALPHA_SHADE_FLAT |
991 RADEON_SPECULAR_SHADE_FLAT |
992 RADEON_FOG_SHADE_FLAT |
993 RADEON_VTX_PIX_CENTER_OGL |
994 RADEON_ROUND_MODE_TRUNC |
995 RADEON_ROUND_PREC_8TH_PIX);
996
997
998 dev_priv->ring_offset = init->ring_offset;
999 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1000 dev_priv->buffers_offset = init->buffers_offset;
1001 dev_priv->gart_textures_offset = init->gart_textures_offset;
1002
1003 master_priv->sarea = drm_getsarea(dev);
1004 if (!master_priv->sarea) {
1005 DRM_ERROR("could not find sarea!\n");
1006 radeon_do_cleanup_cp(dev);
1007 return -EINVAL;
1008 }
1009
1010 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1011 if (!dev_priv->cp_ring) {
1012 DRM_ERROR("could not find cp ring region!\n");
1013 radeon_do_cleanup_cp(dev);
1014 return -EINVAL;
1015 }
1016 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1017 if (!dev_priv->ring_rptr) {
1018 DRM_ERROR("could not find ring read pointer!\n");
1019 radeon_do_cleanup_cp(dev);
1020 return -EINVAL;
1021 }
1022 dev->agp_buffer_token = init->buffers_offset;
1023 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1024 if (!dev->agp_buffer_map) {
1025 DRM_ERROR("could not find dma buffer region!\n");
1026 radeon_do_cleanup_cp(dev);
1027 return -EINVAL;
1028 }
1029
1030 if (init->gart_textures_offset) {
1031 dev_priv->gart_textures =
1032 drm_core_findmap(dev, init->gart_textures_offset);
1033 if (!dev_priv->gart_textures) {
1034 DRM_ERROR("could not find GART texture region!\n");
1035 radeon_do_cleanup_cp(dev);
1036 return -EINVAL;
1037 }
1038 }
1039
1040 #if __OS_HAS_AGP
1041 if (dev_priv->flags & RADEON_IS_AGP) {
1042 drm_core_ioremap(dev_priv->cp_ring, dev);
1043 drm_core_ioremap(dev_priv->ring_rptr, dev);
1044 drm_core_ioremap(dev->agp_buffer_map, dev);
1045 if (!dev_priv->cp_ring->handle ||
1046 !dev_priv->ring_rptr->handle ||
1047 !dev->agp_buffer_map->handle) {
1048 DRM_ERROR("could not find ioremap agp regions!\n");
1049 radeon_do_cleanup_cp(dev);
1050 return -EINVAL;
1051 }
1052 } else
1053 #endif
1054 {
1055 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1056 dev_priv->ring_rptr->handle =
1057 (void *)dev_priv->ring_rptr->offset;
1058 dev->agp_buffer_map->handle =
1059 (void *)dev->agp_buffer_map->offset;
1060
1061 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1062 dev_priv->cp_ring->handle);
1063 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1064 dev_priv->ring_rptr->handle);
1065 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1066 dev->agp_buffer_map->handle);
1067 }
1068
1069 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1070 dev_priv->fb_size =
1071 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1072 - dev_priv->fb_location;
1073
1074 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1075 ((dev_priv->front_offset
1076 + dev_priv->fb_location) >> 10));
1077
1078 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1079 ((dev_priv->back_offset
1080 + dev_priv->fb_location) >> 10));
1081
1082 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1083 ((dev_priv->depth_offset
1084 + dev_priv->fb_location) >> 10));
1085
1086 dev_priv->gart_size = init->gart_size;
1087
1088 /* New let's set the memory map ... */
1089 if (dev_priv->new_memmap) {
1090 u32 base = 0;
1091
1092 DRM_INFO("Setting GART location based on new memory map\n");
1093
1094 /* If using AGP, try to locate the AGP aperture at the same
1095 * location in the card and on the bus, though we have to
1096 * align it down.
1097 */
1098 #if __OS_HAS_AGP
1099 if (dev_priv->flags & RADEON_IS_AGP) {
1100 base = dev->agp->base;
1101 /* Check if valid */
1102 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1103 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1104 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1105 dev->agp->base);
1106 base = 0;
1107 }
1108 }
1109 #endif
1110 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1111 if (base == 0) {
1112 base = dev_priv->fb_location + dev_priv->fb_size;
1113 if (base < dev_priv->fb_location ||
1114 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1115 base = dev_priv->fb_location
1116 - dev_priv->gart_size;
1117 }
1118 dev_priv->gart_vm_start = base & 0xffc00000u;
1119 if (dev_priv->gart_vm_start != base)
1120 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1121 base, dev_priv->gart_vm_start);
1122 } else {
1123 DRM_INFO("Setting GART location based on old memory map\n");
1124 dev_priv->gart_vm_start = dev_priv->fb_location +
1125 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1126 }
1127
1128 #if __OS_HAS_AGP
1129 if (dev_priv->flags & RADEON_IS_AGP)
1130 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1131 - dev->agp->base
1132 + dev_priv->gart_vm_start);
1133 else
1134 #endif
1135 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1136 - (unsigned long)dev->sg->virtual
1137 + dev_priv->gart_vm_start);
1138
1139 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1140 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1141 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1142 dev_priv->gart_buffers_offset);
1143
1144 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1145 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1146 + init->ring_size / sizeof(u32));
1147 dev_priv->ring.size = init->ring_size;
1148 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1149
1150 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1151 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1152
1153 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1154 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1155 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1156
1157 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1158
1159 #if __OS_HAS_AGP
1160 if (dev_priv->flags & RADEON_IS_AGP) {
1161 /* Turn off PCI GART */
1162 radeon_set_pcigart(dev_priv, 0);
1163 } else
1164 #endif
1165 {
1166 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1167 /* if we have an offset set from userspace */
1168 if (dev_priv->pcigart_offset_set) {
1169 dev_priv->gart_info.bus_addr =
1170 dev_priv->pcigart_offset + dev_priv->fb_location;
1171 dev_priv->gart_info.mapping.offset =
1172 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1173 dev_priv->gart_info.mapping.size =
1174 dev_priv->gart_info.table_size;
1175
1176 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1177 dev_priv->gart_info.addr =
1178 dev_priv->gart_info.mapping.handle;
1179
1180 if (dev_priv->flags & RADEON_IS_PCIE)
1181 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1182 else
1183 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1184 dev_priv->gart_info.gart_table_location =
1185 DRM_ATI_GART_FB;
1186
1187 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1188 dev_priv->gart_info.addr,
1189 dev_priv->pcigart_offset);
1190 } else {
1191 if (dev_priv->flags & RADEON_IS_IGPGART)
1192 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1193 else
1194 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1195 dev_priv->gart_info.gart_table_location =
1196 DRM_ATI_GART_MAIN;
1197 dev_priv->gart_info.addr = NULL;
1198 dev_priv->gart_info.bus_addr = 0;
1199 if (dev_priv->flags & RADEON_IS_PCIE) {
1200 DRM_ERROR
1201 ("Cannot use PCI Express without GART in FB memory\n");
1202 radeon_do_cleanup_cp(dev);
1203 return -EINVAL;
1204 }
1205 }
1206
1207 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1208 DRM_ERROR("failed to init PCI GART!\n");
1209 radeon_do_cleanup_cp(dev);
1210 return -ENOMEM;
1211 }
1212
1213 /* Turn on PCI GART */
1214 radeon_set_pcigart(dev_priv, 1);
1215 }
1216
1217 radeon_cp_load_microcode(dev_priv);
1218 radeon_cp_init_ring_buffer(dev, dev_priv);
1219
1220 dev_priv->last_buf = 0;
1221
1222 radeon_do_engine_reset(dev);
1223 radeon_test_writeback(dev_priv);
1224
1225 return 0;
1226 }
1227
1228 static int radeon_do_cleanup_cp(struct drm_device * dev)
1229 {
1230 drm_radeon_private_t *dev_priv = dev->dev_private;
1231 DRM_DEBUG("\n");
1232
1233 /* Make sure interrupts are disabled here because the uninstall ioctl
1234 * may not have been called from userspace and after dev_private
1235 * is freed, it's too late.
1236 */
1237 if (dev->irq_enabled)
1238 drm_irq_uninstall(dev);
1239
1240 #if __OS_HAS_AGP
1241 if (dev_priv->flags & RADEON_IS_AGP) {
1242 if (dev_priv->cp_ring != NULL) {
1243 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1244 dev_priv->cp_ring = NULL;
1245 }
1246 if (dev_priv->ring_rptr != NULL) {
1247 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1248 dev_priv->ring_rptr = NULL;
1249 }
1250 if (dev->agp_buffer_map != NULL) {
1251 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1252 dev->agp_buffer_map = NULL;
1253 }
1254 } else
1255 #endif
1256 {
1257
1258 if (dev_priv->gart_info.bus_addr) {
1259 /* Turn off PCI GART */
1260 radeon_set_pcigart(dev_priv, 0);
1261 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1262 DRM_ERROR("failed to cleanup PCI GART!\n");
1263 }
1264
1265 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1266 {
1267 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1268 dev_priv->gart_info.addr = 0;
1269 }
1270 }
1271 /* only clear to the start of flags */
1272 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1273
1274 return 0;
1275 }
1276
1277 /* This code will reinit the Radeon CP hardware after a resume from disc.
1278 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1279 * here we make sure that all Radeon hardware initialisation is re-done without
1280 * affecting running applications.
1281 *
1282 * Charl P. Botha <http://cpbotha.net>
1283 */
1284 static int radeon_do_resume_cp(struct drm_device * dev)
1285 {
1286 drm_radeon_private_t *dev_priv = dev->dev_private;
1287
1288 if (!dev_priv) {
1289 DRM_ERROR("Called with no initialization\n");
1290 return -EINVAL;
1291 }
1292
1293 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1294
1295 #if __OS_HAS_AGP
1296 if (dev_priv->flags & RADEON_IS_AGP) {
1297 /* Turn off PCI GART */
1298 radeon_set_pcigart(dev_priv, 0);
1299 } else
1300 #endif
1301 {
1302 /* Turn on PCI GART */
1303 radeon_set_pcigart(dev_priv, 1);
1304 }
1305
1306 radeon_cp_load_microcode(dev_priv);
1307 radeon_cp_init_ring_buffer(dev, dev_priv);
1308
1309 radeon_do_engine_reset(dev);
1310 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1311
1312 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1313
1314 return 0;
1315 }
1316
1317 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1318 {
1319 drm_radeon_init_t *init = data;
1320
1321 LOCK_TEST_WITH_RETURN(dev, file_priv);
1322
1323 if (init->func == RADEON_INIT_R300_CP)
1324 r300_init_reg_flags(dev);
1325
1326 switch (init->func) {
1327 case RADEON_INIT_CP:
1328 case RADEON_INIT_R200_CP:
1329 case RADEON_INIT_R300_CP:
1330 return radeon_do_init_cp(dev, init, file_priv);
1331 case RADEON_CLEANUP_CP:
1332 return radeon_do_cleanup_cp(dev);
1333 }
1334
1335 return -EINVAL;
1336 }
1337
1338 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1339 {
1340 drm_radeon_private_t *dev_priv = dev->dev_private;
1341 DRM_DEBUG("\n");
1342
1343 LOCK_TEST_WITH_RETURN(dev, file_priv);
1344
1345 if (dev_priv->cp_running) {
1346 DRM_DEBUG("while CP running\n");
1347 return 0;
1348 }
1349 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1350 DRM_DEBUG("called with bogus CP mode (%d)\n",
1351 dev_priv->cp_mode);
1352 return 0;
1353 }
1354
1355 radeon_do_cp_start(dev_priv);
1356
1357 return 0;
1358 }
1359
1360 /* Stop the CP. The engine must have been idled before calling this
1361 * routine.
1362 */
1363 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1364 {
1365 drm_radeon_private_t *dev_priv = dev->dev_private;
1366 drm_radeon_cp_stop_t *stop = data;
1367 int ret;
1368 DRM_DEBUG("\n");
1369
1370 LOCK_TEST_WITH_RETURN(dev, file_priv);
1371
1372 if (!dev_priv->cp_running)
1373 return 0;
1374
1375 /* Flush any pending CP commands. This ensures any outstanding
1376 * commands are exectuted by the engine before we turn it off.
1377 */
1378 if (stop->flush) {
1379 radeon_do_cp_flush(dev_priv);
1380 }
1381
1382 /* If we fail to make the engine go idle, we return an error
1383 * code so that the DRM ioctl wrapper can try again.
1384 */
1385 if (stop->idle) {
1386 ret = radeon_do_cp_idle(dev_priv);
1387 if (ret)
1388 return ret;
1389 }
1390
1391 /* Finally, we can turn off the CP. If the engine isn't idle,
1392 * we will get some dropped triangles as they won't be fully
1393 * rendered before the CP is shut down.
1394 */
1395 radeon_do_cp_stop(dev_priv);
1396
1397 /* Reset the engine */
1398 radeon_do_engine_reset(dev);
1399
1400 return 0;
1401 }
1402
1403 void radeon_do_release(struct drm_device * dev)
1404 {
1405 drm_radeon_private_t *dev_priv = dev->dev_private;
1406 int i, ret;
1407
1408 if (dev_priv) {
1409 if (dev_priv->cp_running) {
1410 /* Stop the cp */
1411 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1412 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1413 #ifdef __linux__
1414 schedule();
1415 #else
1416 tsleep(&ret, PZERO, "rdnrel", 1);
1417 #endif
1418 }
1419 radeon_do_cp_stop(dev_priv);
1420 radeon_do_engine_reset(dev);
1421 }
1422
1423 /* Disable *all* interrupts */
1424 if (dev_priv->mmio) /* remove this after permanent addmaps */
1425 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1426
1427 if (dev_priv->mmio) { /* remove all surfaces */
1428 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1429 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1430 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1431 16 * i, 0);
1432 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1433 16 * i, 0);
1434 }
1435 }
1436
1437 /* Free memory heap structures */
1438 radeon_mem_takedown(&(dev_priv->gart_heap));
1439 radeon_mem_takedown(&(dev_priv->fb_heap));
1440
1441 /* deallocate kernel resources */
1442 radeon_do_cleanup_cp(dev);
1443 }
1444 }
1445
1446 /* Just reset the CP ring. Called as part of an X Server engine reset.
1447 */
1448 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1449 {
1450 drm_radeon_private_t *dev_priv = dev->dev_private;
1451 DRM_DEBUG("\n");
1452
1453 LOCK_TEST_WITH_RETURN(dev, file_priv);
1454
1455 if (!dev_priv) {
1456 DRM_DEBUG("called before init done\n");
1457 return -EINVAL;
1458 }
1459
1460 radeon_do_cp_reset(dev_priv);
1461
1462 /* The CP is no longer running after an engine reset */
1463 dev_priv->cp_running = 0;
1464
1465 return 0;
1466 }
1467
1468 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1469 {
1470 drm_radeon_private_t *dev_priv = dev->dev_private;
1471 DRM_DEBUG("\n");
1472
1473 LOCK_TEST_WITH_RETURN(dev, file_priv);
1474
1475 return radeon_do_cp_idle(dev_priv);
1476 }
1477
1478 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1479 */
1480 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1481 {
1482
1483 return radeon_do_resume_cp(dev);
1484 }
1485
1486 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1487 {
1488 DRM_DEBUG("\n");
1489
1490 LOCK_TEST_WITH_RETURN(dev, file_priv);
1491
1492 return radeon_do_engine_reset(dev);
1493 }
1494
1495 /* ================================================================
1496 * Fullscreen mode
1497 */
1498
1499 /* KW: Deprecated to say the least:
1500 */
1501 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1502 {
1503 return 0;
1504 }
1505
1506 /* ================================================================
1507 * Freelist management
1508 */
1509
1510 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1511 * bufs until freelist code is used. Note this hides a problem with
1512 * the scratch register * (used to keep track of last buffer
1513 * completed) being written to before * the last buffer has actually
1514 * completed rendering.
1515 *
1516 * KW: It's also a good way to find free buffers quickly.
1517 *
1518 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1519 * sleep. However, bugs in older versions of radeon_accel.c mean that
1520 * we essentially have to do this, else old clients will break.
1521 *
1522 * However, it does leave open a potential deadlock where all the
1523 * buffers are held by other clients, which can't release them because
1524 * they can't get the lock.
1525 */
1526
1527 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1528 {
1529 struct drm_device_dma *dma = dev->dma;
1530 drm_radeon_private_t *dev_priv = dev->dev_private;
1531 drm_radeon_buf_priv_t *buf_priv;
1532 struct drm_buf *buf;
1533 int i, t;
1534 int start;
1535
1536 if (++dev_priv->last_buf >= dma->buf_count)
1537 dev_priv->last_buf = 0;
1538
1539 start = dev_priv->last_buf;
1540
1541 for (t = 0; t < dev_priv->usec_timeout; t++) {
1542 u32 done_age = GET_SCRATCH(1);
1543 DRM_DEBUG("done_age = %d\n", done_age);
1544 for (i = start; i < dma->buf_count; i++) {
1545 buf = dma->buflist[i];
1546 buf_priv = buf->dev_private;
1547 if (buf->file_priv == NULL || (buf->pending &&
1548 buf_priv->age <=
1549 done_age)) {
1550 dev_priv->stats.requested_bufs++;
1551 buf->pending = 0;
1552 return buf;
1553 }
1554 start = 0;
1555 }
1556
1557 if (t) {
1558 DRM_UDELAY(1);
1559 dev_priv->stats.freelist_loops++;
1560 }
1561 }
1562
1563 DRM_DEBUG("returning NULL!\n");
1564 return NULL;
1565 }
1566
1567 #if 0
1568 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1569 {
1570 struct drm_device_dma *dma = dev->dma;
1571 drm_radeon_private_t *dev_priv = dev->dev_private;
1572 drm_radeon_buf_priv_t *buf_priv;
1573 struct drm_buf *buf;
1574 int i, t;
1575 int start;
1576 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1577
1578 if (++dev_priv->last_buf >= dma->buf_count)
1579 dev_priv->last_buf = 0;
1580
1581 start = dev_priv->last_buf;
1582 dev_priv->stats.freelist_loops++;
1583
1584 for (t = 0; t < 2; t++) {
1585 for (i = start; i < dma->buf_count; i++) {
1586 buf = dma->buflist[i];
1587 buf_priv = buf->dev_private;
1588 if (buf->file_priv == 0 || (buf->pending &&
1589 buf_priv->age <=
1590 done_age)) {
1591 dev_priv->stats.requested_bufs++;
1592 buf->pending = 0;
1593 return buf;
1594 }
1595 }
1596 start = 0;
1597 }
1598
1599 return NULL;
1600 }
1601 #endif
1602
1603 void radeon_freelist_reset(struct drm_device * dev)
1604 {
1605 struct drm_device_dma *dma = dev->dma;
1606 drm_radeon_private_t *dev_priv = dev->dev_private;
1607 int i;
1608
1609 dev_priv->last_buf = 0;
1610 for (i = 0; i < dma->buf_count; i++) {
1611 struct drm_buf *buf = dma->buflist[i];
1612 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1613 buf_priv->age = 0;
1614 }
1615 }
1616
1617 /* ================================================================
1618 * CP command submission
1619 */
1620
1621 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1622 {
1623 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1624 int i;
1625 u32 last_head = GET_RING_HEAD(dev_priv);
1626
1627 for (i = 0; i < dev_priv->usec_timeout; i++) {
1628 u32 head = GET_RING_HEAD(dev_priv);
1629
1630 ring->space = (head - ring->tail) * sizeof(u32);
1631 if (ring->space <= 0)
1632 ring->space += ring->size;
1633 if (ring->space > n)
1634 return 0;
1635
1636 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1637
1638 if (head != last_head)
1639 i = 0;
1640 last_head = head;
1641
1642 DRM_UDELAY(1);
1643 }
1644
1645 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1646 #if RADEON_FIFO_DEBUG
1647 radeon_status(dev_priv);
1648 DRM_ERROR("failed!\n");
1649 #endif
1650 return -EBUSY;
1651 }
1652
1653 static int radeon_cp_get_buffers(struct drm_device *dev,
1654 struct drm_file *file_priv,
1655 struct drm_dma * d)
1656 {
1657 int i;
1658 struct drm_buf *buf;
1659
1660 for (i = d->granted_count; i < d->request_count; i++) {
1661 buf = radeon_freelist_get(dev);
1662 if (!buf)
1663 return -EBUSY; /* NOTE: broken client */
1664
1665 buf->file_priv = file_priv;
1666
1667 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1668 sizeof(buf->idx)))
1669 return -EFAULT;
1670 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1671 sizeof(buf->total)))
1672 return -EFAULT;
1673
1674 d->granted_count++;
1675 }
1676 return 0;
1677 }
1678
1679 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1680 {
1681 struct drm_device_dma *dma = dev->dma;
1682 int ret = 0;
1683 struct drm_dma *d = data;
1684
1685 LOCK_TEST_WITH_RETURN(dev, file_priv);
1686
1687 /* Please don't send us buffers.
1688 */
1689 if (d->send_count != 0) {
1690 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1691 DRM_CURRENTPID, d->send_count);
1692 return -EINVAL;
1693 }
1694
1695 /* We'll send you buffers.
1696 */
1697 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1698 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1699 DRM_CURRENTPID, d->request_count, dma->buf_count);
1700 return -EINVAL;
1701 }
1702
1703 d->granted_count = 0;
1704
1705 if (d->request_count) {
1706 ret = radeon_cp_get_buffers(dev, file_priv, d);
1707 }
1708
1709 return ret;
1710 }
1711
1712 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1713 {
1714 drm_radeon_private_t *dev_priv;
1715 int ret = 0;
1716
1717 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1718 if (dev_priv == NULL)
1719 return -ENOMEM;
1720
1721 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1722 dev->dev_private = (void *)dev_priv;
1723 dev_priv->flags = flags;
1724
1725 switch (flags & RADEON_FAMILY_MASK) {
1726 case CHIP_R100:
1727 case CHIP_RV200:
1728 case CHIP_R200:
1729 case CHIP_R300:
1730 case CHIP_R350:
1731 case CHIP_R420:
1732 case CHIP_R423:
1733 case CHIP_RV410:
1734 case CHIP_RV515:
1735 case CHIP_R520:
1736 case CHIP_RV570:
1737 case CHIP_R580:
1738 dev_priv->flags |= RADEON_HAS_HIERZ;
1739 break;
1740 default:
1741 /* all other chips have no hierarchical z buffer */
1742 break;
1743 }
1744
1745 if (drm_device_is_agp(dev))
1746 dev_priv->flags |= RADEON_IS_AGP;
1747 else if (drm_device_is_pcie(dev))
1748 dev_priv->flags |= RADEON_IS_PCIE;
1749 else
1750 dev_priv->flags |= RADEON_IS_PCI;
1751
1752 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1753 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1754 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1755 if (ret != 0)
1756 return ret;
1757
1758 ret = drm_vblank_init(dev, 2);
1759 if (ret) {
1760 radeon_driver_unload(dev);
1761 return ret;
1762 }
1763
1764 DRM_DEBUG("%s card detected\n",
1765 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1766 return ret;
1767 }
1768
1769 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1770 {
1771 struct drm_radeon_master_private *master_priv;
1772 unsigned long sareapage;
1773 int ret;
1774
1775 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1776 if (!master_priv)
1777 return -ENOMEM;
1778
1779 /* prebuild the SAREA */
1780 sareapage = max(SAREA_MAX, PAGE_SIZE);
1781 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1782 &master_priv->sarea);
1783 if (ret) {
1784 DRM_ERROR("SAREA setup failed\n");
1785 return ret;
1786 }
1787 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1788 master_priv->sarea_priv->pfCurrentPage = 0;
1789
1790 master->driver_priv = master_priv;
1791 return 0;
1792 }
1793
1794 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1795 {
1796 struct drm_radeon_master_private *master_priv = master->driver_priv;
1797
1798 if (!master_priv)
1799 return;
1800
1801 if (master_priv->sarea_priv &&
1802 master_priv->sarea_priv->pfCurrentPage != 0)
1803 radeon_cp_dispatch_flip(dev, master);
1804
1805 master_priv->sarea_priv = NULL;
1806 if (master_priv->sarea)
1807 drm_rmmap(dev, master_priv->sarea);
1808
1809 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1810
1811 master->driver_priv = NULL;
1812 }
1813
1814 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1815 * have to find them.
1816 */
1817 int radeon_driver_firstopen(struct drm_device *dev)
1818 {
1819 int ret;
1820 drm_local_map_t *map;
1821 drm_radeon_private_t *dev_priv = dev->dev_private;
1822
1823 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1824
1825 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1826 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1827 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1828 _DRM_WRITE_COMBINING, &map);
1829 if (ret != 0)
1830 return ret;
1831
1832 return 0;
1833 }
1834
1835 int radeon_driver_unload(struct drm_device *dev)
1836 {
1837 drm_radeon_private_t *dev_priv = dev->dev_private;
1838
1839 DRM_DEBUG("\n");
1840
1841 drm_rmmap(dev, dev_priv->mmio);
1842
1843 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1844
1845 dev->dev_private = NULL;
1846 return 0;
1847 }
linux kernel for loongson