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drm: move to kref per-master structures.
[linux-2.6/linux-loongson.git] / drivers / gpu / drm / i915 / i915_dma.c
blobdacdf3c577cbf79fe429111cad29d96c3af63233
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
38 */
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
40 {
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
43 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
44 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
46 u32 acthd;
47 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
48 int i;
49
50 for (i = 0; i < 100000; i++) {
51 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
52 acthd = I915_READ(acthd_reg);
53 ring->space = ring->head - (ring->tail + 8);
54 if (ring->space < 0)
55 ring->space += ring->Size;
56 if (ring->space >= n)
57 return 0;
58
59 if (master_priv->sarea_priv)
60 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
61
62 if (ring->head != last_head)
63 i = 0;
64 if (acthd != last_acthd)
65 i = 0;
66
67 last_head = ring->head;
68 last_acthd = acthd;
69 msleep_interruptible(10);
70
71 }
72
73 return -EBUSY;
74 }
75
76 /**
77 * Sets up the hardware status page for devices that need a physical address
78 * in the register.
79 */
80 static int i915_init_phys_hws(struct drm_device *dev)
81 {
82 drm_i915_private_t *dev_priv = dev->dev_private;
83 /* Program Hardware Status Page */
84 dev_priv->status_page_dmah =
85 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
86
87 if (!dev_priv->status_page_dmah) {
88 DRM_ERROR("Can not allocate hardware status page\n");
89 return -ENOMEM;
90 }
91 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
92 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
93
94 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
95
96 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
97 DRM_DEBUG("Enabled hardware status page\n");
98 return 0;
99 }
100
101 /**
102 * Frees the hardware status page, whether it's a physical address or a virtual
103 * address set up by the X Server.
104 */
105 static void i915_free_hws(struct drm_device *dev)
106 {
107 drm_i915_private_t *dev_priv = dev->dev_private;
108 if (dev_priv->status_page_dmah) {
109 drm_pci_free(dev, dev_priv->status_page_dmah);
110 dev_priv->status_page_dmah = NULL;
111 }
112
113 if (dev_priv->status_gfx_addr) {
114 dev_priv->status_gfx_addr = 0;
115 drm_core_ioremapfree(&dev_priv->hws_map, dev);
116 }
117
118 /* Need to rewrite hardware status page */
119 I915_WRITE(HWS_PGA, 0x1ffff000);
120 }
121
122 void i915_kernel_lost_context(struct drm_device * dev)
123 {
124 drm_i915_private_t *dev_priv = dev->dev_private;
125 struct drm_i915_master_private *master_priv;
126 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
127
128 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
129 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
130 ring->space = ring->head - (ring->tail + 8);
131 if (ring->space < 0)
132 ring->space += ring->Size;
133
134 if (!dev->primary->master)
135 return;
136
137 master_priv = dev->primary->master->driver_priv;
138 if (ring->head == ring->tail && master_priv->sarea_priv)
139 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
140 }
141
142 static int i915_dma_cleanup(struct drm_device * dev)
143 {
144 drm_i915_private_t *dev_priv = dev->dev_private;
145 /* Make sure interrupts are disabled here because the uninstall ioctl
146 * may not have been called from userspace and after dev_private
147 * is freed, it's too late.
148 */
149 if (dev->irq_enabled)
150 drm_irq_uninstall(dev);
151
152 if (dev_priv->ring.virtual_start) {
153 drm_core_ioremapfree(&dev_priv->ring.map, dev);
154 dev_priv->ring.virtual_start = NULL;
155 dev_priv->ring.map.handle = NULL;
156 dev_priv->ring.map.size = 0;
157 }
158
159 /* Clear the HWS virtual address at teardown */
160 if (I915_NEED_GFX_HWS(dev))
161 i915_free_hws(dev);
162
163 return 0;
164 }
165
166 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
167 {
168 drm_i915_private_t *dev_priv = dev->dev_private;
169 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
170
171 if (init->ring_size != 0) {
172 if (dev_priv->ring.ring_obj != NULL) {
173 i915_dma_cleanup(dev);
174 DRM_ERROR("Client tried to initialize ringbuffer in "
175 "GEM mode\n");
176 return -EINVAL;
177 }
178
179 dev_priv->ring.Size = init->ring_size;
180 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
181
182 dev_priv->ring.map.offset = init->ring_start;
183 dev_priv->ring.map.size = init->ring_size;
184 dev_priv->ring.map.type = 0;
185 dev_priv->ring.map.flags = 0;
186 dev_priv->ring.map.mtrr = 0;
187
188 drm_core_ioremap(&dev_priv->ring.map, dev);
189
190 if (dev_priv->ring.map.handle == NULL) {
191 i915_dma_cleanup(dev);
192 DRM_ERROR("can not ioremap virtual address for"
193 " ring buffer\n");
194 return -ENOMEM;
195 }
196 }
197
198 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
199
200 dev_priv->cpp = init->cpp;
201 dev_priv->back_offset = init->back_offset;
202 dev_priv->front_offset = init->front_offset;
203 dev_priv->current_page = 0;
204 if (master_priv->sarea_priv)
205 master_priv->sarea_priv->pf_current_page = 0;
206
207 /* Allow hardware batchbuffers unless told otherwise.
208 */
209 dev_priv->allow_batchbuffer = 1;
210
211 return 0;
212 }
213
214 static int i915_dma_resume(struct drm_device * dev)
215 {
216 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
217
218 DRM_DEBUG("%s\n", __func__);
219
220 if (dev_priv->ring.map.handle == NULL) {
221 DRM_ERROR("can not ioremap virtual address for"
222 " ring buffer\n");
223 return -ENOMEM;
224 }
225
226 /* Program Hardware Status Page */
227 if (!dev_priv->hw_status_page) {
228 DRM_ERROR("Can not find hardware status page\n");
229 return -EINVAL;
230 }
231 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
232
233 if (dev_priv->status_gfx_addr != 0)
234 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
235 else
236 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
237 DRM_DEBUG("Enabled hardware status page\n");
238
239 return 0;
240 }
241
242 static int i915_dma_init(struct drm_device *dev, void *data,
243 struct drm_file *file_priv)
244 {
245 drm_i915_init_t *init = data;
246 int retcode = 0;
247
248 switch (init->func) {
249 case I915_INIT_DMA:
250 retcode = i915_initialize(dev, init);
251 break;
252 case I915_CLEANUP_DMA:
253 retcode = i915_dma_cleanup(dev);
254 break;
255 case I915_RESUME_DMA:
256 retcode = i915_dma_resume(dev);
257 break;
258 default:
259 retcode = -EINVAL;
260 break;
261 }
262
263 return retcode;
264 }
265
266 /* Implement basically the same security restrictions as hardware does
267 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
268 *
269 * Most of the calculations below involve calculating the size of a
270 * particular instruction. It's important to get the size right as
271 * that tells us where the next instruction to check is. Any illegal
272 * instruction detected will be given a size of zero, which is a
273 * signal to abort the rest of the buffer.
274 */
275 static int do_validate_cmd(int cmd)
276 {
277 switch (((cmd >> 29) & 0x7)) {
278 case 0x0:
279 switch ((cmd >> 23) & 0x3f) {
280 case 0x0:
281 return 1; /* MI_NOOP */
282 case 0x4:
283 return 1; /* MI_FLUSH */
284 default:
285 return 0; /* disallow everything else */
286 }
287 break;
288 case 0x1:
289 return 0; /* reserved */
290 case 0x2:
291 return (cmd & 0xff) + 2; /* 2d commands */
292 case 0x3:
293 if (((cmd >> 24) & 0x1f) <= 0x18)
294 return 1;
295
296 switch ((cmd >> 24) & 0x1f) {
297 case 0x1c:
298 return 1;
299 case 0x1d:
300 switch ((cmd >> 16) & 0xff) {
301 case 0x3:
302 return (cmd & 0x1f) + 2;
303 case 0x4:
304 return (cmd & 0xf) + 2;
305 default:
306 return (cmd & 0xffff) + 2;
307 }
308 case 0x1e:
309 if (cmd & (1 << 23))
310 return (cmd & 0xffff) + 1;
311 else
312 return 1;
313 case 0x1f:
314 if ((cmd & (1 << 23)) == 0) /* inline vertices */
315 return (cmd & 0x1ffff) + 2;
316 else if (cmd & (1 << 17)) /* indirect random */
317 if ((cmd & 0xffff) == 0)
318 return 0; /* unknown length, too hard */
319 else
320 return (((cmd & 0xffff) + 1) / 2) + 1;
321 else
322 return 2; /* indirect sequential */
323 default:
324 return 0;
325 }
326 default:
327 return 0;
328 }
329
330 return 0;
331 }
332
333 static int validate_cmd(int cmd)
334 {
335 int ret = do_validate_cmd(cmd);
336
337 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
338
339 return ret;
340 }
341
342 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
343 {
344 drm_i915_private_t *dev_priv = dev->dev_private;
345 int i;
346 RING_LOCALS;
347
348 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
349 return -EINVAL;
350
351 BEGIN_LP_RING((dwords+1)&~1);
352
353 for (i = 0; i < dwords;) {
354 int cmd, sz;
355
356 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
357 return -EINVAL;
358
359 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
360 return -EINVAL;
361
362 OUT_RING(cmd);
363
364 while (++i, --sz) {
365 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
366 sizeof(cmd))) {
367 return -EINVAL;
368 }
369 OUT_RING(cmd);
370 }
371 }
372
373 if (dwords & 1)
374 OUT_RING(0);
375
376 ADVANCE_LP_RING();
377
378 return 0;
379 }
380
381 int
382 i915_emit_box(struct drm_device *dev,
383 struct drm_clip_rect __user *boxes,
384 int i, int DR1, int DR4)
385 {
386 drm_i915_private_t *dev_priv = dev->dev_private;
387 struct drm_clip_rect box;
388 RING_LOCALS;
389
390 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
391 return -EFAULT;
392 }
393
394 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
395 DRM_ERROR("Bad box %d,%d..%d,%d\n",
396 box.x1, box.y1, box.x2, box.y2);
397 return -EINVAL;
398 }
399
400 if (IS_I965G(dev)) {
401 BEGIN_LP_RING(4);
402 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
403 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
404 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
405 OUT_RING(DR4);
406 ADVANCE_LP_RING();
407 } else {
408 BEGIN_LP_RING(6);
409 OUT_RING(GFX_OP_DRAWRECT_INFO);
410 OUT_RING(DR1);
411 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
412 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
413 OUT_RING(DR4);
414 OUT_RING(0);
415 ADVANCE_LP_RING();
416 }
417
418 return 0;
419 }
420
421 /* XXX: Emitting the counter should really be moved to part of the IRQ
422 * emit. For now, do it in both places:
423 */
424
425 static void i915_emit_breadcrumb(struct drm_device *dev)
426 {
427 drm_i915_private_t *dev_priv = dev->dev_private;
428 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
429 RING_LOCALS;
430
431 dev_priv->counter++;
432 if (dev_priv->counter > 0x7FFFFFFFUL)
433 dev_priv->counter = 0;
434 if (master_priv->sarea_priv)
435 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
436
437 BEGIN_LP_RING(4);
438 OUT_RING(MI_STORE_DWORD_INDEX);
439 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
440 OUT_RING(dev_priv->counter);
441 OUT_RING(0);
442 ADVANCE_LP_RING();
443 }
444
445 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
446 drm_i915_cmdbuffer_t * cmd)
447 {
448 int nbox = cmd->num_cliprects;
449 int i = 0, count, ret;
450
451 if (cmd->sz & 0x3) {
452 DRM_ERROR("alignment");
453 return -EINVAL;
454 }
455
456 i915_kernel_lost_context(dev);
457
458 count = nbox ? nbox : 1;
459
460 for (i = 0; i < count; i++) {
461 if (i < nbox) {
462 ret = i915_emit_box(dev, cmd->cliprects, i,
463 cmd->DR1, cmd->DR4);
464 if (ret)
465 return ret;
466 }
467
468 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
469 if (ret)
470 return ret;
471 }
472
473 i915_emit_breadcrumb(dev);
474 return 0;
475 }
476
477 static int i915_dispatch_batchbuffer(struct drm_device * dev,
478 drm_i915_batchbuffer_t * batch)
479 {
480 drm_i915_private_t *dev_priv = dev->dev_private;
481 struct drm_clip_rect __user *boxes = batch->cliprects;
482 int nbox = batch->num_cliprects;
483 int i = 0, count;
484 RING_LOCALS;
485
486 if ((batch->start | batch->used) & 0x7) {
487 DRM_ERROR("alignment");
488 return -EINVAL;
489 }
490
491 i915_kernel_lost_context(dev);
492
493 count = nbox ? nbox : 1;
494
495 for (i = 0; i < count; i++) {
496 if (i < nbox) {
497 int ret = i915_emit_box(dev, boxes, i,
498 batch->DR1, batch->DR4);
499 if (ret)
500 return ret;
501 }
502
503 if (!IS_I830(dev) && !IS_845G(dev)) {
504 BEGIN_LP_RING(2);
505 if (IS_I965G(dev)) {
506 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
507 OUT_RING(batch->start);
508 } else {
509 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
510 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
511 }
512 ADVANCE_LP_RING();
513 } else {
514 BEGIN_LP_RING(4);
515 OUT_RING(MI_BATCH_BUFFER);
516 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
517 OUT_RING(batch->start + batch->used - 4);
518 OUT_RING(0);
519 ADVANCE_LP_RING();
520 }
521 }
522
523 i915_emit_breadcrumb(dev);
524
525 return 0;
526 }
527
528 static int i915_dispatch_flip(struct drm_device * dev)
529 {
530 drm_i915_private_t *dev_priv = dev->dev_private;
531 struct drm_i915_master_private *master_priv =
532 dev->primary->master->driver_priv;
533 RING_LOCALS;
534
535 if (!master_priv->sarea_priv)
536 return -EINVAL;
537
538 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
539 __func__,
540 dev_priv->current_page,
541 master_priv->sarea_priv->pf_current_page);
542
543 i915_kernel_lost_context(dev);
544
545 BEGIN_LP_RING(2);
546 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
547 OUT_RING(0);
548 ADVANCE_LP_RING();
549
550 BEGIN_LP_RING(6);
551 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
552 OUT_RING(0);
553 if (dev_priv->current_page == 0) {
554 OUT_RING(dev_priv->back_offset);
555 dev_priv->current_page = 1;
556 } else {
557 OUT_RING(dev_priv->front_offset);
558 dev_priv->current_page = 0;
559 }
560 OUT_RING(0);
561 ADVANCE_LP_RING();
562
563 BEGIN_LP_RING(2);
564 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
565 OUT_RING(0);
566 ADVANCE_LP_RING();
567
568 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
569
570 BEGIN_LP_RING(4);
571 OUT_RING(MI_STORE_DWORD_INDEX);
572 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
573 OUT_RING(dev_priv->counter);
574 OUT_RING(0);
575 ADVANCE_LP_RING();
576
577 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
578 return 0;
579 }
580
581 static int i915_quiescent(struct drm_device * dev)
582 {
583 drm_i915_private_t *dev_priv = dev->dev_private;
584
585 i915_kernel_lost_context(dev);
586 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
587 }
588
589 static int i915_flush_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *file_priv)
591 {
592 int ret;
593
594 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
595
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_quiescent(dev);
598 mutex_unlock(&dev->struct_mutex);
599
600 return ret;
601 }
602
603 static int i915_batchbuffer(struct drm_device *dev, void *data,
604 struct drm_file *file_priv)
605 {
606 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
607 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
608 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
609 master_priv->sarea_priv;
610 drm_i915_batchbuffer_t *batch = data;
611 int ret;
612
613 if (!dev_priv->allow_batchbuffer) {
614 DRM_ERROR("Batchbuffer ioctl disabled\n");
615 return -EINVAL;
616 }
617
618 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
619 batch->start, batch->used, batch->num_cliprects);
620
621 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
622
623 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
624 batch->num_cliprects *
625 sizeof(struct drm_clip_rect)))
626 return -EFAULT;
627
628 mutex_lock(&dev->struct_mutex);
629 ret = i915_dispatch_batchbuffer(dev, batch);
630 mutex_unlock(&dev->struct_mutex);
631
632 if (sarea_priv)
633 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
634 return ret;
635 }
636
637 static int i915_cmdbuffer(struct drm_device *dev, void *data,
638 struct drm_file *file_priv)
639 {
640 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
641 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
642 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
643 master_priv->sarea_priv;
644 drm_i915_cmdbuffer_t *cmdbuf = data;
645 int ret;
646
647 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
648 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
649
650 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
651
652 if (cmdbuf->num_cliprects &&
653 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
654 cmdbuf->num_cliprects *
655 sizeof(struct drm_clip_rect))) {
656 DRM_ERROR("Fault accessing cliprects\n");
657 return -EFAULT;
658 }
659
660 mutex_lock(&dev->struct_mutex);
661 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
662 mutex_unlock(&dev->struct_mutex);
663 if (ret) {
664 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
665 return ret;
666 }
667
668 if (sarea_priv)
669 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
670 return 0;
671 }
672
673 static int i915_flip_bufs(struct drm_device *dev, void *data,
674 struct drm_file *file_priv)
675 {
676 int ret;
677
678 DRM_DEBUG("%s\n", __func__);
679
680 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
681
682 mutex_lock(&dev->struct_mutex);
683 ret = i915_dispatch_flip(dev);
684 mutex_unlock(&dev->struct_mutex);
685
686 return ret;
687 }
688
689 static int i915_getparam(struct drm_device *dev, void *data,
690 struct drm_file *file_priv)
691 {
692 drm_i915_private_t *dev_priv = dev->dev_private;
693 drm_i915_getparam_t *param = data;
694 int value;
695
696 if (!dev_priv) {
697 DRM_ERROR("called with no initialization\n");
698 return -EINVAL;
699 }
700
701 switch (param->param) {
702 case I915_PARAM_IRQ_ACTIVE:
703 value = dev->pdev->irq ? 1 : 0;
704 break;
705 case I915_PARAM_ALLOW_BATCHBUFFER:
706 value = dev_priv->allow_batchbuffer ? 1 : 0;
707 break;
708 case I915_PARAM_LAST_DISPATCH:
709 value = READ_BREADCRUMB(dev_priv);
710 break;
711 case I915_PARAM_CHIPSET_ID:
712 value = dev->pci_device;
713 break;
714 case I915_PARAM_HAS_GEM:
715 value = dev_priv->has_gem;
716 break;
717 default:
718 DRM_ERROR("Unknown parameter %d\n", param->param);
719 return -EINVAL;
720 }
721
722 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
723 DRM_ERROR("DRM_COPY_TO_USER failed\n");
724 return -EFAULT;
725 }
726
727 return 0;
728 }
729
730 static int i915_setparam(struct drm_device *dev, void *data,
731 struct drm_file *file_priv)
732 {
733 drm_i915_private_t *dev_priv = dev->dev_private;
734 drm_i915_setparam_t *param = data;
735
736 if (!dev_priv) {
737 DRM_ERROR("called with no initialization\n");
738 return -EINVAL;
739 }
740
741 switch (param->param) {
742 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
743 break;
744 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
745 dev_priv->tex_lru_log_granularity = param->value;
746 break;
747 case I915_SETPARAM_ALLOW_BATCHBUFFER:
748 dev_priv->allow_batchbuffer = param->value;
749 break;
750 default:
751 DRM_ERROR("unknown parameter %d\n", param->param);
752 return -EINVAL;
753 }
754
755 return 0;
756 }
757
758 static int i915_set_status_page(struct drm_device *dev, void *data,
759 struct drm_file *file_priv)
760 {
761 drm_i915_private_t *dev_priv = dev->dev_private;
762 drm_i915_hws_addr_t *hws = data;
763
764 if (!I915_NEED_GFX_HWS(dev))
765 return -EINVAL;
766
767 if (!dev_priv) {
768 DRM_ERROR("called with no initialization\n");
769 return -EINVAL;
770 }
771
772 printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
773
774 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
775
776 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
777 dev_priv->hws_map.size = 4*1024;
778 dev_priv->hws_map.type = 0;
779 dev_priv->hws_map.flags = 0;
780 dev_priv->hws_map.mtrr = 0;
781
782 drm_core_ioremap(&dev_priv->hws_map, dev);
783 if (dev_priv->hws_map.handle == NULL) {
784 i915_dma_cleanup(dev);
785 dev_priv->status_gfx_addr = 0;
786 DRM_ERROR("can not ioremap virtual address for"
787 " G33 hw status page\n");
788 return -ENOMEM;
789 }
790 dev_priv->hw_status_page = dev_priv->hws_map.handle;
791
792 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
793 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
794 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
795 dev_priv->status_gfx_addr);
796 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
797 return 0;
798 }
799
800 int i915_master_create(struct drm_device *dev, struct drm_master *master)
801 {
802 struct drm_i915_master_private *master_priv;
803
804 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
805 if (!master_priv)
806 return -ENOMEM;
807
808 master->driver_priv = master_priv;
809 return 0;
810 }
811
812 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
813 {
814 struct drm_i915_master_private *master_priv = master->driver_priv;
815
816 if (!master_priv)
817 return;
818
819 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
820
821 master->driver_priv = NULL;
822 }
823
824 int i915_driver_load(struct drm_device *dev, unsigned long flags)
825 {
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 unsigned long base, size;
828 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
829
830 /* i915 has 4 more counters */
831 dev->counters += 4;
832 dev->types[6] = _DRM_STAT_IRQ;
833 dev->types[7] = _DRM_STAT_PRIMARY;
834 dev->types[8] = _DRM_STAT_SECONDARY;
835 dev->types[9] = _DRM_STAT_DMA;
836
837 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
838 if (dev_priv == NULL)
839 return -ENOMEM;
840
841 memset(dev_priv, 0, sizeof(drm_i915_private_t));
842
843 dev->dev_private = (void *)dev_priv;
844 dev_priv->dev = dev;
845
846 /* Add register map (needed for suspend/resume) */
847 base = drm_get_resource_start(dev, mmio_bar);
848 size = drm_get_resource_len(dev, mmio_bar);
849
850 dev_priv->regs = ioremap(base, size);
851
852 #ifdef CONFIG_HIGHMEM64G
853 /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
854 dev_priv->has_gem = 0;
855 #else
856 /* enable GEM by default */
857 dev_priv->has_gem = 1;
858 #endif
859
860 i915_gem_load(dev);
861
862 /* Init HWS */
863 if (!I915_NEED_GFX_HWS(dev)) {
864 ret = i915_init_phys_hws(dev);
865 if (ret != 0)
866 return ret;
867 }
868
869 /* On the 945G/GM, the chipset reports the MSI capability on the
870 * integrated graphics even though the support isn't actually there
871 * according to the published specs. It doesn't appear to function
872 * correctly in testing on 945G.
873 * This may be a side effect of MSI having been made available for PEG
874 * and the registers being closely associated.
875 *
876 * According to chipset errata, on the 965GM, MSI interrupts may
877 * be lost or delayed, but we use them anyways to avoid
878 * stuck interrupts on some machines.
879 */
880 if (!IS_I945G(dev) && !IS_I945GM(dev))
881 pci_enable_msi(dev->pdev);
882
883 intel_opregion_init(dev);
884
885 spin_lock_init(&dev_priv->user_irq_lock);
886
887 ret = drm_vblank_init(dev, I915_NUM_PIPE);
888
889 if (ret) {
890 (void) i915_driver_unload(dev);
891 return ret;
892 }
893
894 return ret;
895 }
896
897 int i915_driver_unload(struct drm_device *dev)
898 {
899 struct drm_i915_private *dev_priv = dev->dev_private;
900
901 if (dev->pdev->msi_enabled)
902 pci_disable_msi(dev->pdev);
903
904 i915_free_hws(dev);
905
906 if (dev_priv->regs != NULL)
907 iounmap(dev_priv->regs);
908
909 intel_opregion_free(dev);
910
911 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
912 DRM_MEM_DRIVER);
913
914 return 0;
915 }
916
917 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
918 {
919 struct drm_i915_file_private *i915_file_priv;
920
921 DRM_DEBUG("\n");
922 i915_file_priv = (struct drm_i915_file_private *)
923 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
924
925 if (!i915_file_priv)
926 return -ENOMEM;
927
928 file_priv->driver_priv = i915_file_priv;
929
930 i915_file_priv->mm.last_gem_seqno = 0;
931 i915_file_priv->mm.last_gem_throttle_seqno = 0;
932
933 return 0;
934 }
935
936 void i915_driver_lastclose(struct drm_device * dev)
937 {
938 drm_i915_private_t *dev_priv = dev->dev_private;
939
940 if (!dev_priv)
941 return;
942
943 i915_gem_lastclose(dev);
944
945 if (dev_priv->agp_heap)
946 i915_mem_takedown(&(dev_priv->agp_heap));
947
948 i915_dma_cleanup(dev);
949 }
950
951 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
952 {
953 drm_i915_private_t *dev_priv = dev->dev_private;
954 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
955 }
956
957 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
958 {
959 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
960
961 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
962 }
963
964 struct drm_ioctl_desc i915_ioctls[] = {
965 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
966 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
967 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
968 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
969 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
970 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
971 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
972 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
973 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
974 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
975 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
976 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
977 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
978 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
979 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
980 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
981 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
982 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
983 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
984 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
985 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
986 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
987 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
988 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
989 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
990 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
991 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
992 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
993 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
994 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
995 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
996 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
997 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
998 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
999 };
1000
1001 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1002
1003 /**
1004 * Determine if the device really is AGP or not.
1005 *
1006 * All Intel graphics chipsets are treated as AGP, even if they are really
1007 * PCI-e.
1008 *
1009 * \param dev The device to be tested.
1010 *
1011 * \returns
1012 * A value of 1 is always retured to indictate every i9x5 is AGP.
1013 */
1014 int i915_driver_device_is_agp(struct drm_device * dev)
1015 {
1016 return 1;
1017 }
linux kernel for loongson