1 #ifndef __MYRI10GE_MCP_H__
2 #define __MYRI10GE_MCP_H__
4 #define MXGEFW_VERSION_MAJOR 1
5 #define MXGEFW_VERSION_MINOR 4
22 u32 data0
; /* will be low portion if data > 32 bits */
24 u32 data1
; /* will be high portion if data > 32 bits */
25 u32 data2
; /* currently unused.. */
27 struct mcp_dma_addr response_addr
;
33 struct mcp_cmd_response
{
39 * flags used in mcp_kreq_ether_send_t:
41 * The SMALL flag is only needed in the first segment. It is raised
42 * for packets that are total less or equal 512 bytes.
44 * The CKSUM flag must be set in all segments.
46 * The PADDED flags is set if the packet needs to be padded, and it
47 * must be set for all segments.
49 * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
50 * length of all previous segments was odd.
53 #define MXGEFW_FLAGS_SMALL 0x1
54 #define MXGEFW_FLAGS_TSO_HDR 0x1
55 #define MXGEFW_FLAGS_FIRST 0x2
56 #define MXGEFW_FLAGS_ALIGN_ODD 0x4
57 #define MXGEFW_FLAGS_CKSUM 0x8
58 #define MXGEFW_FLAGS_TSO_LAST 0x8
59 #define MXGEFW_FLAGS_NO_TSO 0x10
60 #define MXGEFW_FLAGS_TSO_CHOP 0x10
61 #define MXGEFW_FLAGS_TSO_PLD 0x20
63 #define MXGEFW_SEND_SMALL_SIZE 1520
64 #define MXGEFW_MAX_MTU 9400
66 union mcp_pso_or_cumlen
{
67 u16 pseudo_hdr_offset
;
71 #define MXGEFW_MAX_SEND_DESC 12
75 struct mcp_kreq_ether_send
{
78 u16 pseudo_hdr_offset
;
82 u8 cksum_offset
; /* where to start computing cksum */
83 u8 flags
; /* as defined above */
87 struct mcp_kreq_ether_recv
{
94 #define MXGEFW_CMD_OFFSET 0xf80000
96 enum myri10ge_mcp_cmd_type
{
98 /* Reset the mcp, it is left in a safe state, waiting
99 * for the driver to set all its parameters */
102 /* get the version number of the current firmware..
103 * (may be available in the eeprom strings..? */
104 MXGEFW_GET_MCP_VERSION
,
106 /* Parameters which must be set by the driver before it can
107 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
108 * MXGEFW_CMD_RESET is issued */
110 MXGEFW_CMD_SET_INTRQ_DMA
,
111 MXGEFW_CMD_SET_BIG_BUFFER_SIZE
, /* in bytes, power of 2 */
112 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE
, /* in bytes */
114 /* Parameters which refer to lanai SRAM addresses where the
115 * driver must issue PIO writes for various things */
117 MXGEFW_CMD_GET_SEND_OFFSET
,
118 MXGEFW_CMD_GET_SMALL_RX_OFFSET
,
119 MXGEFW_CMD_GET_BIG_RX_OFFSET
,
120 MXGEFW_CMD_GET_IRQ_ACK_OFFSET
,
121 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET
,
123 /* Parameters which refer to rings stored on the MCP,
124 * and whose size is controlled by the mcp */
126 MXGEFW_CMD_GET_SEND_RING_SIZE
, /* in bytes */
127 MXGEFW_CMD_GET_RX_RING_SIZE
, /* in bytes */
129 /* Parameters which refer to rings stored in the host,
130 * and whose size is controlled by the host. Note that
131 * all must be physically contiguous and must contain
132 * a power of 2 number of entries. */
134 MXGEFW_CMD_SET_INTRQ_SIZE
, /* in bytes */
136 /* command to bring ethernet interface up. Above parameters
137 * (plus mtu & mac address) must have been exchanged prior
138 * to issuing this command */
139 MXGEFW_CMD_ETHERNET_UP
,
141 /* command to bring ethernet interface down. No further sends
142 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
143 * is issued, and all interrupt queues must be flushed prior
144 * to ack'ing this command */
146 MXGEFW_CMD_ETHERNET_DOWN
,
148 /* commands the driver may issue live, without resetting
149 * the nic. Note that increasing the mtu "live" should
150 * only be done if the driver has already supplied buffers
151 * sufficiently large to handle the new mtu. Decreasing
152 * the mtu live is safe */
155 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET
, /* in microseconds */
156 MXGEFW_CMD_SET_STATS_INTERVAL
, /* in microseconds */
157 MXGEFW_CMD_SET_STATS_DMA
,
159 MXGEFW_ENABLE_PROMISC
,
160 MXGEFW_DISABLE_PROMISC
,
161 MXGEFW_SET_MAC_ADDRESS
,
163 MXGEFW_ENABLE_FLOW_CONTROL
,
164 MXGEFW_DISABLE_FLOW_CONTROL
,
167 * data0,data1 = DMA address
168 * data2 = RDMA length (MSH), WDMA length (LSH)
169 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
174 enum myri10ge_mcp_cmd_status
{
177 MXGEFW_CMD_ERROR_RANGE
,
178 MXGEFW_CMD_ERROR_BUSY
,
179 MXGEFW_CMD_ERROR_EMPTY
,
180 MXGEFW_CMD_ERROR_CLOSED
,
181 MXGEFW_CMD_ERROR_HASH_ERROR
,
182 MXGEFW_CMD_ERROR_BAD_PORT
,
183 MXGEFW_CMD_ERROR_RESOURCES
187 struct mcp_irq_data
{
191 u32 dropped_link_overflow
;
192 u32 dropped_link_error_or_filtered
;
195 u32 dropped_no_small_buffer
;
196 u32 dropped_no_big_buffer
;
197 u32 rdma_tags_available
;
205 #endif /* __MYRI10GE_MCP_H__ */