include/asm-x86_64/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/config.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7
   8 #ifdef __KERNEL__
   9
  10 #ifdef CONFIG_SMP
  11 #define LOCK_PREFIX "lock ; "
  12 #else
  13 #define LOCK_PREFIX ""
  14 #endif
  15
  16 #define __STR(x) #x
  17 #define STR(x) __STR(x)
  18
  19 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  20 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  21
  22 /* frame pointer must be last for get_wchan */
  23 #define SAVE_CONTEXT    "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  24 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\n\t"
  25
  26 #define __EXTRA_CLOBBER  \
  27         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  28
  29 #define switch_to(prev,next,last) \
  30         asm volatile(SAVE_CONTEXT                                                   \
  31                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  32                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  33                      "call __switch_to\n\t"                                       \
  34                      ".globl thread_return\n"                                   \
  35                      "thread_return:\n\t"                                           \
  36                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  37                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  38                      LOCK "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"               \
  39                      "movq %%rax,%%rdi\n\t"                                       \
  40                      "jc   ret_from_fork\n\t"                                     \
  41                      RESTORE_CONTEXT                                                \
  42                      : "=a" (last)                                                \
  43                      : [next] "S" (next), [prev] "D" (prev),                      \
  44                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  45                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  46                        [tif_fork] "i" (TIF_FORK),                         \
  47                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
  48                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  49                      : "memory", "cc" __EXTRA_CLOBBER)
  50
  51 extern void load_gs_index(unsigned);
  52
  53 /*
  54  * Load a segment. Fall back on loading the zero
  55  * segment if something goes wrong..
  56  */
  57 #define loadsegment(seg,value)  \
  58         asm volatile("\n"                       \
  59                 "1:\t"                          \
  60                 "movl %k0,%%" #seg "\n"         \
  61                 "2:\n"                          \
  62                 ".section .fixup,\"ax\"\n"      \
  63                 "3:\t"                          \
  64                 "movl %1,%%" #seg "\n\t"        \
  65                 "jmp 2b\n"                      \
  66                 ".previous\n"                   \
  67                 ".section __ex_table,\"a\"\n\t" \
  68                 ".align 8\n\t"                  \
  69                 ".quad 1b,3b\n"                 \
  70                 ".previous"                     \
  71                 : :"r" (value), "r" (0))
  72
  73 #define set_debug(value,register) \
  74                 __asm__("movq %0,%%db" #register  \
  75                 : /* no output */ \
  76                 :"r" ((unsigned long) value))
  77
  78
  79 #ifdef __KERNEL__
  80 struct alt_instr {
  81         __u8 *instr;            /* original instruction */
  82         __u8 *replacement;
  83         __u8  cpuid;            /* cpuid bit set for replacement */
  84         __u8  instrlen;         /* length of original instruction */
  85         __u8  replacementlen;   /* length of new instruction, <= instrlen */
  86         __u8  pad[5];
  87 };
  88 #endif
  89
  90 /*
  91  * Alternative instructions for different CPU types or capabilities.
  92  *
  93  * This allows to use optimized instructions even on generic binary
  94  * kernels.
  95  *
  96  * length of oldinstr must be longer or equal the length of newinstr
  97  * It can be padded with nops as needed.
  98  *
  99  * For non barrier like inlines please define new variants
 100  * without volatile and memory clobber.
 101  */
 102 #define alternative(oldinstr, newinstr, feature)        \
 103         asm volatile ("661:\n\t" oldinstr "\n662:\n"                 \
 104                       ".section .altinstructions,\"a\"\n"            \
 105                       "  .align 8\n"                                   \
 106                       "  .quad 661b\n"            /* label */          \
 107                       "  .quad 663f\n"            /* new instruction */ \
 108                       "  .byte %c0\n"             /* feature bit */    \
 109                       "  .byte 662b-661b\n"       /* sourcelen */      \
 110                       "  .byte 664f-663f\n"       /* replacementlen */ \
 111                       ".previous\n"                                     \
 112                       ".section .altinstr_replacement,\"ax\"\n"         \
 113                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 114                       ".previous" :: "i" (feature) : "memory")
 115
 116 /*
 117  * Alternative inline assembly with input.
 118  *
 119  * Peculiarities:
 120  * No memory clobber here.
 121  * Argument numbers start with 1.
 122  * Best is to use constraints that are fixed size (like (%1) ... "r")
 123  * If you use variable sized constraints like "m" or "g" in the
 124  * replacement make sure to pad to the worst case length.
 125  */
 126 #define alternative_input(oldinstr, newinstr, feature, input...)        \
 127         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 128                       ".section .altinstructions,\"a\"\n"               \
 129                       "  .align 8\n"                                    \
 130                       "  .quad 661b\n"            /* label */           \
 131                       "  .quad 663f\n"            /* new instruction */ \
 132                       "  .byte %c0\n"             /* feature bit */     \
 133                       "  .byte 662b-661b\n"       /* sourcelen */       \
 134                       "  .byte 664f-663f\n"       /* replacementlen */  \
 135                       ".previous\n"                                     \
 136                       ".section .altinstr_replacement,\"ax\"\n"         \
 137                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 138                       ".previous" :: "i" (feature), ##input)
 139
 140 /* Like alternative_input, but with a single output argument */
 141 #define alternative_io(oldinstr, newinstr, feature, output, input...) \
 142         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 143                       ".section .altinstructions,\"a\"\n"               \
 144                       "  .align 8\n"                                    \
 145                       "  .quad 661b\n"            /* label */           \
 146                       "  .quad 663f\n"            /* new instruction */ \
 147                       "  .byte %c[feat]\n"        /* feature bit */     \
 148                       "  .byte 662b-661b\n"       /* sourcelen */       \
 149                       "  .byte 664f-663f\n"       /* replacementlen */  \
 150                       ".previous\n"                                     \
 151                       ".section .altinstr_replacement,\"ax\"\n"         \
 152                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 153                       ".previous" : output : [feat] "i" (feature), ##input)
 154
 155 /*
 156  * Clear and set 'TS' bit respectively
 157  */
 158 #define clts() __asm__ __volatile__ ("clts")
 159
 160 static inline unsigned long read_cr0(void)
 161 {
 162         unsigned long cr0;
 163         asm volatile("movq %%cr0,%0" : "=r" (cr0));
 164         return cr0;
 165 }
 166
 167 static inline void write_cr0(unsigned long val)
 168 {
 169         asm volatile("movq %0,%%cr0" :: "r" (val));
 170 }
 171
 172 static inline unsigned long read_cr3(void)
 173 {
 174         unsigned long cr3;
 175         asm("movq %%cr3,%0" : "=r" (cr3));
 176         return cr3;
 177 }
 178
 179 static inline unsigned long read_cr4(void)
 180 {
 181         unsigned long cr4;
 182         asm("movq %%cr4,%0" : "=r" (cr4));
 183         return cr4;
 184 }
 185
 186 static inline void write_cr4(unsigned long val)
 187 {
 188         asm volatile("movq %0,%%cr4" :: "r" (val));
 189 }
 190
 191 #define stts() write_cr0(8 | read_cr0())
 192
 193 #define wbinvd() \
 194         __asm__ __volatile__ ("wbinvd": : :"memory");
 195
 196 #endif  /* __KERNEL__ */
 197
 198 #define nop() __asm__ __volatile__ ("nop")
 199
 200 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 201
 202 #define tas(ptr) (xchg((ptr),1))
 203
 204 #define __xg(x) ((volatile long *)(x))
 205
 206 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
 207 {
 208         *ptr = val;
 209 }
 210
 211 #define _set_64bit set_64bit
 212
 213 /*
 214  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 215  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 216  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 217  */
 218 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 219 {
 220         switch (size) {
 221                 case 1:
 222                         __asm__ __volatile__("xchgb %b0,%1"
 223                                 :"=q" (x)
 224                                 :"m" (*__xg(ptr)), "0" (x)
 225                                 :"memory");
 226                         break;
 227                 case 2:
 228                         __asm__ __volatile__("xchgw %w0,%1"
 229                                 :"=r" (x)
 230                                 :"m" (*__xg(ptr)), "0" (x)
 231                                 :"memory");
 232                         break;
 233                 case 4:
 234                         __asm__ __volatile__("xchgl %k0,%1"
 235                                 :"=r" (x)
 236                                 :"m" (*__xg(ptr)), "0" (x)
 237                                 :"memory");
 238                         break;
 239                 case 8:
 240                         __asm__ __volatile__("xchgq %0,%1"
 241                                 :"=r" (x)
 242                                 :"m" (*__xg(ptr)), "0" (x)
 243                                 :"memory");
 244                         break;
 245         }
 246         return x;
 247 }
 248
 249 /*
 250  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 251  * store NEW in MEM.  Return the initial value in MEM.  Success is
 252  * indicated by comparing RETURN with OLD.
 253  */
 254
 255 #define __HAVE_ARCH_CMPXCHG 1
 256
 257 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 258                                       unsigned long new, int size)
 259 {
 260         unsigned long prev;
 261         switch (size) {
 262         case 1:
 263                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 264                                      : "=a"(prev)
 265                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 266                                      : "memory");
 267                 return prev;
 268         case 2:
 269                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 270                                      : "=a"(prev)
 271                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 272                                      : "memory");
 273                 return prev;
 274         case 4:
 275                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
 276                                      : "=a"(prev)
 277                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 278                                      : "memory");
 279                 return prev;
 280         case 8:
 281                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
 282                                      : "=a"(prev)
 283                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 284                                      : "memory");
 285                 return prev;
 286         }
 287         return old;
 288 }
 289
 290 #define cmpxchg(ptr,o,n)\
 291         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 292                                         (unsigned long)(n),sizeof(*(ptr))))
 293
 294 #ifdef CONFIG_SMP
 295 #define smp_mb()        mb()
 296 #define smp_rmb()       rmb()
 297 #define smp_wmb()       wmb()
 298 #define smp_read_barrier_depends()      do {} while(0)
 299 #else
 300 #define smp_mb()        barrier()
 301 #define smp_rmb()       barrier()
 302 #define smp_wmb()       barrier()
 303 #define smp_read_barrier_depends()      do {} while(0)
 304 #endif
 305
 306
 307 /*
 308  * Force strict CPU ordering.
 309  * And yes, this is required on UP too when we're talking
 310  * to devices.
 311  */
 312 #define mb()    asm volatile("mfence":::"memory")
 313 #define rmb()   asm volatile("lfence":::"memory")
 314
 315 #ifdef CONFIG_UNORDERED_IO
 316 #define wmb()   asm volatile("sfence" ::: "memory")
 317 #else
 318 #define wmb()   asm volatile("" ::: "memory")
 319 #endif
 320 #define read_barrier_depends()  do {} while(0)
 321 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 322 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 323
 324 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 325
 326 /* interrupt control.. */
 327 #define local_save_flags(x)     do { warn_if_not_ulong(x); __asm__ __volatile__("# save_flags \n\t pushfq ; popq %q0":"=g" (x): /* no input */ :"memory"); } while (0)
 328 #define local_irq_restore(x)    __asm__ __volatile__("# restore_flags \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory", "cc")
 329 #define local_irq_disable()     __asm__ __volatile__("cli": : :"memory")
 330 #define local_irq_enable()      __asm__ __volatile__("sti": : :"memory")
 331 /* used in the idle loop; sti takes one instruction cycle to complete */
 332 #define safe_halt()             __asm__ __volatile__("sti; hlt": : :"memory")
 333 /* used when interrupts are already enabled or to shutdown the processor */
 334 #define halt()                  __asm__ __volatile__("hlt": : :"memory")
 335
 336 #define irqs_disabled()                 \
 337 ({                                      \
 338         unsigned long flags;            \
 339         local_save_flags(flags);        \
 340         !(flags & (1<<9));              \
 341 })
 342
 343 /* For spinlocks etc */
 344 #define local_irq_save(x)       do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
 345
 346 void cpu_idle_wait(void);
 347
 348 extern unsigned long arch_align_stack(unsigned long sp);
 349
 350 #endif