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[ALSA] hda - increase max_codecs of ICH to 4
[linux-2.6/linux-loongson.git] / sound / pci / hda / hda_intel.c
blobdc68709e75694dedbf8626190472c84864e3665b
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int single_cmd;
60 static int enable_msi;
61
62 module_param_array(index, int, NULL, 0444);
63 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
64 module_param_array(id, charp, NULL, 0444);
65 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
66 module_param_array(enable, bool, NULL, 0444);
67 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
68 module_param_array(model, charp, NULL, 0444);
69 MODULE_PARM_DESC(model, "Use the given board model.");
70 module_param_array(position_fix, int, NULL, 0444);
71 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
72 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
73 module_param_array(probe_mask, int, NULL, 0444);
74 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
75 module_param(single_cmd, bool, 0444);
76 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
77 "(for debugging only).");
78 module_param(enable_msi, int, 0444);
79 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80
81 #ifdef CONFIG_SND_HDA_POWER_SAVE
82 /* power_save option is defined in hda_codec.c */
83
84 /* reset the HD-audio controller in power save mode.
85 * this may give more power-saving, but will take longer time to
86 * wake up.
87 */
88 static int power_save_controller = 1;
89 module_param(power_save_controller, bool, 0644);
90 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
91 #endif
92
93 MODULE_LICENSE("GPL");
94 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
95 "{Intel, ICH6M},"
96 "{Intel, ICH7},"
97 "{Intel, ESB2},"
98 "{Intel, ICH8},"
99 "{Intel, ICH9},"
100 "{Intel, ICH10},"
101 "{Intel, SCH},"
102 "{ATI, SB450},"
103 "{ATI, SB600},"
104 "{ATI, RS600},"
105 "{ATI, RS690},"
106 "{ATI, RS780},"
107 "{ATI, R600},"
108 "{ATI, RV630},"
109 "{ATI, RV610},"
110 "{ATI, RV670},"
111 "{ATI, RV635},"
112 "{ATI, RV620},"
113 "{ATI, RV770},"
114 "{VIA, VT8251},"
115 "{VIA, VT8237A},"
116 "{SiS, SIS966},"
117 "{ULI, M5461}}");
118 MODULE_DESCRIPTION("Intel HDA driver");
119
120 #define SFX "hda-intel: "
121
122
123 /*
124 * registers
125 */
126 #define ICH6_REG_GCAP 0x00
127 #define ICH6_REG_VMIN 0x02
128 #define ICH6_REG_VMAJ 0x03
129 #define ICH6_REG_OUTPAY 0x04
130 #define ICH6_REG_INPAY 0x06
131 #define ICH6_REG_GCTL 0x08
132 #define ICH6_REG_WAKEEN 0x0c
133 #define ICH6_REG_STATESTS 0x0e
134 #define ICH6_REG_GSTS 0x10
135 #define ICH6_REG_INTCTL 0x20
136 #define ICH6_REG_INTSTS 0x24
137 #define ICH6_REG_WALCLK 0x30
138 #define ICH6_REG_SYNC 0x34
139 #define ICH6_REG_CORBLBASE 0x40
140 #define ICH6_REG_CORBUBASE 0x44
141 #define ICH6_REG_CORBWP 0x48
142 #define ICH6_REG_CORBRP 0x4A
143 #define ICH6_REG_CORBCTL 0x4c
144 #define ICH6_REG_CORBSTS 0x4d
145 #define ICH6_REG_CORBSIZE 0x4e
146
147 #define ICH6_REG_RIRBLBASE 0x50
148 #define ICH6_REG_RIRBUBASE 0x54
149 #define ICH6_REG_RIRBWP 0x58
150 #define ICH6_REG_RINTCNT 0x5a
151 #define ICH6_REG_RIRBCTL 0x5c
152 #define ICH6_REG_RIRBSTS 0x5d
153 #define ICH6_REG_RIRBSIZE 0x5e
154
155 #define ICH6_REG_IC 0x60
156 #define ICH6_REG_IR 0x64
157 #define ICH6_REG_IRS 0x68
158 #define ICH6_IRS_VALID (1<<1)
159 #define ICH6_IRS_BUSY (1<<0)
160
161 #define ICH6_REG_DPLBASE 0x70
162 #define ICH6_REG_DPUBASE 0x74
163 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
164
165 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
166 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167
168 /* stream register offsets from stream base */
169 #define ICH6_REG_SD_CTL 0x00
170 #define ICH6_REG_SD_STS 0x03
171 #define ICH6_REG_SD_LPIB 0x04
172 #define ICH6_REG_SD_CBL 0x08
173 #define ICH6_REG_SD_LVI 0x0c
174 #define ICH6_REG_SD_FIFOW 0x0e
175 #define ICH6_REG_SD_FIFOSIZE 0x10
176 #define ICH6_REG_SD_FORMAT 0x12
177 #define ICH6_REG_SD_BDLPL 0x18
178 #define ICH6_REG_SD_BDLPU 0x1c
179
180 /* PCI space */
181 #define ICH6_PCIREG_TCSEL 0x44
182
183 /*
184 * other constants
185 */
186
187 /* max number of SDs */
188 /* ICH, ATI and VIA have 4 playback and 4 capture */
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_NUM_PLAYBACK 4
191
192 /* ULI has 6 playback and 5 capture */
193 #define ULI_NUM_CAPTURE 5
194 #define ULI_NUM_PLAYBACK 6
195
196 /* ATI HDMI has 1 playback and 0 capture */
197 #define ATIHDMI_NUM_CAPTURE 0
198 #define ATIHDMI_NUM_PLAYBACK 1
199
200 /* TERA has 4 playback and 3 capture */
201 #define TERA_NUM_CAPTURE 3
202 #define TERA_NUM_PLAYBACK 4
203
204 /* this number is statically defined for simplicity */
205 #define MAX_AZX_DEV 16
206
207 /* max number of fragments - we may use more if allocating more pages for BDL */
208 #define BDL_SIZE 4096
209 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
210 #define AZX_MAX_FRAG 32
211 /* max buffer size - no h/w limit, you can increase as you like */
212 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
213 /* max number of PCM devics per card */
214 #define AZX_MAX_PCMS 8
215
216 /* RIRB int mask: overrun[2], response[0] */
217 #define RIRB_INT_RESPONSE 0x01
218 #define RIRB_INT_OVERRUN 0x04
219 #define RIRB_INT_MASK 0x05
220
221 /* STATESTS int mask: SD2,SD1,SD0 */
222 #define AZX_MAX_CODECS 3
223 #define STATESTS_INT_MASK 0x07
224
225 /* SD_CTL bits */
226 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
227 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
228 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
229 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
230 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
231 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
232 #define SD_CTL_STREAM_TAG_SHIFT 20
233
234 /* SD_CTL and SD_STS */
235 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
236 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
237 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
238 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
239 SD_INT_COMPLETE)
240
241 /* SD_STS */
242 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
243
244 /* INTCTL and INTSTS */
245 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
246 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
247 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
248
249 /* GCTL unsolicited response enable bit */
250 #define ICH6_GCTL_UREN (1<<8)
251
252 /* GCTL reset bit */
253 #define ICH6_GCTL_RESET (1<<0)
254
255 /* CORB/RIRB control, read/write pointer */
256 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
257 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
258 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
259 /* below are so far hardcoded - should read registers in future */
260 #define ICH6_MAX_CORB_ENTRIES 256
261 #define ICH6_MAX_RIRB_ENTRIES 256
262
263 /* position fix mode */
264 enum {
265 POS_FIX_AUTO,
266 POS_FIX_NONE,
267 POS_FIX_POSBUF,
268 POS_FIX_FIFO,
269 };
270
271 /* Defines for ATI HD Audio support in SB450 south bridge */
272 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
273 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
274
275 /* Defines for Nvidia HDA support */
276 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
277 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
278
279 /* Defines for Intel SCH HDA snoop control */
280 #define INTEL_SCH_HDA_DEVC 0x78
281 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
282
283
284 /*
285 */
286
287 struct azx_dev {
288 struct snd_dma_buffer bdl; /* BDL buffer */
289 u32 *posbuf; /* position buffer pointer */
290
291 unsigned int bufsize; /* size of the play buffer in bytes */
292 unsigned int period_bytes; /* size of the period in bytes */
293 unsigned int frags; /* number for period in the play buffer */
294 unsigned int fifo_size; /* FIFO size */
295
296 void __iomem *sd_addr; /* stream descriptor pointer */
297
298 u32 sd_int_sta_mask; /* stream int status mask */
299
300 /* pcm support */
301 struct snd_pcm_substream *substream; /* assigned substream,
302 * set in PCM open
303 */
304 unsigned int format_val; /* format value to be set in the
305 * controller and the codec
306 */
307 unsigned char stream_tag; /* assigned stream */
308 unsigned char index; /* stream index */
309
310 unsigned int opened :1;
311 unsigned int running :1;
312 unsigned int irq_pending: 1;
313 };
314
315 /* CORB/RIRB */
316 struct azx_rb {
317 u32 *buf; /* CORB/RIRB buffer
318 * Each CORB entry is 4byte, RIRB is 8byte
319 */
320 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
321 /* for RIRB */
322 unsigned short rp, wp; /* read/write pointers */
323 int cmds; /* number of pending requests */
324 u32 res; /* last read value */
325 };
326
327 struct azx {
328 struct snd_card *card;
329 struct pci_dev *pci;
330
331 /* chip type specific */
332 int driver_type;
333 int playback_streams;
334 int playback_index_offset;
335 int capture_streams;
336 int capture_index_offset;
337 int num_streams;
338
339 /* pci resources */
340 unsigned long addr;
341 void __iomem *remap_addr;
342 int irq;
343
344 /* locks */
345 spinlock_t reg_lock;
346 struct mutex open_mutex;
347
348 /* streams (x num_streams) */
349 struct azx_dev *azx_dev;
350
351 /* PCM */
352 struct snd_pcm *pcm[AZX_MAX_PCMS];
353
354 /* HD codec */
355 unsigned short codec_mask;
356 struct hda_bus *bus;
357
358 /* CORB/RIRB */
359 struct azx_rb corb;
360 struct azx_rb rirb;
361
362 /* CORB/RIRB and position buffers */
363 struct snd_dma_buffer rb;
364 struct snd_dma_buffer posbuf;
365
366 /* flags */
367 int position_fix;
368 unsigned int running :1;
369 unsigned int initialized :1;
370 unsigned int single_cmd :1;
371 unsigned int polling_mode :1;
372 unsigned int msi :1;
373
374 /* for debugging */
375 unsigned int last_cmd; /* last issued command (to sync) */
376
377 /* for pending irqs */
378 struct work_struct irq_pending_work;
379 };
380
381 /* driver types */
382 enum {
383 AZX_DRIVER_ICH,
384 AZX_DRIVER_SCH,
385 AZX_DRIVER_ATI,
386 AZX_DRIVER_ATIHDMI,
387 AZX_DRIVER_VIA,
388 AZX_DRIVER_SIS,
389 AZX_DRIVER_ULI,
390 AZX_DRIVER_NVIDIA,
391 AZX_DRIVER_TERA,
392 };
393
394 static char *driver_short_names[] __devinitdata = {
395 [AZX_DRIVER_ICH] = "HDA Intel",
396 [AZX_DRIVER_SCH] = "HDA Intel MID",
397 [AZX_DRIVER_ATI] = "HDA ATI SB",
398 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
399 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
400 [AZX_DRIVER_SIS] = "HDA SIS966",
401 [AZX_DRIVER_ULI] = "HDA ULI M5461",
402 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
403 [AZX_DRIVER_TERA] = "HDA Teradici",
404 };
405
406 /*
407 * macros for easy use
408 */
409 #define azx_writel(chip,reg,value) \
410 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
411 #define azx_readl(chip,reg) \
412 readl((chip)->remap_addr + ICH6_REG_##reg)
413 #define azx_writew(chip,reg,value) \
414 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
415 #define azx_readw(chip,reg) \
416 readw((chip)->remap_addr + ICH6_REG_##reg)
417 #define azx_writeb(chip,reg,value) \
418 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
419 #define azx_readb(chip,reg) \
420 readb((chip)->remap_addr + ICH6_REG_##reg)
421
422 #define azx_sd_writel(dev,reg,value) \
423 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
424 #define azx_sd_readl(dev,reg) \
425 readl((dev)->sd_addr + ICH6_REG_##reg)
426 #define azx_sd_writew(dev,reg,value) \
427 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
428 #define azx_sd_readw(dev,reg) \
429 readw((dev)->sd_addr + ICH6_REG_##reg)
430 #define azx_sd_writeb(dev,reg,value) \
431 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
432 #define azx_sd_readb(dev,reg) \
433 readb((dev)->sd_addr + ICH6_REG_##reg)
434
435 /* for pcm support */
436 #define get_azx_dev(substream) (substream->runtime->private_data)
437
438 /* Get the upper 32bit of the given dma_addr_t
439 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
440 */
441 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
442
443 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
444
445 /*
446 * Interface for HD codec
447 */
448
449 /*
450 * CORB / RIRB interface
451 */
452 static int azx_alloc_cmd_io(struct azx *chip)
453 {
454 int err;
455
456 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
457 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
458 snd_dma_pci_data(chip->pci),
459 PAGE_SIZE, &chip->rb);
460 if (err < 0) {
461 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
462 return err;
463 }
464 return 0;
465 }
466
467 static void azx_init_cmd_io(struct azx *chip)
468 {
469 /* CORB set up */
470 chip->corb.addr = chip->rb.addr;
471 chip->corb.buf = (u32 *)chip->rb.area;
472 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
473 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
474
475 /* set the corb size to 256 entries (ULI requires explicitly) */
476 azx_writeb(chip, CORBSIZE, 0x02);
477 /* set the corb write pointer to 0 */
478 azx_writew(chip, CORBWP, 0);
479 /* reset the corb hw read pointer */
480 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
481 /* enable corb dma */
482 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
483
484 /* RIRB set up */
485 chip->rirb.addr = chip->rb.addr + 2048;
486 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
487 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
488 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
489
490 /* set the rirb size to 256 entries (ULI requires explicitly) */
491 azx_writeb(chip, RIRBSIZE, 0x02);
492 /* reset the rirb hw write pointer */
493 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
494 /* set N=1, get RIRB response interrupt for new entry */
495 azx_writew(chip, RINTCNT, 1);
496 /* enable rirb dma and response irq */
497 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
498 chip->rirb.rp = chip->rirb.cmds = 0;
499 }
500
501 static void azx_free_cmd_io(struct azx *chip)
502 {
503 /* disable ringbuffer DMAs */
504 azx_writeb(chip, RIRBCTL, 0);
505 azx_writeb(chip, CORBCTL, 0);
506 }
507
508 /* send a command */
509 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
510 {
511 struct azx *chip = codec->bus->private_data;
512 unsigned int wp;
513
514 /* add command to corb */
515 wp = azx_readb(chip, CORBWP);
516 wp++;
517 wp %= ICH6_MAX_CORB_ENTRIES;
518
519 spin_lock_irq(&chip->reg_lock);
520 chip->rirb.cmds++;
521 chip->corb.buf[wp] = cpu_to_le32(val);
522 azx_writel(chip, CORBWP, wp);
523 spin_unlock_irq(&chip->reg_lock);
524
525 return 0;
526 }
527
528 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
529
530 /* retrieve RIRB entry - called from interrupt handler */
531 static void azx_update_rirb(struct azx *chip)
532 {
533 unsigned int rp, wp;
534 u32 res, res_ex;
535
536 wp = azx_readb(chip, RIRBWP);
537 if (wp == chip->rirb.wp)
538 return;
539 chip->rirb.wp = wp;
540
541 while (chip->rirb.rp != wp) {
542 chip->rirb.rp++;
543 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
544
545 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
546 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
547 res = le32_to_cpu(chip->rirb.buf[rp]);
548 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
549 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
550 else if (chip->rirb.cmds) {
551 chip->rirb.res = res;
552 smp_wmb();
553 chip->rirb.cmds--;
554 }
555 }
556 }
557
558 /* receive a response */
559 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
560 {
561 struct azx *chip = codec->bus->private_data;
562 unsigned long timeout;
563
564 again:
565 timeout = jiffies + msecs_to_jiffies(1000);
566 for (;;) {
567 if (chip->polling_mode) {
568 spin_lock_irq(&chip->reg_lock);
569 azx_update_rirb(chip);
570 spin_unlock_irq(&chip->reg_lock);
571 }
572 if (!chip->rirb.cmds) {
573 smp_rmb();
574 return chip->rirb.res; /* the last value */
575 }
576 if (time_after(jiffies, timeout))
577 break;
578 if (codec->bus->needs_damn_long_delay)
579 msleep(2); /* temporary workaround */
580 else {
581 udelay(10);
582 cond_resched();
583 }
584 }
585
586 if (chip->msi) {
587 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
588 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
589 free_irq(chip->irq, chip);
590 chip->irq = -1;
591 pci_disable_msi(chip->pci);
592 chip->msi = 0;
593 if (azx_acquire_irq(chip, 1) < 0)
594 return -1;
595 goto again;
596 }
597
598 if (!chip->polling_mode) {
599 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
600 "switching to polling mode: last cmd=0x%08x\n",
601 chip->last_cmd);
602 chip->polling_mode = 1;
603 goto again;
604 }
605
606 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
607 "switching to single_cmd mode: last cmd=0x%08x\n",
608 chip->last_cmd);
609 chip->rirb.rp = azx_readb(chip, RIRBWP);
610 chip->rirb.cmds = 0;
611 /* switch to single_cmd mode */
612 chip->single_cmd = 1;
613 azx_free_cmd_io(chip);
614 return -1;
615 }
616
617 /*
618 * Use the single immediate command instead of CORB/RIRB for simplicity
619 *
620 * Note: according to Intel, this is not preferred use. The command was
621 * intended for the BIOS only, and may get confused with unsolicited
622 * responses. So, we shouldn't use it for normal operation from the
623 * driver.
624 * I left the codes, however, for debugging/testing purposes.
625 */
626
627 /* send a command */
628 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
629 {
630 struct azx *chip = codec->bus->private_data;
631 int timeout = 50;
632
633 while (timeout--) {
634 /* check ICB busy bit */
635 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
636 /* Clear IRV valid bit */
637 azx_writew(chip, IRS, azx_readw(chip, IRS) |
638 ICH6_IRS_VALID);
639 azx_writel(chip, IC, val);
640 azx_writew(chip, IRS, azx_readw(chip, IRS) |
641 ICH6_IRS_BUSY);
642 return 0;
643 }
644 udelay(1);
645 }
646 if (printk_ratelimit())
647 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
648 azx_readw(chip, IRS), val);
649 return -EIO;
650 }
651
652 /* receive a response */
653 static unsigned int azx_single_get_response(struct hda_codec *codec)
654 {
655 struct azx *chip = codec->bus->private_data;
656 int timeout = 50;
657
658 while (timeout--) {
659 /* check IRV busy bit */
660 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
661 return azx_readl(chip, IR);
662 udelay(1);
663 }
664 if (printk_ratelimit())
665 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
666 azx_readw(chip, IRS));
667 return (unsigned int)-1;
668 }
669
670 /*
671 * The below are the main callbacks from hda_codec.
672 *
673 * They are just the skeleton to call sub-callbacks according to the
674 * current setting of chip->single_cmd.
675 */
676
677 /* send a command */
678 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
679 int direct, unsigned int verb,
680 unsigned int para)
681 {
682 struct azx *chip = codec->bus->private_data;
683 u32 val;
684
685 val = (u32)(codec->addr & 0x0f) << 28;
686 val |= (u32)direct << 27;
687 val |= (u32)nid << 20;
688 val |= verb << 8;
689 val |= para;
690 chip->last_cmd = val;
691
692 if (chip->single_cmd)
693 return azx_single_send_cmd(codec, val);
694 else
695 return azx_corb_send_cmd(codec, val);
696 }
697
698 /* get a response */
699 static unsigned int azx_get_response(struct hda_codec *codec)
700 {
701 struct azx *chip = codec->bus->private_data;
702 if (chip->single_cmd)
703 return azx_single_get_response(codec);
704 else
705 return azx_rirb_get_response(codec);
706 }
707
708 #ifdef CONFIG_SND_HDA_POWER_SAVE
709 static void azx_power_notify(struct hda_codec *codec);
710 #endif
711
712 /* reset codec link */
713 static int azx_reset(struct azx *chip)
714 {
715 int count;
716
717 /* clear STATESTS */
718 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
719
720 /* reset controller */
721 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
722
723 count = 50;
724 while (azx_readb(chip, GCTL) && --count)
725 msleep(1);
726
727 /* delay for >= 100us for codec PLL to settle per spec
728 * Rev 0.9 section 5.5.1
729 */
730 msleep(1);
731
732 /* Bring controller out of reset */
733 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
734
735 count = 50;
736 while (!azx_readb(chip, GCTL) && --count)
737 msleep(1);
738
739 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
740 msleep(1);
741
742 /* check to see if controller is ready */
743 if (!azx_readb(chip, GCTL)) {
744 snd_printd("azx_reset: controller not ready!\n");
745 return -EBUSY;
746 }
747
748 /* Accept unsolicited responses */
749 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
750
751 /* detect codecs */
752 if (!chip->codec_mask) {
753 chip->codec_mask = azx_readw(chip, STATESTS);
754 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
755 }
756
757 return 0;
758 }
759
760
761 /*
762 * Lowlevel interface
763 */
764
765 /* enable interrupts */
766 static void azx_int_enable(struct azx *chip)
767 {
768 /* enable controller CIE and GIE */
769 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
770 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
771 }
772
773 /* disable interrupts */
774 static void azx_int_disable(struct azx *chip)
775 {
776 int i;
777
778 /* disable interrupts in stream descriptor */
779 for (i = 0; i < chip->num_streams; i++) {
780 struct azx_dev *azx_dev = &chip->azx_dev[i];
781 azx_sd_writeb(azx_dev, SD_CTL,
782 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
783 }
784
785 /* disable SIE for all streams */
786 azx_writeb(chip, INTCTL, 0);
787
788 /* disable controller CIE and GIE */
789 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
790 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
791 }
792
793 /* clear interrupts */
794 static void azx_int_clear(struct azx *chip)
795 {
796 int i;
797
798 /* clear stream status */
799 for (i = 0; i < chip->num_streams; i++) {
800 struct azx_dev *azx_dev = &chip->azx_dev[i];
801 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
802 }
803
804 /* clear STATESTS */
805 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
806
807 /* clear rirb status */
808 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
809
810 /* clear int status */
811 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
812 }
813
814 /* start a stream */
815 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
816 {
817 /* enable SIE */
818 azx_writeb(chip, INTCTL,
819 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
820 /* set DMA start and interrupt mask */
821 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
822 SD_CTL_DMA_START | SD_INT_MASK);
823 }
824
825 /* stop a stream */
826 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
827 {
828 /* stop DMA */
829 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
830 ~(SD_CTL_DMA_START | SD_INT_MASK));
831 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
832 /* disable SIE */
833 azx_writeb(chip, INTCTL,
834 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
835 }
836
837
838 /*
839 * reset and start the controller registers
840 */
841 static void azx_init_chip(struct azx *chip)
842 {
843 if (chip->initialized)
844 return;
845
846 /* reset controller */
847 azx_reset(chip);
848
849 /* initialize interrupts */
850 azx_int_clear(chip);
851 azx_int_enable(chip);
852
853 /* initialize the codec command I/O */
854 if (!chip->single_cmd)
855 azx_init_cmd_io(chip);
856
857 /* program the position buffer */
858 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
859 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
860
861 chip->initialized = 1;
862 }
863
864 /*
865 * initialize the PCI registers
866 */
867 /* update bits in a PCI register byte */
868 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
869 unsigned char mask, unsigned char val)
870 {
871 unsigned char data;
872
873 pci_read_config_byte(pci, reg, &data);
874 data &= ~mask;
875 data |= (val & mask);
876 pci_write_config_byte(pci, reg, data);
877 }
878
879 static void azx_init_pci(struct azx *chip)
880 {
881 unsigned short snoop;
882
883 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
884 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
885 * Ensuring these bits are 0 clears playback static on some HD Audio
886 * codecs
887 */
888 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
889
890 switch (chip->driver_type) {
891 case AZX_DRIVER_ATI:
892 /* For ATI SB450 azalia HD audio, we need to enable snoop */
893 update_pci_byte(chip->pci,
894 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
895 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
896 break;
897 case AZX_DRIVER_NVIDIA:
898 /* For NVIDIA HDA, enable snoop */
899 update_pci_byte(chip->pci,
900 NVIDIA_HDA_TRANSREG_ADDR,
901 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
902 break;
903 case AZX_DRIVER_SCH:
904 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
905 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
906 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
907 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
908 pci_read_config_word(chip->pci,
909 INTEL_SCH_HDA_DEVC, &snoop);
910 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
911 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
912 ? "Failed" : "OK");
913 }
914 break;
915
916 }
917 }
918
919
920 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
921
922 /*
923 * interrupt handler
924 */
925 static irqreturn_t azx_interrupt(int irq, void *dev_id)
926 {
927 struct azx *chip = dev_id;
928 struct azx_dev *azx_dev;
929 u32 status;
930 int i;
931
932 spin_lock(&chip->reg_lock);
933
934 status = azx_readl(chip, INTSTS);
935 if (status == 0) {
936 spin_unlock(&chip->reg_lock);
937 return IRQ_NONE;
938 }
939
940 for (i = 0; i < chip->num_streams; i++) {
941 azx_dev = &chip->azx_dev[i];
942 if (status & azx_dev->sd_int_sta_mask) {
943 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
944 if (!azx_dev->substream || !azx_dev->running)
945 continue;
946 /* check whether this IRQ is really acceptable */
947 if (azx_position_ok(chip, azx_dev)) {
948 azx_dev->irq_pending = 0;
949 spin_unlock(&chip->reg_lock);
950 snd_pcm_period_elapsed(azx_dev->substream);
951 spin_lock(&chip->reg_lock);
952 } else {
953 /* bogus IRQ, process it later */
954 azx_dev->irq_pending = 1;
955 schedule_work(&chip->irq_pending_work);
956 }
957 }
958 }
959
960 /* clear rirb int */
961 status = azx_readb(chip, RIRBSTS);
962 if (status & RIRB_INT_MASK) {
963 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
964 azx_update_rirb(chip);
965 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
966 }
967
968 #if 0
969 /* clear state status int */
970 if (azx_readb(chip, STATESTS) & 0x04)
971 azx_writeb(chip, STATESTS, 0x04);
972 #endif
973 spin_unlock(&chip->reg_lock);
974
975 return IRQ_HANDLED;
976 }
977
978
979 /*
980 * set up BDL entries
981 */
982 static int azx_setup_periods(struct snd_pcm_substream *substream,
983 struct azx_dev *azx_dev)
984 {
985 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
986 u32 *bdl;
987 int i, ofs, periods, period_bytes;
988
989 /* reset BDL address */
990 azx_sd_writel(azx_dev, SD_BDLPL, 0);
991 azx_sd_writel(azx_dev, SD_BDLPU, 0);
992
993 period_bytes = snd_pcm_lib_period_bytes(substream);
994 azx_dev->period_bytes = period_bytes;
995 periods = azx_dev->bufsize / period_bytes;
996
997 /* program the initial BDL entries */
998 bdl = (u32 *)azx_dev->bdl.area;
999 ofs = 0;
1000 azx_dev->frags = 0;
1001 for (i = 0; i < periods; i++) {
1002 int size, rest;
1003 if (i >= AZX_MAX_BDL_ENTRIES) {
1004 snd_printk(KERN_ERR "Too many BDL entries: "
1005 "buffer=%d, period=%d\n",
1006 azx_dev->bufsize, period_bytes);
1007 /* reset */
1008 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1009 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1010 return -EINVAL;
1011 }
1012 rest = period_bytes;
1013 do {
1014 dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1015 /* program the address field of the BDL entry */
1016 bdl[0] = cpu_to_le32((u32)addr);
1017 bdl[1] = cpu_to_le32(upper_32bit(addr));
1018 /* program the size field of the BDL entry */
1019 size = PAGE_SIZE - (ofs % PAGE_SIZE);
1020 if (rest < size)
1021 size = rest;
1022 bdl[2] = cpu_to_le32(size);
1023 /* program the IOC to enable interrupt
1024 * only when the whole fragment is processed
1025 */
1026 rest -= size;
1027 bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1028 bdl += 4;
1029 azx_dev->frags++;
1030 ofs += size;
1031 } while (rest > 0);
1032 }
1033 return 0;
1034 }
1035
1036 /*
1037 * set up the SD for streaming
1038 */
1039 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1040 {
1041 unsigned char val;
1042 int timeout;
1043
1044 /* make sure the run bit is zero for SD */
1045 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1046 ~SD_CTL_DMA_START);
1047 /* reset stream */
1048 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1049 SD_CTL_STREAM_RESET);
1050 udelay(3);
1051 timeout = 300;
1052 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1053 --timeout)
1054 ;
1055 val &= ~SD_CTL_STREAM_RESET;
1056 azx_sd_writeb(azx_dev, SD_CTL, val);
1057 udelay(3);
1058
1059 timeout = 300;
1060 /* waiting for hardware to report that the stream is out of reset */
1061 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1062 --timeout)
1063 ;
1064
1065 /* program the stream_tag */
1066 azx_sd_writel(azx_dev, SD_CTL,
1067 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1068 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1069
1070 /* program the length of samples in cyclic buffer */
1071 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1072
1073 /* program the stream format */
1074 /* this value needs to be the same as the one programmed */
1075 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1076
1077 /* program the stream LVI (last valid index) of the BDL */
1078 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1079
1080 /* program the BDL address */
1081 /* lower BDL address */
1082 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1083 /* upper BDL address */
1084 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1085
1086 /* enable the position buffer */
1087 if (chip->position_fix == POS_FIX_POSBUF ||
1088 chip->position_fix == POS_FIX_AUTO) {
1089 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1090 azx_writel(chip, DPLBASE,
1091 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1092 }
1093
1094 /* set the interrupt enable bits in the descriptor control register */
1095 azx_sd_writel(azx_dev, SD_CTL,
1096 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1097
1098 return 0;
1099 }
1100
1101
1102 /*
1103 * Codec initialization
1104 */
1105
1106 static unsigned int azx_max_codecs[] __devinitdata = {
1107 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
1108 [AZX_DRIVER_SCH] = 3,
1109 [AZX_DRIVER_ATI] = 4,
1110 [AZX_DRIVER_ATIHDMI] = 4,
1111 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1112 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1113 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1114 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1115 [AZX_DRIVER_TERA] = 1,
1116 };
1117
1118 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1119 unsigned int codec_probe_mask)
1120 {
1121 struct hda_bus_template bus_temp;
1122 int c, codecs, audio_codecs, err;
1123
1124 memset(&bus_temp, 0, sizeof(bus_temp));
1125 bus_temp.private_data = chip;
1126 bus_temp.modelname = model;
1127 bus_temp.pci = chip->pci;
1128 bus_temp.ops.command = azx_send_cmd;
1129 bus_temp.ops.get_response = azx_get_response;
1130 #ifdef CONFIG_SND_HDA_POWER_SAVE
1131 bus_temp.ops.pm_notify = azx_power_notify;
1132 #endif
1133
1134 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1135 if (err < 0)
1136 return err;
1137
1138 codecs = audio_codecs = 0;
1139 for (c = 0; c < AZX_MAX_CODECS; c++) {
1140 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1141 struct hda_codec *codec;
1142 err = snd_hda_codec_new(chip->bus, c, &codec);
1143 if (err < 0)
1144 continue;
1145 codecs++;
1146 if (codec->afg)
1147 audio_codecs++;
1148 }
1149 }
1150 if (!audio_codecs) {
1151 /* probe additional slots if no codec is found */
1152 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1153 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1154 err = snd_hda_codec_new(chip->bus, c, NULL);
1155 if (err < 0)
1156 continue;
1157 codecs++;
1158 }
1159 }
1160 }
1161 if (!codecs) {
1162 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1163 return -ENXIO;
1164 }
1165
1166 return 0;
1167 }
1168
1169
1170 /*
1171 * PCM support
1172 */
1173
1174 /* assign a stream for the PCM */
1175 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1176 {
1177 int dev, i, nums;
1178 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1179 dev = chip->playback_index_offset;
1180 nums = chip->playback_streams;
1181 } else {
1182 dev = chip->capture_index_offset;
1183 nums = chip->capture_streams;
1184 }
1185 for (i = 0; i < nums; i++, dev++)
1186 if (!chip->azx_dev[dev].opened) {
1187 chip->azx_dev[dev].opened = 1;
1188 return &chip->azx_dev[dev];
1189 }
1190 return NULL;
1191 }
1192
1193 /* release the assigned stream */
1194 static inline void azx_release_device(struct azx_dev *azx_dev)
1195 {
1196 azx_dev->opened = 0;
1197 }
1198
1199 static struct snd_pcm_hardware azx_pcm_hw = {
1200 .info = (SNDRV_PCM_INFO_MMAP |
1201 SNDRV_PCM_INFO_INTERLEAVED |
1202 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1203 SNDRV_PCM_INFO_MMAP_VALID |
1204 /* No full-resume yet implemented */
1205 /* SNDRV_PCM_INFO_RESUME |*/
1206 SNDRV_PCM_INFO_PAUSE |
1207 SNDRV_PCM_INFO_SYNC_START),
1208 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1209 .rates = SNDRV_PCM_RATE_48000,
1210 .rate_min = 48000,
1211 .rate_max = 48000,
1212 .channels_min = 2,
1213 .channels_max = 2,
1214 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1215 .period_bytes_min = 128,
1216 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1217 .periods_min = 2,
1218 .periods_max = AZX_MAX_FRAG,
1219 .fifo_size = 0,
1220 };
1221
1222 struct azx_pcm {
1223 struct azx *chip;
1224 struct hda_codec *codec;
1225 struct hda_pcm_stream *hinfo[2];
1226 };
1227
1228 static int azx_pcm_open(struct snd_pcm_substream *substream)
1229 {
1230 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1231 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1232 struct azx *chip = apcm->chip;
1233 struct azx_dev *azx_dev;
1234 struct snd_pcm_runtime *runtime = substream->runtime;
1235 unsigned long flags;
1236 int err;
1237
1238 mutex_lock(&chip->open_mutex);
1239 azx_dev = azx_assign_device(chip, substream->stream);
1240 if (azx_dev == NULL) {
1241 mutex_unlock(&chip->open_mutex);
1242 return -EBUSY;
1243 }
1244 runtime->hw = azx_pcm_hw;
1245 runtime->hw.channels_min = hinfo->channels_min;
1246 runtime->hw.channels_max = hinfo->channels_max;
1247 runtime->hw.formats = hinfo->formats;
1248 runtime->hw.rates = hinfo->rates;
1249 snd_pcm_limit_hw_rates(runtime);
1250 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1251 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1252 128);
1253 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1254 128);
1255 snd_hda_power_up(apcm->codec);
1256 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1257 if (err < 0) {
1258 azx_release_device(azx_dev);
1259 snd_hda_power_down(apcm->codec);
1260 mutex_unlock(&chip->open_mutex);
1261 return err;
1262 }
1263 spin_lock_irqsave(&chip->reg_lock, flags);
1264 azx_dev->substream = substream;
1265 azx_dev->running = 0;
1266 spin_unlock_irqrestore(&chip->reg_lock, flags);
1267
1268 runtime->private_data = azx_dev;
1269 snd_pcm_set_sync(substream);
1270 mutex_unlock(&chip->open_mutex);
1271 return 0;
1272 }
1273
1274 static int azx_pcm_close(struct snd_pcm_substream *substream)
1275 {
1276 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1277 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1278 struct azx *chip = apcm->chip;
1279 struct azx_dev *azx_dev = get_azx_dev(substream);
1280 unsigned long flags;
1281
1282 mutex_lock(&chip->open_mutex);
1283 spin_lock_irqsave(&chip->reg_lock, flags);
1284 azx_dev->substream = NULL;
1285 azx_dev->running = 0;
1286 spin_unlock_irqrestore(&chip->reg_lock, flags);
1287 azx_release_device(azx_dev);
1288 hinfo->ops.close(hinfo, apcm->codec, substream);
1289 snd_hda_power_down(apcm->codec);
1290 mutex_unlock(&chip->open_mutex);
1291 return 0;
1292 }
1293
1294 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1295 struct snd_pcm_hw_params *hw_params)
1296 {
1297 return snd_pcm_lib_malloc_pages(substream,
1298 params_buffer_bytes(hw_params));
1299 }
1300
1301 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1302 {
1303 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1304 struct azx_dev *azx_dev = get_azx_dev(substream);
1305 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1306
1307 /* reset BDL address */
1308 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1309 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1310 azx_sd_writel(azx_dev, SD_CTL, 0);
1311
1312 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1313
1314 return snd_pcm_lib_free_pages(substream);
1315 }
1316
1317 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1318 {
1319 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1320 struct azx *chip = apcm->chip;
1321 struct azx_dev *azx_dev = get_azx_dev(substream);
1322 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1324
1325 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1326 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1327 runtime->channels,
1328 runtime->format,
1329 hinfo->maxbps);
1330 if (!azx_dev->format_val) {
1331 snd_printk(KERN_ERR SFX
1332 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1333 runtime->rate, runtime->channels, runtime->format);
1334 return -EINVAL;
1335 }
1336
1337 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1338 azx_dev->bufsize, azx_dev->format_val);
1339 if (azx_setup_periods(substream, azx_dev) < 0)
1340 return -EINVAL;
1341 azx_setup_controller(chip, azx_dev);
1342 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1343 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1344 else
1345 azx_dev->fifo_size = 0;
1346
1347 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1348 azx_dev->format_val, substream);
1349 }
1350
1351 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1352 {
1353 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1354 struct azx *chip = apcm->chip;
1355 struct azx_dev *azx_dev;
1356 struct snd_pcm_substream *s;
1357 int start, nsync = 0, sbits = 0;
1358 int nwait, timeout;
1359
1360 switch (cmd) {
1361 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1362 case SNDRV_PCM_TRIGGER_RESUME:
1363 case SNDRV_PCM_TRIGGER_START:
1364 start = 1;
1365 break;
1366 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1367 case SNDRV_PCM_TRIGGER_SUSPEND:
1368 case SNDRV_PCM_TRIGGER_STOP:
1369 start = 0;
1370 break;
1371 default:
1372 return -EINVAL;
1373 }
1374
1375 snd_pcm_group_for_each_entry(s, substream) {
1376 if (s->pcm->card != substream->pcm->card)
1377 continue;
1378 azx_dev = get_azx_dev(s);
1379 sbits |= 1 << azx_dev->index;
1380 nsync++;
1381 snd_pcm_trigger_done(s, substream);
1382 }
1383
1384 spin_lock(&chip->reg_lock);
1385 if (nsync > 1) {
1386 /* first, set SYNC bits of corresponding streams */
1387 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1388 }
1389 snd_pcm_group_for_each_entry(s, substream) {
1390 if (s->pcm->card != substream->pcm->card)
1391 continue;
1392 azx_dev = get_azx_dev(s);
1393 if (start)
1394 azx_stream_start(chip, azx_dev);
1395 else
1396 azx_stream_stop(chip, azx_dev);
1397 azx_dev->running = start;
1398 }
1399 spin_unlock(&chip->reg_lock);
1400 if (start) {
1401 if (nsync == 1)
1402 return 0;
1403 /* wait until all FIFOs get ready */
1404 for (timeout = 5000; timeout; timeout--) {
1405 nwait = 0;
1406 snd_pcm_group_for_each_entry(s, substream) {
1407 if (s->pcm->card != substream->pcm->card)
1408 continue;
1409 azx_dev = get_azx_dev(s);
1410 if (!(azx_sd_readb(azx_dev, SD_STS) &
1411 SD_STS_FIFO_READY))
1412 nwait++;
1413 }
1414 if (!nwait)
1415 break;
1416 cpu_relax();
1417 }
1418 } else {
1419 /* wait until all RUN bits are cleared */
1420 for (timeout = 5000; timeout; timeout--) {
1421 nwait = 0;
1422 snd_pcm_group_for_each_entry(s, substream) {
1423 if (s->pcm->card != substream->pcm->card)
1424 continue;
1425 azx_dev = get_azx_dev(s);
1426 if (azx_sd_readb(azx_dev, SD_CTL) &
1427 SD_CTL_DMA_START)
1428 nwait++;
1429 }
1430 if (!nwait)
1431 break;
1432 cpu_relax();
1433 }
1434 }
1435 if (nsync > 1) {
1436 spin_lock(&chip->reg_lock);
1437 /* reset SYNC bits */
1438 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1439 spin_unlock(&chip->reg_lock);
1440 }
1441 return 0;
1442 }
1443
1444 static unsigned int azx_get_position(struct azx *chip,
1445 struct azx_dev *azx_dev)
1446 {
1447 unsigned int pos;
1448
1449 if (chip->position_fix == POS_FIX_POSBUF ||
1450 chip->position_fix == POS_FIX_AUTO) {
1451 /* use the position buffer */
1452 pos = le32_to_cpu(*azx_dev->posbuf);
1453 } else {
1454 /* read LPIB */
1455 pos = azx_sd_readl(azx_dev, SD_LPIB);
1456 if (chip->position_fix == POS_FIX_FIFO)
1457 pos += azx_dev->fifo_size;
1458 }
1459 if (pos >= azx_dev->bufsize)
1460 pos = 0;
1461 return pos;
1462 }
1463
1464 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1465 {
1466 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1467 struct azx *chip = apcm->chip;
1468 struct azx_dev *azx_dev = get_azx_dev(substream);
1469 return bytes_to_frames(substream->runtime,
1470 azx_get_position(chip, azx_dev));
1471 }
1472
1473 /*
1474 * Check whether the current DMA position is acceptable for updating
1475 * periods. Returns non-zero if it's OK.
1476 *
1477 * Many HD-audio controllers appear pretty inaccurate about
1478 * the update-IRQ timing. The IRQ is issued before actually the
1479 * data is processed. So, we need to process it afterwords in a
1480 * workqueue.
1481 */
1482 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1483 {
1484 unsigned int pos;
1485
1486 pos = azx_get_position(chip, azx_dev);
1487 if (chip->position_fix == POS_FIX_AUTO) {
1488 if (!pos) {
1489 printk(KERN_WARNING
1490 "hda-intel: Invalid position buffer, "
1491 "using LPIB read method instead.\n");
1492 chip->position_fix = POS_FIX_NONE;
1493 pos = azx_get_position(chip, azx_dev);
1494 } else
1495 chip->position_fix = POS_FIX_POSBUF;
1496 }
1497
1498 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1499 return 0; /* NG - it's below the period boundary */
1500 return 1; /* OK, it's fine */
1501 }
1502
1503 /*
1504 * The work for pending PCM period updates.
1505 */
1506 static void azx_irq_pending_work(struct work_struct *work)
1507 {
1508 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1509 int i, pending;
1510
1511 for (;;) {
1512 pending = 0;
1513 spin_lock_irq(&chip->reg_lock);
1514 for (i = 0; i < chip->num_streams; i++) {
1515 struct azx_dev *azx_dev = &chip->azx_dev[i];
1516 if (!azx_dev->irq_pending ||
1517 !azx_dev->substream ||
1518 !azx_dev->running)
1519 continue;
1520 if (azx_position_ok(chip, azx_dev)) {
1521 azx_dev->irq_pending = 0;
1522 spin_unlock(&chip->reg_lock);
1523 snd_pcm_period_elapsed(azx_dev->substream);
1524 spin_lock(&chip->reg_lock);
1525 } else
1526 pending++;
1527 }
1528 spin_unlock_irq(&chip->reg_lock);
1529 if (!pending)
1530 return;
1531 cond_resched();
1532 }
1533 }
1534
1535 /* clear irq_pending flags and assure no on-going workq */
1536 static void azx_clear_irq_pending(struct azx *chip)
1537 {
1538 int i;
1539
1540 spin_lock_irq(&chip->reg_lock);
1541 for (i = 0; i < chip->num_streams; i++)
1542 chip->azx_dev[i].irq_pending = 0;
1543 spin_unlock_irq(&chip->reg_lock);
1544 flush_scheduled_work();
1545 }
1546
1547 static struct snd_pcm_ops azx_pcm_ops = {
1548 .open = azx_pcm_open,
1549 .close = azx_pcm_close,
1550 .ioctl = snd_pcm_lib_ioctl,
1551 .hw_params = azx_pcm_hw_params,
1552 .hw_free = azx_pcm_hw_free,
1553 .prepare = azx_pcm_prepare,
1554 .trigger = azx_pcm_trigger,
1555 .pointer = azx_pcm_pointer,
1556 .page = snd_pcm_sgbuf_ops_page,
1557 };
1558
1559 static void azx_pcm_free(struct snd_pcm *pcm)
1560 {
1561 kfree(pcm->private_data);
1562 }
1563
1564 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1565 struct hda_pcm *cpcm)
1566 {
1567 int err;
1568 struct snd_pcm *pcm;
1569 struct azx_pcm *apcm;
1570
1571 /* if no substreams are defined for both playback and capture,
1572 * it's just a placeholder. ignore it.
1573 */
1574 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1575 return 0;
1576
1577 snd_assert(cpcm->name, return -EINVAL);
1578
1579 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1580 cpcm->stream[0].substreams,
1581 cpcm->stream[1].substreams,
1582 &pcm);
1583 if (err < 0)
1584 return err;
1585 strcpy(pcm->name, cpcm->name);
1586 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1587 if (apcm == NULL)
1588 return -ENOMEM;
1589 apcm->chip = chip;
1590 apcm->codec = codec;
1591 apcm->hinfo[0] = &cpcm->stream[0];
1592 apcm->hinfo[1] = &cpcm->stream[1];
1593 pcm->private_data = apcm;
1594 pcm->private_free = azx_pcm_free;
1595 if (cpcm->stream[0].substreams)
1596 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1597 if (cpcm->stream[1].substreams)
1598 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1599 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1600 snd_dma_pci_data(chip->pci),
1601 1024 * 64, 1024 * 1024);
1602 chip->pcm[cpcm->device] = pcm;
1603 return 0;
1604 }
1605
1606 static int __devinit azx_pcm_create(struct azx *chip)
1607 {
1608 static const char *dev_name[HDA_PCM_NTYPES] = {
1609 "Audio", "SPDIF", "HDMI", "Modem"
1610 };
1611 /* starting device index for each PCM type */
1612 static int dev_idx[HDA_PCM_NTYPES] = {
1613 [HDA_PCM_TYPE_AUDIO] = 0,
1614 [HDA_PCM_TYPE_SPDIF] = 1,
1615 [HDA_PCM_TYPE_HDMI] = 3,
1616 [HDA_PCM_TYPE_MODEM] = 6
1617 };
1618 /* normal audio device indices; not linear to keep compatibility */
1619 static int audio_idx[4] = { 0, 2, 4, 5 };
1620 struct hda_codec *codec;
1621 int c, err;
1622 int num_devs[HDA_PCM_NTYPES];
1623
1624 err = snd_hda_build_pcms(chip->bus);
1625 if (err < 0)
1626 return err;
1627
1628 /* create audio PCMs */
1629 memset(num_devs, 0, sizeof(num_devs));
1630 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1631 for (c = 0; c < codec->num_pcms; c++) {
1632 struct hda_pcm *cpcm = &codec->pcm_info[c];
1633 int type = cpcm->pcm_type;
1634 switch (type) {
1635 case HDA_PCM_TYPE_AUDIO:
1636 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1637 snd_printk(KERN_WARNING
1638 "Too many audio devices\n");
1639 continue;
1640 }
1641 cpcm->device = audio_idx[num_devs[type]];
1642 break;
1643 case HDA_PCM_TYPE_SPDIF:
1644 case HDA_PCM_TYPE_HDMI:
1645 case HDA_PCM_TYPE_MODEM:
1646 if (num_devs[type]) {
1647 snd_printk(KERN_WARNING
1648 "%s already defined\n",
1649 dev_name[type]);
1650 continue;
1651 }
1652 cpcm->device = dev_idx[type];
1653 break;
1654 default:
1655 snd_printk(KERN_WARNING
1656 "Invalid PCM type %d\n", type);
1657 continue;
1658 }
1659 num_devs[type]++;
1660 err = create_codec_pcm(chip, codec, cpcm);
1661 if (err < 0)
1662 return err;
1663 }
1664 }
1665 return 0;
1666 }
1667
1668 /*
1669 * mixer creation - all stuff is implemented in hda module
1670 */
1671 static int __devinit azx_mixer_create(struct azx *chip)
1672 {
1673 return snd_hda_build_controls(chip->bus);
1674 }
1675
1676
1677 /*
1678 * initialize SD streams
1679 */
1680 static int __devinit azx_init_stream(struct azx *chip)
1681 {
1682 int i;
1683
1684 /* initialize each stream (aka device)
1685 * assign the starting bdl address to each stream (device)
1686 * and initialize
1687 */
1688 for (i = 0; i < chip->num_streams; i++) {
1689 struct azx_dev *azx_dev = &chip->azx_dev[i];
1690 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1691 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1692 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1693 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1694 azx_dev->sd_int_sta_mask = 1 << i;
1695 /* stream tag: must be non-zero and unique */
1696 azx_dev->index = i;
1697 azx_dev->stream_tag = i + 1;
1698 }
1699
1700 return 0;
1701 }
1702
1703 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1704 {
1705 if (request_irq(chip->pci->irq, azx_interrupt,
1706 chip->msi ? 0 : IRQF_SHARED,
1707 "HDA Intel", chip)) {
1708 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1709 "disabling device\n", chip->pci->irq);
1710 if (do_disconnect)
1711 snd_card_disconnect(chip->card);
1712 return -1;
1713 }
1714 chip->irq = chip->pci->irq;
1715 pci_intx(chip->pci, !chip->msi);
1716 return 0;
1717 }
1718
1719
1720 static void azx_stop_chip(struct azx *chip)
1721 {
1722 if (!chip->initialized)
1723 return;
1724
1725 /* disable interrupts */
1726 azx_int_disable(chip);
1727 azx_int_clear(chip);
1728
1729 /* disable CORB/RIRB */
1730 azx_free_cmd_io(chip);
1731
1732 /* disable position buffer */
1733 azx_writel(chip, DPLBASE, 0);
1734 azx_writel(chip, DPUBASE, 0);
1735
1736 chip->initialized = 0;
1737 }
1738
1739 #ifdef CONFIG_SND_HDA_POWER_SAVE
1740 /* power-up/down the controller */
1741 static void azx_power_notify(struct hda_codec *codec)
1742 {
1743 struct azx *chip = codec->bus->private_data;
1744 struct hda_codec *c;
1745 int power_on = 0;
1746
1747 list_for_each_entry(c, &codec->bus->codec_list, list) {
1748 if (c->power_on) {
1749 power_on = 1;
1750 break;
1751 }
1752 }
1753 if (power_on)
1754 azx_init_chip(chip);
1755 else if (chip->running && power_save_controller)
1756 azx_stop_chip(chip);
1757 }
1758 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1759
1760 #ifdef CONFIG_PM
1761 /*
1762 * power management
1763 */
1764 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1765 {
1766 struct snd_card *card = pci_get_drvdata(pci);
1767 struct azx *chip = card->private_data;
1768 int i;
1769
1770 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1771 azx_clear_irq_pending(chip);
1772 for (i = 0; i < AZX_MAX_PCMS; i++)
1773 snd_pcm_suspend_all(chip->pcm[i]);
1774 if (chip->initialized)
1775 snd_hda_suspend(chip->bus, state);
1776 azx_stop_chip(chip);
1777 if (chip->irq >= 0) {
1778 free_irq(chip->irq, chip);
1779 chip->irq = -1;
1780 }
1781 if (chip->msi)
1782 pci_disable_msi(chip->pci);
1783 pci_disable_device(pci);
1784 pci_save_state(pci);
1785 pci_set_power_state(pci, pci_choose_state(pci, state));
1786 return 0;
1787 }
1788
1789 static int azx_resume(struct pci_dev *pci)
1790 {
1791 struct snd_card *card = pci_get_drvdata(pci);
1792 struct azx *chip = card->private_data;
1793
1794 pci_set_power_state(pci, PCI_D0);
1795 pci_restore_state(pci);
1796 if (pci_enable_device(pci) < 0) {
1797 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1798 "disabling device\n");
1799 snd_card_disconnect(card);
1800 return -EIO;
1801 }
1802 pci_set_master(pci);
1803 if (chip->msi)
1804 if (pci_enable_msi(pci) < 0)
1805 chip->msi = 0;
1806 if (azx_acquire_irq(chip, 1) < 0)
1807 return -EIO;
1808 azx_init_pci(chip);
1809
1810 if (snd_hda_codecs_inuse(chip->bus))
1811 azx_init_chip(chip);
1812
1813 snd_hda_resume(chip->bus);
1814 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1815 return 0;
1816 }
1817 #endif /* CONFIG_PM */
1818
1819
1820 /*
1821 * destructor
1822 */
1823 static int azx_free(struct azx *chip)
1824 {
1825 int i;
1826
1827 if (chip->initialized) {
1828 azx_clear_irq_pending(chip);
1829 for (i = 0; i < chip->num_streams; i++)
1830 azx_stream_stop(chip, &chip->azx_dev[i]);
1831 azx_stop_chip(chip);
1832 }
1833
1834 if (chip->irq >= 0)
1835 free_irq(chip->irq, (void*)chip);
1836 if (chip->msi)
1837 pci_disable_msi(chip->pci);
1838 if (chip->remap_addr)
1839 iounmap(chip->remap_addr);
1840
1841 if (chip->azx_dev) {
1842 for (i = 0; i < chip->num_streams; i++)
1843 if (chip->azx_dev[i].bdl.area)
1844 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1845 }
1846 if (chip->rb.area)
1847 snd_dma_free_pages(&chip->rb);
1848 if (chip->posbuf.area)
1849 snd_dma_free_pages(&chip->posbuf);
1850 pci_release_regions(chip->pci);
1851 pci_disable_device(chip->pci);
1852 kfree(chip->azx_dev);
1853 kfree(chip);
1854
1855 return 0;
1856 }
1857
1858 static int azx_dev_free(struct snd_device *device)
1859 {
1860 return azx_free(device->device_data);
1861 }
1862
1863 /*
1864 * white/black-listing for position_fix
1865 */
1866 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1867 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1868 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1869 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1870 {}
1871 };
1872
1873 static int __devinit check_position_fix(struct azx *chip, int fix)
1874 {
1875 const struct snd_pci_quirk *q;
1876
1877 if (fix == POS_FIX_AUTO) {
1878 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1879 if (q) {
1880 printk(KERN_INFO
1881 "hda_intel: position_fix set to %d "
1882 "for device %04x:%04x\n",
1883 q->value, q->subvendor, q->subdevice);
1884 return q->value;
1885 }
1886 }
1887 return fix;
1888 }
1889
1890 /*
1891 * black-lists for probe_mask
1892 */
1893 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1894 /* Thinkpad often breaks the controller communication when accessing
1895 * to the non-working (or non-existing) modem codec slot.
1896 */
1897 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1898 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1899 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1900 {}
1901 };
1902
1903 static void __devinit check_probe_mask(struct azx *chip, int dev)
1904 {
1905 const struct snd_pci_quirk *q;
1906
1907 if (probe_mask[dev] == -1) {
1908 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1909 if (q) {
1910 printk(KERN_INFO
1911 "hda_intel: probe_mask set to 0x%x "
1912 "for device %04x:%04x\n",
1913 q->value, q->subvendor, q->subdevice);
1914 probe_mask[dev] = q->value;
1915 }
1916 }
1917 }
1918
1919
1920 /*
1921 * constructor
1922 */
1923 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1924 int dev, int driver_type,
1925 struct azx **rchip)
1926 {
1927 struct azx *chip;
1928 int i, err;
1929 unsigned short gcap;
1930 static struct snd_device_ops ops = {
1931 .dev_free = azx_dev_free,
1932 };
1933
1934 *rchip = NULL;
1935
1936 err = pci_enable_device(pci);
1937 if (err < 0)
1938 return err;
1939
1940 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1941 if (!chip) {
1942 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1943 pci_disable_device(pci);
1944 return -ENOMEM;
1945 }
1946
1947 spin_lock_init(&chip->reg_lock);
1948 mutex_init(&chip->open_mutex);
1949 chip->card = card;
1950 chip->pci = pci;
1951 chip->irq = -1;
1952 chip->driver_type = driver_type;
1953 chip->msi = enable_msi;
1954 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1955
1956 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1957 check_probe_mask(chip, dev);
1958
1959 chip->single_cmd = single_cmd;
1960
1961 #if BITS_PER_LONG != 64
1962 /* Fix up base address on ULI M5461 */
1963 if (chip->driver_type == AZX_DRIVER_ULI) {
1964 u16 tmp3;
1965 pci_read_config_word(pci, 0x40, &tmp3);
1966 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1967 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1968 }
1969 #endif
1970
1971 err = pci_request_regions(pci, "ICH HD audio");
1972 if (err < 0) {
1973 kfree(chip);
1974 pci_disable_device(pci);
1975 return err;
1976 }
1977
1978 chip->addr = pci_resource_start(pci, 0);
1979 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1980 if (chip->remap_addr == NULL) {
1981 snd_printk(KERN_ERR SFX "ioremap error\n");
1982 err = -ENXIO;
1983 goto errout;
1984 }
1985
1986 if (chip->msi)
1987 if (pci_enable_msi(pci) < 0)
1988 chip->msi = 0;
1989
1990 if (azx_acquire_irq(chip, 0) < 0) {
1991 err = -EBUSY;
1992 goto errout;
1993 }
1994
1995 pci_set_master(pci);
1996 synchronize_irq(chip->irq);
1997
1998 gcap = azx_readw(chip, GCAP);
1999 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2000
2001 /* allow 64bit DMA address if supported by H/W */
2002 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2003 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2004
2005 /* read number of streams from GCAP register instead of using
2006 * hardcoded value
2007 */
2008 chip->capture_streams = (gcap >> 8) & 0x0f;
2009 chip->playback_streams = (gcap >> 12) & 0x0f;
2010 if (!chip->playback_streams && !chip->capture_streams) {
2011 /* gcap didn't give any info, switching to old method */
2012
2013 switch (chip->driver_type) {
2014 case AZX_DRIVER_ULI:
2015 chip->playback_streams = ULI_NUM_PLAYBACK;
2016 chip->capture_streams = ULI_NUM_CAPTURE;
2017 break;
2018 case AZX_DRIVER_ATIHDMI:
2019 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2020 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2021 break;
2022 default:
2023 chip->playback_streams = ICH6_NUM_PLAYBACK;
2024 chip->capture_streams = ICH6_NUM_CAPTURE;
2025 break;
2026 }
2027 }
2028 chip->capture_index_offset = 0;
2029 chip->playback_index_offset = chip->capture_streams;
2030 chip->num_streams = chip->playback_streams + chip->capture_streams;
2031 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2032 GFP_KERNEL);
2033 if (!chip->azx_dev) {
2034 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2035 goto errout;
2036 }
2037
2038 for (i = 0; i < chip->num_streams; i++) {
2039 /* allocate memory for the BDL for each stream */
2040 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2041 snd_dma_pci_data(chip->pci),
2042 BDL_SIZE, &chip->azx_dev[i].bdl);
2043 if (err < 0) {
2044 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2045 goto errout;
2046 }
2047 }
2048 /* allocate memory for the position buffer */
2049 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2050 snd_dma_pci_data(chip->pci),
2051 chip->num_streams * 8, &chip->posbuf);
2052 if (err < 0) {
2053 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2054 goto errout;
2055 }
2056 /* allocate CORB/RIRB */
2057 if (!chip->single_cmd) {
2058 err = azx_alloc_cmd_io(chip);
2059 if (err < 0)
2060 goto errout;
2061 }
2062
2063 /* initialize streams */
2064 azx_init_stream(chip);
2065
2066 /* initialize chip */
2067 azx_init_pci(chip);
2068 azx_init_chip(chip);
2069
2070 /* codec detection */
2071 if (!chip->codec_mask) {
2072 snd_printk(KERN_ERR SFX "no codecs found!\n");
2073 err = -ENODEV;
2074 goto errout;
2075 }
2076
2077 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2078 if (err <0) {
2079 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2080 goto errout;
2081 }
2082
2083 strcpy(card->driver, "HDA-Intel");
2084 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2085 sprintf(card->longname, "%s at 0x%lx irq %i",
2086 card->shortname, chip->addr, chip->irq);
2087
2088 *rchip = chip;
2089 return 0;
2090
2091 errout:
2092 azx_free(chip);
2093 return err;
2094 }
2095
2096 static void power_down_all_codecs(struct azx *chip)
2097 {
2098 #ifdef CONFIG_SND_HDA_POWER_SAVE
2099 /* The codecs were powered up in snd_hda_codec_new().
2100 * Now all initialization done, so turn them down if possible
2101 */
2102 struct hda_codec *codec;
2103 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2104 snd_hda_power_down(codec);
2105 }
2106 #endif
2107 }
2108
2109 static int __devinit azx_probe(struct pci_dev *pci,
2110 const struct pci_device_id *pci_id)
2111 {
2112 static int dev;
2113 struct snd_card *card;
2114 struct azx *chip;
2115 int err;
2116
2117 if (dev >= SNDRV_CARDS)
2118 return -ENODEV;
2119 if (!enable[dev]) {
2120 dev++;
2121 return -ENOENT;
2122 }
2123
2124 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2125 if (!card) {
2126 snd_printk(KERN_ERR SFX "Error creating card!\n");
2127 return -ENOMEM;
2128 }
2129
2130 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2131 if (err < 0) {
2132 snd_card_free(card);
2133 return err;
2134 }
2135 card->private_data = chip;
2136
2137 /* create codec instances */
2138 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2139 if (err < 0) {
2140 snd_card_free(card);
2141 return err;
2142 }
2143
2144 /* create PCM streams */
2145 err = azx_pcm_create(chip);
2146 if (err < 0) {
2147 snd_card_free(card);
2148 return err;
2149 }
2150
2151 /* create mixer controls */
2152 err = azx_mixer_create(chip);
2153 if (err < 0) {
2154 snd_card_free(card);
2155 return err;
2156 }
2157
2158 snd_card_set_dev(card, &pci->dev);
2159
2160 err = snd_card_register(card);
2161 if (err < 0) {
2162 snd_card_free(card);
2163 return err;
2164 }
2165
2166 pci_set_drvdata(pci, card);
2167 chip->running = 1;
2168 power_down_all_codecs(chip);
2169
2170 dev++;
2171 return err;
2172 }
2173
2174 static void __devexit azx_remove(struct pci_dev *pci)
2175 {
2176 snd_card_free(pci_get_drvdata(pci));
2177 pci_set_drvdata(pci, NULL);
2178 }
2179
2180 /* PCI IDs */
2181 static struct pci_device_id azx_ids[] = {
2182 /* ICH 6..10 */
2183 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2184 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2185 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2186 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2187 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2188 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2189 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2190 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2191 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2192 /* SCH */
2193 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2194 /* ATI SB 450/600 */
2195 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2196 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2197 /* ATI HDMI */
2198 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2199 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2200 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2201 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2202 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2203 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2204 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2205 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2206 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2207 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2208 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2209 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2210 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2211 /* VIA VT8251/VT8237A */
2212 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2213 /* SIS966 */
2214 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2215 /* ULI M5461 */
2216 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2217 /* NVIDIA MCP */
2218 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2219 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2220 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2221 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2222 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2223 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2224 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2225 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2226 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2227 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2228 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2229 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2230 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2231 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2232 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2233 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2234 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2235 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2236 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2237 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2238 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2239 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2240 /* Teradici */
2241 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2242 { 0, }
2243 };
2244 MODULE_DEVICE_TABLE(pci, azx_ids);
2245
2246 /* pci_driver definition */
2247 static struct pci_driver driver = {
2248 .name = "HDA Intel",
2249 .id_table = azx_ids,
2250 .probe = azx_probe,
2251 .remove = __devexit_p(azx_remove),
2252 #ifdef CONFIG_PM
2253 .suspend = azx_suspend,
2254 .resume = azx_resume,
2255 #endif
2256 };
2257
2258 static int __init alsa_card_azx_init(void)
2259 {
2260 return pci_register_driver(&driver);
2261 }
2262
2263 static void __exit alsa_card_azx_exit(void)
2264 {
2265 pci_unregister_driver(&driver);
2266 }
2267
2268 module_init(alsa_card_azx_init)
2269 module_exit(alsa_card_azx_exit)
linux kernel for loongson