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BUG_ON() Conversion in drivers/net/
[linux-2.6/linux-loongson.git] / drivers / net / b44.c
blobc4e12b5cbb92c2f4cb2412e7ece8d22151c902df
1 /* b44.c: Broadcom 4400 device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
5 *
6 * Distribute under GPL.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/dma-mapping.h>
22
23 #include <asm/uaccess.h>
24 #include <asm/io.h>
25 #include <asm/irq.h>
26
27 #include "b44.h"
28
29 #define DRV_MODULE_NAME "b44"
30 #define PFX DRV_MODULE_NAME ": "
31 #define DRV_MODULE_VERSION "0.97"
32 #define DRV_MODULE_RELDATE "Nov 30, 2005"
33
34 #define B44_DEF_MSG_ENABLE \
35 (NETIF_MSG_DRV | \
36 NETIF_MSG_PROBE | \
37 NETIF_MSG_LINK | \
38 NETIF_MSG_TIMER | \
39 NETIF_MSG_IFDOWN | \
40 NETIF_MSG_IFUP | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR)
43
44 /* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
46 */
47 #define B44_TX_TIMEOUT (5 * HZ)
48
49 /* hardware minimum and maximum for a single frame's data payload */
50 #define B44_MIN_MTU 60
51 #define B44_MAX_MTU 1500
52
53 #define B44_RX_RING_SIZE 512
54 #define B44_DEF_RX_RING_PENDING 200
55 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
56 B44_RX_RING_SIZE)
57 #define B44_TX_RING_SIZE 512
58 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
60 B44_TX_RING_SIZE)
61 #define B44_DMA_MASK 0x3fffffff
62
63 #define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65 #define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
70
71 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
73
74 /* minimum number of free TX descriptors required to wake up TX process */
75 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
76
77 static char version[] __devinitdata =
78 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79
80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84
85 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86 module_param(b44_debug, int, 0);
87 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
88
89 static struct pci_device_id b44_pci_tbl[] = {
90 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
94 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
96 { } /* terminate list with empty entry */
97 };
98
99 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
100
101 static void b44_halt(struct b44 *);
102 static void b44_init_rings(struct b44 *);
103 static void b44_init_hw(struct b44 *);
104
105 static int dma_desc_align_mask;
106 static int dma_desc_sync_size;
107
108 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
109 #define _B44(x...) # x,
110 B44_STAT_REG_DECLARE
111 #undef _B44
112 };
113
114 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
115 dma_addr_t dma_base,
116 unsigned long offset,
117 enum dma_data_direction dir)
118 {
119 dma_sync_single_range_for_device(&pdev->dev, dma_base,
120 offset & dma_desc_align_mask,
121 dma_desc_sync_size, dir);
122 }
123
124 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
125 dma_addr_t dma_base,
126 unsigned long offset,
127 enum dma_data_direction dir)
128 {
129 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
130 offset & dma_desc_align_mask,
131 dma_desc_sync_size, dir);
132 }
133
134 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
135 {
136 return readl(bp->regs + reg);
137 }
138
139 static inline void bw32(const struct b44 *bp,
140 unsigned long reg, unsigned long val)
141 {
142 writel(val, bp->regs + reg);
143 }
144
145 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
146 u32 bit, unsigned long timeout, const int clear)
147 {
148 unsigned long i;
149
150 for (i = 0; i < timeout; i++) {
151 u32 val = br32(bp, reg);
152
153 if (clear && !(val & bit))
154 break;
155 if (!clear && (val & bit))
156 break;
157 udelay(10);
158 }
159 if (i == timeout) {
160 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
161 "%lx to %s.\n",
162 bp->dev->name,
163 bit, reg,
164 (clear ? "clear" : "set"));
165 return -ENODEV;
166 }
167 return 0;
168 }
169
170 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
171 * buzz words used on this company's website :-)
172 *
173 * All of these routines must be invoked with bp->lock held and
174 * interrupts disabled.
175 */
176
177 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
178 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
179
180 static u32 ssb_get_core_rev(struct b44 *bp)
181 {
182 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
183 }
184
185 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
186 {
187 u32 bar_orig, pci_rev, val;
188
189 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
190 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
191 pci_rev = ssb_get_core_rev(bp);
192
193 val = br32(bp, B44_SBINTVEC);
194 val |= cores;
195 bw32(bp, B44_SBINTVEC, val);
196
197 val = br32(bp, SSB_PCI_TRANS_2);
198 val |= SSB_PCI_PREF | SSB_PCI_BURST;
199 bw32(bp, SSB_PCI_TRANS_2, val);
200
201 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
202
203 return pci_rev;
204 }
205
206 static void ssb_core_disable(struct b44 *bp)
207 {
208 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
209 return;
210
211 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
212 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
213 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
214 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
215 SBTMSLOW_REJECT | SBTMSLOW_RESET));
216 br32(bp, B44_SBTMSLOW);
217 udelay(1);
218 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
219 br32(bp, B44_SBTMSLOW);
220 udelay(1);
221 }
222
223 static void ssb_core_reset(struct b44 *bp)
224 {
225 u32 val;
226
227 ssb_core_disable(bp);
228 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
229 br32(bp, B44_SBTMSLOW);
230 udelay(1);
231
232 /* Clear SERR if set, this is a hw bug workaround. */
233 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
234 bw32(bp, B44_SBTMSHIGH, 0);
235
236 val = br32(bp, B44_SBIMSTATE);
237 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
238 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
239
240 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
241 br32(bp, B44_SBTMSLOW);
242 udelay(1);
243
244 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
245 br32(bp, B44_SBTMSLOW);
246 udelay(1);
247 }
248
249 static int ssb_core_unit(struct b44 *bp)
250 {
251 #if 0
252 u32 val = br32(bp, B44_SBADMATCH0);
253 u32 base;
254
255 type = val & SBADMATCH0_TYPE_MASK;
256 switch (type) {
257 case 0:
258 base = val & SBADMATCH0_BS0_MASK;
259 break;
260
261 case 1:
262 base = val & SBADMATCH0_BS1_MASK;
263 break;
264
265 case 2:
266 default:
267 base = val & SBADMATCH0_BS2_MASK;
268 break;
269 };
270 #endif
271 return 0;
272 }
273
274 static int ssb_is_core_up(struct b44 *bp)
275 {
276 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
277 == SBTMSLOW_CLOCK);
278 }
279
280 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
281 {
282 u32 val;
283
284 val = ((u32) data[2]) << 24;
285 val |= ((u32) data[3]) << 16;
286 val |= ((u32) data[4]) << 8;
287 val |= ((u32) data[5]) << 0;
288 bw32(bp, B44_CAM_DATA_LO, val);
289 val = (CAM_DATA_HI_VALID |
290 (((u32) data[0]) << 8) |
291 (((u32) data[1]) << 0));
292 bw32(bp, B44_CAM_DATA_HI, val);
293 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
294 (index << CAM_CTRL_INDEX_SHIFT)));
295 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
296 }
297
298 static inline void __b44_disable_ints(struct b44 *bp)
299 {
300 bw32(bp, B44_IMASK, 0);
301 }
302
303 static void b44_disable_ints(struct b44 *bp)
304 {
305 __b44_disable_ints(bp);
306
307 /* Flush posted writes. */
308 br32(bp, B44_IMASK);
309 }
310
311 static void b44_enable_ints(struct b44 *bp)
312 {
313 bw32(bp, B44_IMASK, bp->imask);
314 }
315
316 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
317 {
318 int err;
319
320 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
321 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
322 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
323 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
324 (reg << MDIO_DATA_RA_SHIFT) |
325 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
326 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
327 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
328
329 return err;
330 }
331
332 static int b44_writephy(struct b44 *bp, int reg, u32 val)
333 {
334 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
335 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
336 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
337 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
338 (reg << MDIO_DATA_RA_SHIFT) |
339 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
340 (val & MDIO_DATA_DATA)));
341 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
342 }
343
344 /* miilib interface */
345 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
346 * due to code existing before miilib use was added to this driver.
347 * Someone should remove this artificial driver limitation in
348 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
349 */
350 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
351 {
352 u32 val;
353 struct b44 *bp = netdev_priv(dev);
354 int rc = b44_readphy(bp, location, &val);
355 if (rc)
356 return 0xffffffff;
357 return val;
358 }
359
360 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
361 int val)
362 {
363 struct b44 *bp = netdev_priv(dev);
364 b44_writephy(bp, location, val);
365 }
366
367 static int b44_phy_reset(struct b44 *bp)
368 {
369 u32 val;
370 int err;
371
372 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
373 if (err)
374 return err;
375 udelay(100);
376 err = b44_readphy(bp, MII_BMCR, &val);
377 if (!err) {
378 if (val & BMCR_RESET) {
379 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
380 bp->dev->name);
381 err = -ENODEV;
382 }
383 }
384
385 return 0;
386 }
387
388 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
389 {
390 u32 val;
391
392 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
393 bp->flags |= pause_flags;
394
395 val = br32(bp, B44_RXCONFIG);
396 if (pause_flags & B44_FLAG_RX_PAUSE)
397 val |= RXCONFIG_FLOW;
398 else
399 val &= ~RXCONFIG_FLOW;
400 bw32(bp, B44_RXCONFIG, val);
401
402 val = br32(bp, B44_MAC_FLOW);
403 if (pause_flags & B44_FLAG_TX_PAUSE)
404 val |= (MAC_FLOW_PAUSE_ENAB |
405 (0xc0 & MAC_FLOW_RX_HI_WATER));
406 else
407 val &= ~MAC_FLOW_PAUSE_ENAB;
408 bw32(bp, B44_MAC_FLOW, val);
409 }
410
411 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
412 {
413 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
414 B44_FLAG_RX_PAUSE);
415
416 if (local & ADVERTISE_PAUSE_CAP) {
417 if (local & ADVERTISE_PAUSE_ASYM) {
418 if (remote & LPA_PAUSE_CAP)
419 pause_enab |= (B44_FLAG_TX_PAUSE |
420 B44_FLAG_RX_PAUSE);
421 else if (remote & LPA_PAUSE_ASYM)
422 pause_enab |= B44_FLAG_RX_PAUSE;
423 } else {
424 if (remote & LPA_PAUSE_CAP)
425 pause_enab |= (B44_FLAG_TX_PAUSE |
426 B44_FLAG_RX_PAUSE);
427 }
428 } else if (local & ADVERTISE_PAUSE_ASYM) {
429 if ((remote & LPA_PAUSE_CAP) &&
430 (remote & LPA_PAUSE_ASYM))
431 pause_enab |= B44_FLAG_TX_PAUSE;
432 }
433
434 __b44_set_flow_ctrl(bp, pause_enab);
435 }
436
437 static int b44_setup_phy(struct b44 *bp)
438 {
439 u32 val;
440 int err;
441
442 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
443 goto out;
444 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
445 val & MII_ALEDCTRL_ALLMSK)) != 0)
446 goto out;
447 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
448 goto out;
449 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
450 val | MII_TLEDCTRL_ENABLE)) != 0)
451 goto out;
452
453 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
454 u32 adv = ADVERTISE_CSMA;
455
456 if (bp->flags & B44_FLAG_ADV_10HALF)
457 adv |= ADVERTISE_10HALF;
458 if (bp->flags & B44_FLAG_ADV_10FULL)
459 adv |= ADVERTISE_10FULL;
460 if (bp->flags & B44_FLAG_ADV_100HALF)
461 adv |= ADVERTISE_100HALF;
462 if (bp->flags & B44_FLAG_ADV_100FULL)
463 adv |= ADVERTISE_100FULL;
464
465 if (bp->flags & B44_FLAG_PAUSE_AUTO)
466 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
467
468 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
469 goto out;
470 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
471 BMCR_ANRESTART))) != 0)
472 goto out;
473 } else {
474 u32 bmcr;
475
476 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
477 goto out;
478 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
479 if (bp->flags & B44_FLAG_100_BASE_T)
480 bmcr |= BMCR_SPEED100;
481 if (bp->flags & B44_FLAG_FULL_DUPLEX)
482 bmcr |= BMCR_FULLDPLX;
483 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
484 goto out;
485
486 /* Since we will not be negotiating there is no safe way
487 * to determine if the link partner supports flow control
488 * or not. So just disable it completely in this case.
489 */
490 b44_set_flow_ctrl(bp, 0, 0);
491 }
492
493 out:
494 return err;
495 }
496
497 static void b44_stats_update(struct b44 *bp)
498 {
499 unsigned long reg;
500 u32 *val;
501
502 val = &bp->hw_stats.tx_good_octets;
503 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
504 *val++ += br32(bp, reg);
505 }
506
507 /* Pad */
508 reg += 8*4UL;
509
510 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
511 *val++ += br32(bp, reg);
512 }
513 }
514
515 static void b44_link_report(struct b44 *bp)
516 {
517 if (!netif_carrier_ok(bp->dev)) {
518 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
519 } else {
520 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
521 bp->dev->name,
522 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
523 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
524
525 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
526 "%s for RX.\n",
527 bp->dev->name,
528 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
529 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
530 }
531 }
532
533 static void b44_check_phy(struct b44 *bp)
534 {
535 u32 bmsr, aux;
536
537 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
538 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
539 (bmsr != 0xffff)) {
540 if (aux & MII_AUXCTRL_SPEED)
541 bp->flags |= B44_FLAG_100_BASE_T;
542 else
543 bp->flags &= ~B44_FLAG_100_BASE_T;
544 if (aux & MII_AUXCTRL_DUPLEX)
545 bp->flags |= B44_FLAG_FULL_DUPLEX;
546 else
547 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
548
549 if (!netif_carrier_ok(bp->dev) &&
550 (bmsr & BMSR_LSTATUS)) {
551 u32 val = br32(bp, B44_TX_CTRL);
552 u32 local_adv, remote_adv;
553
554 if (bp->flags & B44_FLAG_FULL_DUPLEX)
555 val |= TX_CTRL_DUPLEX;
556 else
557 val &= ~TX_CTRL_DUPLEX;
558 bw32(bp, B44_TX_CTRL, val);
559
560 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
561 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
562 !b44_readphy(bp, MII_LPA, &remote_adv))
563 b44_set_flow_ctrl(bp, local_adv, remote_adv);
564
565 /* Link now up */
566 netif_carrier_on(bp->dev);
567 b44_link_report(bp);
568 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
569 /* Link now down */
570 netif_carrier_off(bp->dev);
571 b44_link_report(bp);
572 }
573
574 if (bmsr & BMSR_RFAULT)
575 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
576 bp->dev->name);
577 if (bmsr & BMSR_JCD)
578 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
579 bp->dev->name);
580 }
581 }
582
583 static void b44_timer(unsigned long __opaque)
584 {
585 struct b44 *bp = (struct b44 *) __opaque;
586
587 spin_lock_irq(&bp->lock);
588
589 b44_check_phy(bp);
590
591 b44_stats_update(bp);
592
593 spin_unlock_irq(&bp->lock);
594
595 bp->timer.expires = jiffies + HZ;
596 add_timer(&bp->timer);
597 }
598
599 static void b44_tx(struct b44 *bp)
600 {
601 u32 cur, cons;
602
603 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
604 cur /= sizeof(struct dma_desc);
605
606 /* XXX needs updating when NETIF_F_SG is supported */
607 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
608 struct ring_info *rp = &bp->tx_buffers[cons];
609 struct sk_buff *skb = rp->skb;
610
611 BUG_ON(skb == NULL);
612
613 pci_unmap_single(bp->pdev,
614 pci_unmap_addr(rp, mapping),
615 skb->len,
616 PCI_DMA_TODEVICE);
617 rp->skb = NULL;
618 dev_kfree_skb_irq(skb);
619 }
620
621 bp->tx_cons = cons;
622 if (netif_queue_stopped(bp->dev) &&
623 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
624 netif_wake_queue(bp->dev);
625
626 bw32(bp, B44_GPTIMER, 0);
627 }
628
629 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
630 * before the DMA address you give it. So we allocate 30 more bytes
631 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
632 * point the chip at 30 bytes past where the rx_header will go.
633 */
634 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
635 {
636 struct dma_desc *dp;
637 struct ring_info *src_map, *map;
638 struct rx_header *rh;
639 struct sk_buff *skb;
640 dma_addr_t mapping;
641 int dest_idx;
642 u32 ctrl;
643
644 src_map = NULL;
645 if (src_idx >= 0)
646 src_map = &bp->rx_buffers[src_idx];
647 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
648 map = &bp->rx_buffers[dest_idx];
649 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
650 if (skb == NULL)
651 return -ENOMEM;
652
653 mapping = pci_map_single(bp->pdev, skb->data,
654 RX_PKT_BUF_SZ,
655 PCI_DMA_FROMDEVICE);
656
657 /* Hardware bug work-around, the chip is unable to do PCI DMA
658 to/from anything above 1GB :-( */
659 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
660 /* Sigh... */
661 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
662 dev_kfree_skb_any(skb);
663 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
664 if (skb == NULL)
665 return -ENOMEM;
666 mapping = pci_map_single(bp->pdev, skb->data,
667 RX_PKT_BUF_SZ,
668 PCI_DMA_FROMDEVICE);
669 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
670 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
671 dev_kfree_skb_any(skb);
672 return -ENOMEM;
673 }
674 }
675
676 skb->dev = bp->dev;
677 skb_reserve(skb, bp->rx_offset);
678
679 rh = (struct rx_header *)
680 (skb->data - bp->rx_offset);
681 rh->len = 0;
682 rh->flags = 0;
683
684 map->skb = skb;
685 pci_unmap_addr_set(map, mapping, mapping);
686
687 if (src_map != NULL)
688 src_map->skb = NULL;
689
690 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
691 if (dest_idx == (B44_RX_RING_SIZE - 1))
692 ctrl |= DESC_CTRL_EOT;
693
694 dp = &bp->rx_ring[dest_idx];
695 dp->ctrl = cpu_to_le32(ctrl);
696 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
697
698 if (bp->flags & B44_FLAG_RX_RING_HACK)
699 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
700 dest_idx * sizeof(dp),
701 DMA_BIDIRECTIONAL);
702
703 return RX_PKT_BUF_SZ;
704 }
705
706 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
707 {
708 struct dma_desc *src_desc, *dest_desc;
709 struct ring_info *src_map, *dest_map;
710 struct rx_header *rh;
711 int dest_idx;
712 u32 ctrl;
713
714 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
715 dest_desc = &bp->rx_ring[dest_idx];
716 dest_map = &bp->rx_buffers[dest_idx];
717 src_desc = &bp->rx_ring[src_idx];
718 src_map = &bp->rx_buffers[src_idx];
719
720 dest_map->skb = src_map->skb;
721 rh = (struct rx_header *) src_map->skb->data;
722 rh->len = 0;
723 rh->flags = 0;
724 pci_unmap_addr_set(dest_map, mapping,
725 pci_unmap_addr(src_map, mapping));
726
727 if (bp->flags & B44_FLAG_RX_RING_HACK)
728 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
729 src_idx * sizeof(src_desc),
730 DMA_BIDIRECTIONAL);
731
732 ctrl = src_desc->ctrl;
733 if (dest_idx == (B44_RX_RING_SIZE - 1))
734 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
735 else
736 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
737
738 dest_desc->ctrl = ctrl;
739 dest_desc->addr = src_desc->addr;
740
741 src_map->skb = NULL;
742
743 if (bp->flags & B44_FLAG_RX_RING_HACK)
744 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
745 dest_idx * sizeof(dest_desc),
746 DMA_BIDIRECTIONAL);
747
748 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
749 RX_PKT_BUF_SZ,
750 PCI_DMA_FROMDEVICE);
751 }
752
753 static int b44_rx(struct b44 *bp, int budget)
754 {
755 int received;
756 u32 cons, prod;
757
758 received = 0;
759 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
760 prod /= sizeof(struct dma_desc);
761 cons = bp->rx_cons;
762
763 while (cons != prod && budget > 0) {
764 struct ring_info *rp = &bp->rx_buffers[cons];
765 struct sk_buff *skb = rp->skb;
766 dma_addr_t map = pci_unmap_addr(rp, mapping);
767 struct rx_header *rh;
768 u16 len;
769
770 pci_dma_sync_single_for_cpu(bp->pdev, map,
771 RX_PKT_BUF_SZ,
772 PCI_DMA_FROMDEVICE);
773 rh = (struct rx_header *) skb->data;
774 len = cpu_to_le16(rh->len);
775 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
776 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
777 drop_it:
778 b44_recycle_rx(bp, cons, bp->rx_prod);
779 drop_it_no_recycle:
780 bp->stats.rx_dropped++;
781 goto next_pkt;
782 }
783
784 if (len == 0) {
785 int i = 0;
786
787 do {
788 udelay(2);
789 barrier();
790 len = cpu_to_le16(rh->len);
791 } while (len == 0 && i++ < 5);
792 if (len == 0)
793 goto drop_it;
794 }
795
796 /* Omit CRC. */
797 len -= 4;
798
799 if (len > RX_COPY_THRESHOLD) {
800 int skb_size;
801 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
802 if (skb_size < 0)
803 goto drop_it;
804 pci_unmap_single(bp->pdev, map,
805 skb_size, PCI_DMA_FROMDEVICE);
806 /* Leave out rx_header */
807 skb_put(skb, len+bp->rx_offset);
808 skb_pull(skb,bp->rx_offset);
809 } else {
810 struct sk_buff *copy_skb;
811
812 b44_recycle_rx(bp, cons, bp->rx_prod);
813 copy_skb = dev_alloc_skb(len + 2);
814 if (copy_skb == NULL)
815 goto drop_it_no_recycle;
816
817 copy_skb->dev = bp->dev;
818 skb_reserve(copy_skb, 2);
819 skb_put(copy_skb, len);
820 /* DMA sync done above, copy just the actual packet */
821 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
822
823 skb = copy_skb;
824 }
825 skb->ip_summed = CHECKSUM_NONE;
826 skb->protocol = eth_type_trans(skb, bp->dev);
827 netif_receive_skb(skb);
828 bp->dev->last_rx = jiffies;
829 received++;
830 budget--;
831 next_pkt:
832 bp->rx_prod = (bp->rx_prod + 1) &
833 (B44_RX_RING_SIZE - 1);
834 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
835 }
836
837 bp->rx_cons = cons;
838 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
839
840 return received;
841 }
842
843 static int b44_poll(struct net_device *netdev, int *budget)
844 {
845 struct b44 *bp = netdev_priv(netdev);
846 int done;
847
848 spin_lock_irq(&bp->lock);
849
850 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
851 /* spin_lock(&bp->tx_lock); */
852 b44_tx(bp);
853 /* spin_unlock(&bp->tx_lock); */
854 }
855 spin_unlock_irq(&bp->lock);
856
857 done = 1;
858 if (bp->istat & ISTAT_RX) {
859 int orig_budget = *budget;
860 int work_done;
861
862 if (orig_budget > netdev->quota)
863 orig_budget = netdev->quota;
864
865 work_done = b44_rx(bp, orig_budget);
866
867 *budget -= work_done;
868 netdev->quota -= work_done;
869
870 if (work_done >= orig_budget)
871 done = 0;
872 }
873
874 if (bp->istat & ISTAT_ERRORS) {
875 spin_lock_irq(&bp->lock);
876 b44_halt(bp);
877 b44_init_rings(bp);
878 b44_init_hw(bp);
879 netif_wake_queue(bp->dev);
880 spin_unlock_irq(&bp->lock);
881 done = 1;
882 }
883
884 if (done) {
885 netif_rx_complete(netdev);
886 b44_enable_ints(bp);
887 }
888
889 return (done ? 0 : 1);
890 }
891
892 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
893 {
894 struct net_device *dev = dev_id;
895 struct b44 *bp = netdev_priv(dev);
896 u32 istat, imask;
897 int handled = 0;
898
899 spin_lock(&bp->lock);
900
901 istat = br32(bp, B44_ISTAT);
902 imask = br32(bp, B44_IMASK);
903
904 /* ??? What the fuck is the purpose of the interrupt mask
905 * ??? register if we have to mask it out by hand anyways?
906 */
907 istat &= imask;
908 if (istat) {
909 handled = 1;
910
911 if (unlikely(!netif_running(dev))) {
912 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
913 goto irq_ack;
914 }
915
916 if (netif_rx_schedule_prep(dev)) {
917 /* NOTE: These writes are posted by the readback of
918 * the ISTAT register below.
919 */
920 bp->istat = istat;
921 __b44_disable_ints(bp);
922 __netif_rx_schedule(dev);
923 } else {
924 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
925 dev->name);
926 }
927
928 irq_ack:
929 bw32(bp, B44_ISTAT, istat);
930 br32(bp, B44_ISTAT);
931 }
932 spin_unlock(&bp->lock);
933 return IRQ_RETVAL(handled);
934 }
935
936 static void b44_tx_timeout(struct net_device *dev)
937 {
938 struct b44 *bp = netdev_priv(dev);
939
940 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
941 dev->name);
942
943 spin_lock_irq(&bp->lock);
944
945 b44_halt(bp);
946 b44_init_rings(bp);
947 b44_init_hw(bp);
948
949 spin_unlock_irq(&bp->lock);
950
951 b44_enable_ints(bp);
952
953 netif_wake_queue(dev);
954 }
955
956 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
957 {
958 struct b44 *bp = netdev_priv(dev);
959 struct sk_buff *bounce_skb;
960 int rc = NETDEV_TX_OK;
961 dma_addr_t mapping;
962 u32 len, entry, ctrl;
963
964 len = skb->len;
965 spin_lock_irq(&bp->lock);
966
967 /* This is a hard error, log it. */
968 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
969 netif_stop_queue(dev);
970 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
971 dev->name);
972 goto err_out;
973 }
974
975 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
976 if (mapping + len > B44_DMA_MASK) {
977 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
978 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
979
980 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
981 GFP_ATOMIC|GFP_DMA);
982 if (!bounce_skb)
983 goto err_out;
984
985 mapping = pci_map_single(bp->pdev, bounce_skb->data,
986 len, PCI_DMA_TODEVICE);
987 if (mapping + len > B44_DMA_MASK) {
988 pci_unmap_single(bp->pdev, mapping,
989 len, PCI_DMA_TODEVICE);
990 dev_kfree_skb_any(bounce_skb);
991 goto err_out;
992 }
993
994 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
995 dev_kfree_skb_any(skb);
996 skb = bounce_skb;
997 }
998
999 entry = bp->tx_prod;
1000 bp->tx_buffers[entry].skb = skb;
1001 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
1002
1003 ctrl = (len & DESC_CTRL_LEN);
1004 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1005 if (entry == (B44_TX_RING_SIZE - 1))
1006 ctrl |= DESC_CTRL_EOT;
1007
1008 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1009 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1010
1011 if (bp->flags & B44_FLAG_TX_RING_HACK)
1012 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1013 entry * sizeof(bp->tx_ring[0]),
1014 DMA_TO_DEVICE);
1015
1016 entry = NEXT_TX(entry);
1017
1018 bp->tx_prod = entry;
1019
1020 wmb();
1021
1022 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1023 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1024 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1025 if (bp->flags & B44_FLAG_REORDER_BUG)
1026 br32(bp, B44_DMATX_PTR);
1027
1028 if (TX_BUFFS_AVAIL(bp) < 1)
1029 netif_stop_queue(dev);
1030
1031 dev->trans_start = jiffies;
1032
1033 out_unlock:
1034 spin_unlock_irq(&bp->lock);
1035
1036 return rc;
1037
1038 err_out:
1039 rc = NETDEV_TX_BUSY;
1040 goto out_unlock;
1041 }
1042
1043 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1044 {
1045 struct b44 *bp = netdev_priv(dev);
1046
1047 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1048 return -EINVAL;
1049
1050 if (!netif_running(dev)) {
1051 /* We'll just catch it later when the
1052 * device is up'd.
1053 */
1054 dev->mtu = new_mtu;
1055 return 0;
1056 }
1057
1058 spin_lock_irq(&bp->lock);
1059 b44_halt(bp);
1060 dev->mtu = new_mtu;
1061 b44_init_rings(bp);
1062 b44_init_hw(bp);
1063 spin_unlock_irq(&bp->lock);
1064
1065 b44_enable_ints(bp);
1066
1067 return 0;
1068 }
1069
1070 /* Free up pending packets in all rx/tx rings.
1071 *
1072 * The chip has been shut down and the driver detached from
1073 * the networking, so no interrupts or new tx packets will
1074 * end up in the driver. bp->lock is not held and we are not
1075 * in an interrupt context and thus may sleep.
1076 */
1077 static void b44_free_rings(struct b44 *bp)
1078 {
1079 struct ring_info *rp;
1080 int i;
1081
1082 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1083 rp = &bp->rx_buffers[i];
1084
1085 if (rp->skb == NULL)
1086 continue;
1087 pci_unmap_single(bp->pdev,
1088 pci_unmap_addr(rp, mapping),
1089 RX_PKT_BUF_SZ,
1090 PCI_DMA_FROMDEVICE);
1091 dev_kfree_skb_any(rp->skb);
1092 rp->skb = NULL;
1093 }
1094
1095 /* XXX needs changes once NETIF_F_SG is set... */
1096 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1097 rp = &bp->tx_buffers[i];
1098
1099 if (rp->skb == NULL)
1100 continue;
1101 pci_unmap_single(bp->pdev,
1102 pci_unmap_addr(rp, mapping),
1103 rp->skb->len,
1104 PCI_DMA_TODEVICE);
1105 dev_kfree_skb_any(rp->skb);
1106 rp->skb = NULL;
1107 }
1108 }
1109
1110 /* Initialize tx/rx rings for packet processing.
1111 *
1112 * The chip has been shut down and the driver detached from
1113 * the networking, so no interrupts or new tx packets will
1114 * end up in the driver.
1115 */
1116 static void b44_init_rings(struct b44 *bp)
1117 {
1118 int i;
1119
1120 b44_free_rings(bp);
1121
1122 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1123 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1124
1125 if (bp->flags & B44_FLAG_RX_RING_HACK)
1126 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1127 DMA_TABLE_BYTES,
1128 PCI_DMA_BIDIRECTIONAL);
1129
1130 if (bp->flags & B44_FLAG_TX_RING_HACK)
1131 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1132 DMA_TABLE_BYTES,
1133 PCI_DMA_TODEVICE);
1134
1135 for (i = 0; i < bp->rx_pending; i++) {
1136 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1137 break;
1138 }
1139 }
1140
1141 /*
1142 * Must not be invoked with interrupt sources disabled and
1143 * the hardware shutdown down.
1144 */
1145 static void b44_free_consistent(struct b44 *bp)
1146 {
1147 kfree(bp->rx_buffers);
1148 bp->rx_buffers = NULL;
1149 kfree(bp->tx_buffers);
1150 bp->tx_buffers = NULL;
1151 if (bp->rx_ring) {
1152 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1153 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1154 DMA_TABLE_BYTES,
1155 DMA_BIDIRECTIONAL);
1156 kfree(bp->rx_ring);
1157 } else
1158 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1159 bp->rx_ring, bp->rx_ring_dma);
1160 bp->rx_ring = NULL;
1161 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1162 }
1163 if (bp->tx_ring) {
1164 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1165 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1166 DMA_TABLE_BYTES,
1167 DMA_TO_DEVICE);
1168 kfree(bp->tx_ring);
1169 } else
1170 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1171 bp->tx_ring, bp->tx_ring_dma);
1172 bp->tx_ring = NULL;
1173 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1174 }
1175 }
1176
1177 /*
1178 * Must not be invoked with interrupt sources disabled and
1179 * the hardware shutdown down. Can sleep.
1180 */
1181 static int b44_alloc_consistent(struct b44 *bp)
1182 {
1183 int size;
1184
1185 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1186 bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1187 if (!bp->rx_buffers)
1188 goto out_err;
1189
1190 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1191 bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1192 if (!bp->tx_buffers)
1193 goto out_err;
1194
1195 size = DMA_TABLE_BYTES;
1196 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1197 if (!bp->rx_ring) {
1198 /* Allocation may have failed due to pci_alloc_consistent
1199 insisting on use of GFP_DMA, which is more restrictive
1200 than necessary... */
1201 struct dma_desc *rx_ring;
1202 dma_addr_t rx_ring_dma;
1203
1204 rx_ring = kzalloc(size, GFP_KERNEL);
1205 if (!rx_ring)
1206 goto out_err;
1207
1208 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1209 DMA_TABLE_BYTES,
1210 DMA_BIDIRECTIONAL);
1211
1212 if (rx_ring_dma + size > B44_DMA_MASK) {
1213 kfree(rx_ring);
1214 goto out_err;
1215 }
1216
1217 bp->rx_ring = rx_ring;
1218 bp->rx_ring_dma = rx_ring_dma;
1219 bp->flags |= B44_FLAG_RX_RING_HACK;
1220 }
1221
1222 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1223 if (!bp->tx_ring) {
1224 /* Allocation may have failed due to pci_alloc_consistent
1225 insisting on use of GFP_DMA, which is more restrictive
1226 than necessary... */
1227 struct dma_desc *tx_ring;
1228 dma_addr_t tx_ring_dma;
1229
1230 tx_ring = kzalloc(size, GFP_KERNEL);
1231 if (!tx_ring)
1232 goto out_err;
1233
1234 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1235 DMA_TABLE_BYTES,
1236 DMA_TO_DEVICE);
1237
1238 if (tx_ring_dma + size > B44_DMA_MASK) {
1239 kfree(tx_ring);
1240 goto out_err;
1241 }
1242
1243 bp->tx_ring = tx_ring;
1244 bp->tx_ring_dma = tx_ring_dma;
1245 bp->flags |= B44_FLAG_TX_RING_HACK;
1246 }
1247
1248 return 0;
1249
1250 out_err:
1251 b44_free_consistent(bp);
1252 return -ENOMEM;
1253 }
1254
1255 /* bp->lock is held. */
1256 static void b44_clear_stats(struct b44 *bp)
1257 {
1258 unsigned long reg;
1259
1260 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1261 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1262 br32(bp, reg);
1263 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1264 br32(bp, reg);
1265 }
1266
1267 /* bp->lock is held. */
1268 static void b44_chip_reset(struct b44 *bp)
1269 {
1270 if (ssb_is_core_up(bp)) {
1271 bw32(bp, B44_RCV_LAZY, 0);
1272 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1273 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1274 bw32(bp, B44_DMATX_CTRL, 0);
1275 bp->tx_prod = bp->tx_cons = 0;
1276 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1277 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1278 100, 0);
1279 }
1280 bw32(bp, B44_DMARX_CTRL, 0);
1281 bp->rx_prod = bp->rx_cons = 0;
1282 } else {
1283 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1284 SBINTVEC_ENET0 :
1285 SBINTVEC_ENET1));
1286 }
1287
1288 ssb_core_reset(bp);
1289
1290 b44_clear_stats(bp);
1291
1292 /* Make PHY accessible. */
1293 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1294 (0x0d & MDIO_CTRL_MAXF_MASK)));
1295 br32(bp, B44_MDIO_CTRL);
1296
1297 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1298 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1299 br32(bp, B44_ENET_CTRL);
1300 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1301 } else {
1302 u32 val = br32(bp, B44_DEVCTRL);
1303
1304 if (val & DEVCTRL_EPR) {
1305 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1306 br32(bp, B44_DEVCTRL);
1307 udelay(100);
1308 }
1309 bp->flags |= B44_FLAG_INTERNAL_PHY;
1310 }
1311 }
1312
1313 /* bp->lock is held. */
1314 static void b44_halt(struct b44 *bp)
1315 {
1316 b44_disable_ints(bp);
1317 b44_chip_reset(bp);
1318 }
1319
1320 /* bp->lock is held. */
1321 static void __b44_set_mac_addr(struct b44 *bp)
1322 {
1323 bw32(bp, B44_CAM_CTRL, 0);
1324 if (!(bp->dev->flags & IFF_PROMISC)) {
1325 u32 val;
1326
1327 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1328 val = br32(bp, B44_CAM_CTRL);
1329 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1330 }
1331 }
1332
1333 static int b44_set_mac_addr(struct net_device *dev, void *p)
1334 {
1335 struct b44 *bp = netdev_priv(dev);
1336 struct sockaddr *addr = p;
1337
1338 if (netif_running(dev))
1339 return -EBUSY;
1340
1341 if (!is_valid_ether_addr(addr->sa_data))
1342 return -EINVAL;
1343
1344 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1345
1346 spin_lock_irq(&bp->lock);
1347 __b44_set_mac_addr(bp);
1348 spin_unlock_irq(&bp->lock);
1349
1350 return 0;
1351 }
1352
1353 /* Called at device open time to get the chip ready for
1354 * packet processing. Invoked with bp->lock held.
1355 */
1356 static void __b44_set_rx_mode(struct net_device *);
1357 static void b44_init_hw(struct b44 *bp)
1358 {
1359 u32 val;
1360
1361 b44_chip_reset(bp);
1362 b44_phy_reset(bp);
1363 b44_setup_phy(bp);
1364
1365 /* Enable CRC32, set proper LED modes and power on PHY */
1366 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1367 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1368
1369 /* This sets the MAC address too. */
1370 __b44_set_rx_mode(bp->dev);
1371
1372 /* MTU + eth header + possible VLAN tag + struct rx_header */
1373 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1374 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1375
1376 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1377 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1378 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1379 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1380 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1381 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1382
1383 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1384 bp->rx_prod = bp->rx_pending;
1385
1386 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1387
1388 val = br32(bp, B44_ENET_CTRL);
1389 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1390 }
1391
1392 static int b44_open(struct net_device *dev)
1393 {
1394 struct b44 *bp = netdev_priv(dev);
1395 int err;
1396
1397 err = b44_alloc_consistent(bp);
1398 if (err)
1399 goto out;
1400
1401 b44_init_rings(bp);
1402 b44_init_hw(bp);
1403
1404 b44_check_phy(bp);
1405
1406 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1407 if (unlikely(err < 0)) {
1408 b44_chip_reset(bp);
1409 b44_free_rings(bp);
1410 b44_free_consistent(bp);
1411 goto out;
1412 }
1413
1414 init_timer(&bp->timer);
1415 bp->timer.expires = jiffies + HZ;
1416 bp->timer.data = (unsigned long) bp;
1417 bp->timer.function = b44_timer;
1418 add_timer(&bp->timer);
1419
1420 b44_enable_ints(bp);
1421 netif_start_queue(dev);
1422 out:
1423 return err;
1424 }
1425
1426 #if 0
1427 /*static*/ void b44_dump_state(struct b44 *bp)
1428 {
1429 u32 val32, val32_2, val32_3, val32_4, val32_5;
1430 u16 val16;
1431
1432 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1433 printk("DEBUG: PCI status [%04x] \n", val16);
1434
1435 }
1436 #endif
1437
1438 #ifdef CONFIG_NET_POLL_CONTROLLER
1439 /*
1440 * Polling receive - used by netconsole and other diagnostic tools
1441 * to allow network i/o with interrupts disabled.
1442 */
1443 static void b44_poll_controller(struct net_device *dev)
1444 {
1445 disable_irq(dev->irq);
1446 b44_interrupt(dev->irq, dev, NULL);
1447 enable_irq(dev->irq);
1448 }
1449 #endif
1450
1451 static int b44_close(struct net_device *dev)
1452 {
1453 struct b44 *bp = netdev_priv(dev);
1454
1455 netif_stop_queue(dev);
1456
1457 netif_poll_disable(dev);
1458
1459 del_timer_sync(&bp->timer);
1460
1461 spin_lock_irq(&bp->lock);
1462
1463 #if 0
1464 b44_dump_state(bp);
1465 #endif
1466 b44_halt(bp);
1467 b44_free_rings(bp);
1468 netif_carrier_off(dev);
1469
1470 spin_unlock_irq(&bp->lock);
1471
1472 free_irq(dev->irq, dev);
1473
1474 netif_poll_enable(dev);
1475
1476 b44_free_consistent(bp);
1477
1478 return 0;
1479 }
1480
1481 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1482 {
1483 struct b44 *bp = netdev_priv(dev);
1484 struct net_device_stats *nstat = &bp->stats;
1485 struct b44_hw_stats *hwstat = &bp->hw_stats;
1486
1487 /* Convert HW stats into netdevice stats. */
1488 nstat->rx_packets = hwstat->rx_pkts;
1489 nstat->tx_packets = hwstat->tx_pkts;
1490 nstat->rx_bytes = hwstat->rx_octets;
1491 nstat->tx_bytes = hwstat->tx_octets;
1492 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1493 hwstat->tx_oversize_pkts +
1494 hwstat->tx_underruns +
1495 hwstat->tx_excessive_cols +
1496 hwstat->tx_late_cols);
1497 nstat->multicast = hwstat->tx_multicast_pkts;
1498 nstat->collisions = hwstat->tx_total_cols;
1499
1500 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1501 hwstat->rx_undersize);
1502 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1503 nstat->rx_frame_errors = hwstat->rx_align_errs;
1504 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1505 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1506 hwstat->rx_oversize_pkts +
1507 hwstat->rx_missed_pkts +
1508 hwstat->rx_crc_align_errs +
1509 hwstat->rx_undersize +
1510 hwstat->rx_crc_errs +
1511 hwstat->rx_align_errs +
1512 hwstat->rx_symbol_errs);
1513
1514 nstat->tx_aborted_errors = hwstat->tx_underruns;
1515 #if 0
1516 /* Carrier lost counter seems to be broken for some devices */
1517 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1518 #endif
1519
1520 return nstat;
1521 }
1522
1523 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1524 {
1525 struct dev_mc_list *mclist;
1526 int i, num_ents;
1527
1528 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1529 mclist = dev->mc_list;
1530 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1531 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1532 }
1533 return i+1;
1534 }
1535
1536 static void __b44_set_rx_mode(struct net_device *dev)
1537 {
1538 struct b44 *bp = netdev_priv(dev);
1539 u32 val;
1540
1541 val = br32(bp, B44_RXCONFIG);
1542 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1543 if (dev->flags & IFF_PROMISC) {
1544 val |= RXCONFIG_PROMISC;
1545 bw32(bp, B44_RXCONFIG, val);
1546 } else {
1547 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1548 int i = 0;
1549
1550 __b44_set_mac_addr(bp);
1551
1552 if (dev->flags & IFF_ALLMULTI)
1553 val |= RXCONFIG_ALLMULTI;
1554 else
1555 i = __b44_load_mcast(bp, dev);
1556
1557 for (; i < 64; i++) {
1558 __b44_cam_write(bp, zero, i);
1559 }
1560 bw32(bp, B44_RXCONFIG, val);
1561 val = br32(bp, B44_CAM_CTRL);
1562 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1563 }
1564 }
1565
1566 static void b44_set_rx_mode(struct net_device *dev)
1567 {
1568 struct b44 *bp = netdev_priv(dev);
1569
1570 spin_lock_irq(&bp->lock);
1571 __b44_set_rx_mode(dev);
1572 spin_unlock_irq(&bp->lock);
1573 }
1574
1575 static u32 b44_get_msglevel(struct net_device *dev)
1576 {
1577 struct b44 *bp = netdev_priv(dev);
1578 return bp->msg_enable;
1579 }
1580
1581 static void b44_set_msglevel(struct net_device *dev, u32 value)
1582 {
1583 struct b44 *bp = netdev_priv(dev);
1584 bp->msg_enable = value;
1585 }
1586
1587 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1588 {
1589 struct b44 *bp = netdev_priv(dev);
1590 struct pci_dev *pci_dev = bp->pdev;
1591
1592 strcpy (info->driver, DRV_MODULE_NAME);
1593 strcpy (info->version, DRV_MODULE_VERSION);
1594 strcpy (info->bus_info, pci_name(pci_dev));
1595 }
1596
1597 static int b44_nway_reset(struct net_device *dev)
1598 {
1599 struct b44 *bp = netdev_priv(dev);
1600 u32 bmcr;
1601 int r;
1602
1603 spin_lock_irq(&bp->lock);
1604 b44_readphy(bp, MII_BMCR, &bmcr);
1605 b44_readphy(bp, MII_BMCR, &bmcr);
1606 r = -EINVAL;
1607 if (bmcr & BMCR_ANENABLE) {
1608 b44_writephy(bp, MII_BMCR,
1609 bmcr | BMCR_ANRESTART);
1610 r = 0;
1611 }
1612 spin_unlock_irq(&bp->lock);
1613
1614 return r;
1615 }
1616
1617 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1618 {
1619 struct b44 *bp = netdev_priv(dev);
1620
1621 if (!netif_running(dev))
1622 return -EAGAIN;
1623 cmd->supported = (SUPPORTED_Autoneg);
1624 cmd->supported |= (SUPPORTED_100baseT_Half |
1625 SUPPORTED_100baseT_Full |
1626 SUPPORTED_10baseT_Half |
1627 SUPPORTED_10baseT_Full |
1628 SUPPORTED_MII);
1629
1630 cmd->advertising = 0;
1631 if (bp->flags & B44_FLAG_ADV_10HALF)
1632 cmd->advertising |= ADVERTISED_10baseT_Half;
1633 if (bp->flags & B44_FLAG_ADV_10FULL)
1634 cmd->advertising |= ADVERTISED_10baseT_Full;
1635 if (bp->flags & B44_FLAG_ADV_100HALF)
1636 cmd->advertising |= ADVERTISED_100baseT_Half;
1637 if (bp->flags & B44_FLAG_ADV_100FULL)
1638 cmd->advertising |= ADVERTISED_100baseT_Full;
1639 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1640 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1641 SPEED_100 : SPEED_10;
1642 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1643 DUPLEX_FULL : DUPLEX_HALF;
1644 cmd->port = 0;
1645 cmd->phy_address = bp->phy_addr;
1646 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1647 XCVR_INTERNAL : XCVR_EXTERNAL;
1648 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1649 AUTONEG_DISABLE : AUTONEG_ENABLE;
1650 cmd->maxtxpkt = 0;
1651 cmd->maxrxpkt = 0;
1652 return 0;
1653 }
1654
1655 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1656 {
1657 struct b44 *bp = netdev_priv(dev);
1658
1659 if (!netif_running(dev))
1660 return -EAGAIN;
1661
1662 /* We do not support gigabit. */
1663 if (cmd->autoneg == AUTONEG_ENABLE) {
1664 if (cmd->advertising &
1665 (ADVERTISED_1000baseT_Half |
1666 ADVERTISED_1000baseT_Full))
1667 return -EINVAL;
1668 } else if ((cmd->speed != SPEED_100 &&
1669 cmd->speed != SPEED_10) ||
1670 (cmd->duplex != DUPLEX_HALF &&
1671 cmd->duplex != DUPLEX_FULL)) {
1672 return -EINVAL;
1673 }
1674
1675 spin_lock_irq(&bp->lock);
1676
1677 if (cmd->autoneg == AUTONEG_ENABLE) {
1678 bp->flags &= ~B44_FLAG_FORCE_LINK;
1679 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1680 B44_FLAG_ADV_10FULL |
1681 B44_FLAG_ADV_100HALF |
1682 B44_FLAG_ADV_100FULL);
1683 if (cmd->advertising & ADVERTISE_10HALF)
1684 bp->flags |= B44_FLAG_ADV_10HALF;
1685 if (cmd->advertising & ADVERTISE_10FULL)
1686 bp->flags |= B44_FLAG_ADV_10FULL;
1687 if (cmd->advertising & ADVERTISE_100HALF)
1688 bp->flags |= B44_FLAG_ADV_100HALF;
1689 if (cmd->advertising & ADVERTISE_100FULL)
1690 bp->flags |= B44_FLAG_ADV_100FULL;
1691 } else {
1692 bp->flags |= B44_FLAG_FORCE_LINK;
1693 if (cmd->speed == SPEED_100)
1694 bp->flags |= B44_FLAG_100_BASE_T;
1695 if (cmd->duplex == DUPLEX_FULL)
1696 bp->flags |= B44_FLAG_FULL_DUPLEX;
1697 }
1698
1699 b44_setup_phy(bp);
1700
1701 spin_unlock_irq(&bp->lock);
1702
1703 return 0;
1704 }
1705
1706 static void b44_get_ringparam(struct net_device *dev,
1707 struct ethtool_ringparam *ering)
1708 {
1709 struct b44 *bp = netdev_priv(dev);
1710
1711 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1712 ering->rx_pending = bp->rx_pending;
1713
1714 /* XXX ethtool lacks a tx_max_pending, oops... */
1715 }
1716
1717 static int b44_set_ringparam(struct net_device *dev,
1718 struct ethtool_ringparam *ering)
1719 {
1720 struct b44 *bp = netdev_priv(dev);
1721
1722 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1723 (ering->rx_mini_pending != 0) ||
1724 (ering->rx_jumbo_pending != 0) ||
1725 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1726 return -EINVAL;
1727
1728 spin_lock_irq(&bp->lock);
1729
1730 bp->rx_pending = ering->rx_pending;
1731 bp->tx_pending = ering->tx_pending;
1732
1733 b44_halt(bp);
1734 b44_init_rings(bp);
1735 b44_init_hw(bp);
1736 netif_wake_queue(bp->dev);
1737 spin_unlock_irq(&bp->lock);
1738
1739 b44_enable_ints(bp);
1740
1741 return 0;
1742 }
1743
1744 static void b44_get_pauseparam(struct net_device *dev,
1745 struct ethtool_pauseparam *epause)
1746 {
1747 struct b44 *bp = netdev_priv(dev);
1748
1749 epause->autoneg =
1750 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1751 epause->rx_pause =
1752 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1753 epause->tx_pause =
1754 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1755 }
1756
1757 static int b44_set_pauseparam(struct net_device *dev,
1758 struct ethtool_pauseparam *epause)
1759 {
1760 struct b44 *bp = netdev_priv(dev);
1761
1762 spin_lock_irq(&bp->lock);
1763 if (epause->autoneg)
1764 bp->flags |= B44_FLAG_PAUSE_AUTO;
1765 else
1766 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1767 if (epause->rx_pause)
1768 bp->flags |= B44_FLAG_RX_PAUSE;
1769 else
1770 bp->flags &= ~B44_FLAG_RX_PAUSE;
1771 if (epause->tx_pause)
1772 bp->flags |= B44_FLAG_TX_PAUSE;
1773 else
1774 bp->flags &= ~B44_FLAG_TX_PAUSE;
1775 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1776 b44_halt(bp);
1777 b44_init_rings(bp);
1778 b44_init_hw(bp);
1779 } else {
1780 __b44_set_flow_ctrl(bp, bp->flags);
1781 }
1782 spin_unlock_irq(&bp->lock);
1783
1784 b44_enable_ints(bp);
1785
1786 return 0;
1787 }
1788
1789 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1790 {
1791 switch(stringset) {
1792 case ETH_SS_STATS:
1793 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1794 break;
1795 }
1796 }
1797
1798 static int b44_get_stats_count(struct net_device *dev)
1799 {
1800 return ARRAY_SIZE(b44_gstrings);
1801 }
1802
1803 static void b44_get_ethtool_stats(struct net_device *dev,
1804 struct ethtool_stats *stats, u64 *data)
1805 {
1806 struct b44 *bp = netdev_priv(dev);
1807 u32 *val = &bp->hw_stats.tx_good_octets;
1808 u32 i;
1809
1810 spin_lock_irq(&bp->lock);
1811
1812 b44_stats_update(bp);
1813
1814 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1815 *data++ = *val++;
1816
1817 spin_unlock_irq(&bp->lock);
1818 }
1819
1820 static struct ethtool_ops b44_ethtool_ops = {
1821 .get_drvinfo = b44_get_drvinfo,
1822 .get_settings = b44_get_settings,
1823 .set_settings = b44_set_settings,
1824 .nway_reset = b44_nway_reset,
1825 .get_link = ethtool_op_get_link,
1826 .get_ringparam = b44_get_ringparam,
1827 .set_ringparam = b44_set_ringparam,
1828 .get_pauseparam = b44_get_pauseparam,
1829 .set_pauseparam = b44_set_pauseparam,
1830 .get_msglevel = b44_get_msglevel,
1831 .set_msglevel = b44_set_msglevel,
1832 .get_strings = b44_get_strings,
1833 .get_stats_count = b44_get_stats_count,
1834 .get_ethtool_stats = b44_get_ethtool_stats,
1835 .get_perm_addr = ethtool_op_get_perm_addr,
1836 };
1837
1838 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1839 {
1840 struct mii_ioctl_data *data = if_mii(ifr);
1841 struct b44 *bp = netdev_priv(dev);
1842 int err = -EINVAL;
1843
1844 if (!netif_running(dev))
1845 goto out;
1846
1847 spin_lock_irq(&bp->lock);
1848 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1849 spin_unlock_irq(&bp->lock);
1850 out:
1851 return err;
1852 }
1853
1854 /* Read 128-bytes of EEPROM. */
1855 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1856 {
1857 long i;
1858 u16 *ptr = (u16 *) data;
1859
1860 for (i = 0; i < 128; i += 2)
1861 ptr[i / 2] = readw(bp->regs + 4096 + i);
1862
1863 return 0;
1864 }
1865
1866 static int __devinit b44_get_invariants(struct b44 *bp)
1867 {
1868 u8 eeprom[128];
1869 int err;
1870
1871 err = b44_read_eeprom(bp, &eeprom[0]);
1872 if (err)
1873 goto out;
1874
1875 bp->dev->dev_addr[0] = eeprom[79];
1876 bp->dev->dev_addr[1] = eeprom[78];
1877 bp->dev->dev_addr[2] = eeprom[81];
1878 bp->dev->dev_addr[3] = eeprom[80];
1879 bp->dev->dev_addr[4] = eeprom[83];
1880 bp->dev->dev_addr[5] = eeprom[82];
1881
1882 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
1883 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
1884 return -EINVAL;
1885 }
1886
1887 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1888
1889 bp->phy_addr = eeprom[90] & 0x1f;
1890
1891 /* With this, plus the rx_header prepended to the data by the
1892 * hardware, we'll land the ethernet header on a 2-byte boundary.
1893 */
1894 bp->rx_offset = 30;
1895
1896 bp->imask = IMASK_DEF;
1897
1898 bp->core_unit = ssb_core_unit(bp);
1899 bp->dma_offset = SB_PCI_DMA;
1900
1901 /* XXX - really required?
1902 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1903 */
1904 out:
1905 return err;
1906 }
1907
1908 static int __devinit b44_init_one(struct pci_dev *pdev,
1909 const struct pci_device_id *ent)
1910 {
1911 static int b44_version_printed = 0;
1912 unsigned long b44reg_base, b44reg_len;
1913 struct net_device *dev;
1914 struct b44 *bp;
1915 int err, i;
1916
1917 if (b44_version_printed++ == 0)
1918 printk(KERN_INFO "%s", version);
1919
1920 err = pci_enable_device(pdev);
1921 if (err) {
1922 printk(KERN_ERR PFX "Cannot enable PCI device, "
1923 "aborting.\n");
1924 return err;
1925 }
1926
1927 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1928 printk(KERN_ERR PFX "Cannot find proper PCI device "
1929 "base address, aborting.\n");
1930 err = -ENODEV;
1931 goto err_out_disable_pdev;
1932 }
1933
1934 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1935 if (err) {
1936 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1937 "aborting.\n");
1938 goto err_out_disable_pdev;
1939 }
1940
1941 pci_set_master(pdev);
1942
1943 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1944 if (err) {
1945 printk(KERN_ERR PFX "No usable DMA configuration, "
1946 "aborting.\n");
1947 goto err_out_free_res;
1948 }
1949
1950 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1951 if (err) {
1952 printk(KERN_ERR PFX "No usable DMA configuration, "
1953 "aborting.\n");
1954 goto err_out_free_res;
1955 }
1956
1957 b44reg_base = pci_resource_start(pdev, 0);
1958 b44reg_len = pci_resource_len(pdev, 0);
1959
1960 dev = alloc_etherdev(sizeof(*bp));
1961 if (!dev) {
1962 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1963 err = -ENOMEM;
1964 goto err_out_free_res;
1965 }
1966
1967 SET_MODULE_OWNER(dev);
1968 SET_NETDEV_DEV(dev,&pdev->dev);
1969
1970 /* No interesting netdevice features in this card... */
1971 dev->features |= 0;
1972
1973 bp = netdev_priv(dev);
1974 bp->pdev = pdev;
1975 bp->dev = dev;
1976
1977 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1978
1979 spin_lock_init(&bp->lock);
1980
1981 bp->regs = ioremap(b44reg_base, b44reg_len);
1982 if (bp->regs == 0UL) {
1983 printk(KERN_ERR PFX "Cannot map device registers, "
1984 "aborting.\n");
1985 err = -ENOMEM;
1986 goto err_out_free_dev;
1987 }
1988
1989 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1990 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1991
1992 dev->open = b44_open;
1993 dev->stop = b44_close;
1994 dev->hard_start_xmit = b44_start_xmit;
1995 dev->get_stats = b44_get_stats;
1996 dev->set_multicast_list = b44_set_rx_mode;
1997 dev->set_mac_address = b44_set_mac_addr;
1998 dev->do_ioctl = b44_ioctl;
1999 dev->tx_timeout = b44_tx_timeout;
2000 dev->poll = b44_poll;
2001 dev->weight = 64;
2002 dev->watchdog_timeo = B44_TX_TIMEOUT;
2003 #ifdef CONFIG_NET_POLL_CONTROLLER
2004 dev->poll_controller = b44_poll_controller;
2005 #endif
2006 dev->change_mtu = b44_change_mtu;
2007 dev->irq = pdev->irq;
2008 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2009
2010 netif_carrier_off(dev);
2011
2012 err = b44_get_invariants(bp);
2013 if (err) {
2014 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
2015 "aborting.\n");
2016 goto err_out_iounmap;
2017 }
2018
2019 bp->mii_if.dev = dev;
2020 bp->mii_if.mdio_read = b44_mii_read;
2021 bp->mii_if.mdio_write = b44_mii_write;
2022 bp->mii_if.phy_id = bp->phy_addr;
2023 bp->mii_if.phy_id_mask = 0x1f;
2024 bp->mii_if.reg_num_mask = 0x1f;
2025
2026 /* By default, advertise all speed/duplex settings. */
2027 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2028 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2029
2030 /* By default, auto-negotiate PAUSE. */
2031 bp->flags |= B44_FLAG_PAUSE_AUTO;
2032
2033 err = register_netdev(dev);
2034 if (err) {
2035 printk(KERN_ERR PFX "Cannot register net device, "
2036 "aborting.\n");
2037 goto err_out_iounmap;
2038 }
2039
2040 pci_set_drvdata(pdev, dev);
2041
2042 pci_save_state(bp->pdev);
2043
2044 /* Chip reset provides power to the b44 MAC & PCI cores, which
2045 * is necessary for MAC register access.
2046 */
2047 b44_chip_reset(bp);
2048
2049 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2050 for (i = 0; i < 6; i++)
2051 printk("%2.2x%c", dev->dev_addr[i],
2052 i == 5 ? '\n' : ':');
2053
2054 return 0;
2055
2056 err_out_iounmap:
2057 iounmap(bp->regs);
2058
2059 err_out_free_dev:
2060 free_netdev(dev);
2061
2062 err_out_free_res:
2063 pci_release_regions(pdev);
2064
2065 err_out_disable_pdev:
2066 pci_disable_device(pdev);
2067 pci_set_drvdata(pdev, NULL);
2068 return err;
2069 }
2070
2071 static void __devexit b44_remove_one(struct pci_dev *pdev)
2072 {
2073 struct net_device *dev = pci_get_drvdata(pdev);
2074 struct b44 *bp = netdev_priv(dev);
2075
2076 unregister_netdev(dev);
2077 iounmap(bp->regs);
2078 free_netdev(dev);
2079 pci_release_regions(pdev);
2080 pci_disable_device(pdev);
2081 pci_set_drvdata(pdev, NULL);
2082 }
2083
2084 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2085 {
2086 struct net_device *dev = pci_get_drvdata(pdev);
2087 struct b44 *bp = netdev_priv(dev);
2088
2089 if (!netif_running(dev))
2090 return 0;
2091
2092 del_timer_sync(&bp->timer);
2093
2094 spin_lock_irq(&bp->lock);
2095
2096 b44_halt(bp);
2097 netif_carrier_off(bp->dev);
2098 netif_device_detach(bp->dev);
2099 b44_free_rings(bp);
2100
2101 spin_unlock_irq(&bp->lock);
2102
2103 free_irq(dev->irq, dev);
2104 pci_disable_device(pdev);
2105 return 0;
2106 }
2107
2108 static int b44_resume(struct pci_dev *pdev)
2109 {
2110 struct net_device *dev = pci_get_drvdata(pdev);
2111 struct b44 *bp = netdev_priv(dev);
2112
2113 pci_restore_state(pdev);
2114 pci_enable_device(pdev);
2115 pci_set_master(pdev);
2116
2117 if (!netif_running(dev))
2118 return 0;
2119
2120 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2121 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2122
2123 spin_lock_irq(&bp->lock);
2124
2125 b44_init_rings(bp);
2126 b44_init_hw(bp);
2127 netif_device_attach(bp->dev);
2128 spin_unlock_irq(&bp->lock);
2129
2130 bp->timer.expires = jiffies + HZ;
2131 add_timer(&bp->timer);
2132
2133 b44_enable_ints(bp);
2134 netif_wake_queue(dev);
2135 return 0;
2136 }
2137
2138 static struct pci_driver b44_driver = {
2139 .name = DRV_MODULE_NAME,
2140 .id_table = b44_pci_tbl,
2141 .probe = b44_init_one,
2142 .remove = __devexit_p(b44_remove_one),
2143 .suspend = b44_suspend,
2144 .resume = b44_resume,
2145 };
2146
2147 static int __init b44_init(void)
2148 {
2149 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2150
2151 /* Setup paramaters for syncing RX/TX DMA descriptors */
2152 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2153 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2154
2155 return pci_module_init(&b44_driver);
2156 }
2157
2158 static void __exit b44_cleanup(void)
2159 {
2160 pci_unregister_driver(&b44_driver);
2161 }
2162
2163 module_init(b44_init);
2164 module_exit(b44_cleanup);
2165
linux kernel for loongson