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BUG_ON() Conversion in drivers/net/
[linux-2.6/linux-loongson.git] / drivers / net / 8139cp.c
blob066e22b01a941ed90fcc3edf028ed217b8688da0
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/if_vlan.h>
69 #include <linux/crc32.h>
70 #include <linux/in.h>
71 #include <linux/ip.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/cache.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/uaccess.h>
78
79 /* VLAN tagging feature enable/disable */
80 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81 #define CP_VLAN_TAG_USED 1
82 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #else
85 #define CP_VLAN_TAG_USED 0
86 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88 #endif
89
90 /* These identify the driver base version and may not be removed. */
91 static char version[] =
92 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96 MODULE_VERSION(DRV_VERSION);
97 MODULE_LICENSE("GPL");
98
99 static int debug = -1;
100 module_param(debug, int, 0);
101 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105 static int multicast_filter_limit = 32;
106 module_param(multicast_filter_limit, int, 0);
107 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109 #define PFX DRV_NAME ": "
110
111 #ifndef TRUE
112 #define FALSE 0
113 #define TRUE (!FALSE)
114 #endif
115
116 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
117 NETIF_MSG_PROBE | \
118 NETIF_MSG_LINK)
119 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
120 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
121 #define CP_REGS_SIZE (0xff + 1)
122 #define CP_REGS_VER 1 /* version 1 */
123 #define CP_RX_RING_SIZE 64
124 #define CP_TX_RING_SIZE 64
125 #define CP_RING_BYTES \
126 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
127 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 CP_STATS_SIZE)
129 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
130 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
131 #define TX_BUFFS_AVAIL(CP) \
132 (((CP)->tx_tail <= (CP)->tx_head) ? \
133 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
134 (CP)->tx_tail - (CP)->tx_head - 1)
135
136 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define RX_OFFSET 2
138 #define CP_INTERNAL_PHY 32
139
140 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
141 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
142 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
143 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
144 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145
146 /* Time in jiffies before concluding the transmitter is hung. */
147 #define TX_TIMEOUT (6*HZ)
148
149 /* hardware minimum and maximum for a single frame's data payload */
150 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
151 #define CP_MAX_MTU 4096
152
153 enum {
154 /* NIC register offsets */
155 MAC0 = 0x00, /* Ethernet hardware address. */
156 MAR0 = 0x08, /* Multicast filter. */
157 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
158 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
159 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
160 Cmd = 0x37, /* Command register */
161 IntrMask = 0x3C, /* Interrupt mask */
162 IntrStatus = 0x3E, /* Interrupt status */
163 TxConfig = 0x40, /* Tx configuration */
164 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
165 RxConfig = 0x44, /* Rx configuration */
166 RxMissed = 0x4C, /* 24 bits valid, write clears */
167 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
168 Config1 = 0x52, /* Config1 */
169 Config3 = 0x59, /* Config3 */
170 Config4 = 0x5A, /* Config4 */
171 MultiIntr = 0x5C, /* Multiple interrupt select */
172 BasicModeCtrl = 0x62, /* MII BMCR */
173 BasicModeStatus = 0x64, /* MII BMSR */
174 NWayAdvert = 0x66, /* MII ADVERTISE */
175 NWayLPAR = 0x68, /* MII LPA */
176 NWayExpansion = 0x6A, /* MII Expansion */
177 Config5 = 0xD8, /* Config5 */
178 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
179 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
180 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
181 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
182 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
183 TxThresh = 0xEC, /* Early Tx threshold */
184 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
185 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186
187 /* Tx and Rx status descriptors */
188 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
189 RingEnd = (1 << 30), /* End of descriptor ring */
190 FirstFrag = (1 << 29), /* First segment of a packet */
191 LastFrag = (1 << 28), /* Final segment of a packet */
192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
195 TxError = (1 << 23), /* Tx error summary */
196 RxError = (1 << 20), /* Rx error summary */
197 IPCS = (1 << 18), /* Calculate IP checksum */
198 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
199 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
200 TxVlanTag = (1 << 17), /* Add VLAN tag */
201 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
202 IPFail = (1 << 15), /* IP checksum failed */
203 UDPFail = (1 << 14), /* UDP/IP checksum failed */
204 TCPFail = (1 << 13), /* TCP/IP checksum failed */
205 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
206 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
207 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 RxProtoTCP = 1,
209 RxProtoUDP = 2,
210 RxProtoIP = 3,
211 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
212 TxOWC = (1 << 22), /* Tx Out-of-window collision */
213 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
214 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
215 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
216 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
217 RxErrFrame = (1 << 27), /* Rx frame alignment error */
218 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
219 RxErrCRC = (1 << 18), /* Rx CRC error */
220 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
221 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
222 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223
224 /* StatsAddr register */
225 DumpStats = (1 << 3), /* Begin stats dump */
226
227 /* RxConfig register */
228 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
229 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
230 AcceptErr = 0x20, /* Accept packets with CRC errors */
231 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
232 AcceptBroadcast = 0x08, /* Accept broadcast packets */
233 AcceptMulticast = 0x04, /* Accept multicast packets */
234 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
235 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236
237 /* IntrMask / IntrStatus registers */
238 PciErr = (1 << 15), /* System error on the PCI bus */
239 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
240 LenChg = (1 << 13), /* Cable length change */
241 SWInt = (1 << 8), /* Software-requested interrupt */
242 TxEmpty = (1 << 7), /* No Tx descriptors available */
243 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
244 LinkChg = (1 << 5), /* Packet underrun, or link change */
245 RxEmpty = (1 << 4), /* No Rx descriptors available */
246 TxErr = (1 << 3), /* Tx error */
247 TxOK = (1 << 2), /* Tx packet sent */
248 RxErr = (1 << 1), /* Rx error */
249 RxOK = (1 << 0), /* Rx packet received */
250 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
251 but hardware likes to raise it */
252
253 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
254 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
255 RxErr | RxOK | IntrResvd,
256
257 /* C mode command register */
258 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
259 RxOn = (1 << 3), /* Rx mode enable */
260 TxOn = (1 << 2), /* Tx mode enable */
261
262 /* C+ mode command register */
263 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
264 RxChkSum = (1 << 5), /* Rx checksum offload enable */
265 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
266 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
267 CpRxOn = (1 << 1), /* Rx mode enable */
268 CpTxOn = (1 << 0), /* Tx mode enable */
269
270 /* Cfg9436 EEPROM control register */
271 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
272 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273
274 /* TxConfig register */
275 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /* Early Tx Threshold register */
279 TxThreshMask = 0x3f, /* Mask bits 5-0 */
280 TxThreshMax = 2048, /* Max early Tx threshold */
281
282 /* Config1 register */
283 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
284 LWACT = (1 << 4), /* LWAKE active mode */
285 PMEnable = (1 << 0), /* Enable various PM features of chip */
286
287 /* Config3 register */
288 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
292 /* Config4 register */
293 LWPTN = (1 << 1), /* LWAKE Pattern */
294 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295
296 /* Config5 register */
297 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
298 MWF = (1 << 5), /* Accept Multicast wakeup frame */
299 UWF = (1 << 4), /* Accept Unicast wakeup frame */
300 LANWake = (1 << 1), /* Enable LANWake signal */
301 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302
303 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
304 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
305 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
306 };
307
308 static const unsigned int cp_rx_config =
309 (RX_FIFO_THRESH << RxCfgFIFOShift) |
310 (RX_DMA_BURST << RxCfgDMAShift);
311
312 struct cp_desc {
313 u32 opts1;
314 u32 opts2;
315 u64 addr;
316 };
317
318 struct ring_info {
319 struct sk_buff *skb;
320 dma_addr_t mapping;
321 u32 len;
322 };
323
324 struct cp_dma_stats {
325 u64 tx_ok;
326 u64 rx_ok;
327 u64 tx_err;
328 u32 rx_err;
329 u16 rx_fifo;
330 u16 frame_align;
331 u32 tx_ok_1col;
332 u32 tx_ok_mcol;
333 u64 rx_ok_phys;
334 u64 rx_ok_bcast;
335 u32 rx_ok_mcast;
336 u16 tx_abort;
337 u16 tx_underrun;
338 } __attribute__((packed));
339
340 struct cp_extra_stats {
341 unsigned long rx_frags;
342 };
343
344 struct cp_private {
345 void __iomem *regs;
346 struct net_device *dev;
347 spinlock_t lock;
348 u32 msg_enable;
349
350 struct pci_dev *pdev;
351 u32 rx_config;
352 u16 cpcmd;
353
354 struct net_device_stats net_stats;
355 struct cp_extra_stats cp_stats;
356
357 unsigned rx_tail ____cacheline_aligned;
358 struct cp_desc *rx_ring;
359 struct ring_info rx_skb[CP_RX_RING_SIZE];
360 unsigned rx_buf_sz;
361
362 unsigned tx_head ____cacheline_aligned;
363 unsigned tx_tail;
364
365 struct cp_desc *tx_ring;
366 struct ring_info tx_skb[CP_TX_RING_SIZE];
367 dma_addr_t ring_dma;
368
369 #if CP_VLAN_TAG_USED
370 struct vlan_group *vlgrp;
371 #endif
372
373 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374
375 struct mii_if_info mii_if;
376 };
377
378 #define cpr8(reg) readb(cp->regs + (reg))
379 #define cpr16(reg) readw(cp->regs + (reg))
380 #define cpr32(reg) readl(cp->regs + (reg))
381 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
382 #define cpw16(reg,val) writew((val), cp->regs + (reg))
383 #define cpw32(reg,val) writel((val), cp->regs + (reg))
384 #define cpw8_f(reg,val) do { \
385 writeb((val), cp->regs + (reg)); \
386 readb(cp->regs + (reg)); \
387 } while (0)
388 #define cpw16_f(reg,val) do { \
389 writew((val), cp->regs + (reg)); \
390 readw(cp->regs + (reg)); \
391 } while (0)
392 #define cpw32_f(reg,val) do { \
393 writel((val), cp->regs + (reg)); \
394 readl(cp->regs + (reg)); \
395 } while (0)
396
397
398 static void __cp_set_rx_mode (struct net_device *dev);
399 static void cp_tx (struct cp_private *cp);
400 static void cp_clean_rings (struct cp_private *cp);
401 #ifdef CONFIG_NET_POLL_CONTROLLER
402 static void cp_poll_controller(struct net_device *dev);
403 #endif
404
405 static struct pci_device_id cp_pci_tbl[] = {
406 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
410 { },
411 };
412 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
413
414 static struct {
415 const char str[ETH_GSTRING_LEN];
416 } ethtool_stats_keys[] = {
417 { "tx_ok" },
418 { "rx_ok" },
419 { "tx_err" },
420 { "rx_err" },
421 { "rx_fifo" },
422 { "frame_align" },
423 { "tx_ok_1col" },
424 { "tx_ok_mcol" },
425 { "rx_ok_phys" },
426 { "rx_ok_bcast" },
427 { "rx_ok_mcast" },
428 { "tx_abort" },
429 { "tx_underrun" },
430 { "rx_frags" },
431 };
432
433
434 #if CP_VLAN_TAG_USED
435 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
436 {
437 struct cp_private *cp = netdev_priv(dev);
438 unsigned long flags;
439
440 spin_lock_irqsave(&cp->lock, flags);
441 cp->vlgrp = grp;
442 cp->cpcmd |= RxVlanOn;
443 cpw16(CpCmd, cp->cpcmd);
444 spin_unlock_irqrestore(&cp->lock, flags);
445 }
446
447 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
448 {
449 struct cp_private *cp = netdev_priv(dev);
450 unsigned long flags;
451
452 spin_lock_irqsave(&cp->lock, flags);
453 cp->cpcmd &= ~RxVlanOn;
454 cpw16(CpCmd, cp->cpcmd);
455 if (cp->vlgrp)
456 cp->vlgrp->vlan_devices[vid] = NULL;
457 spin_unlock_irqrestore(&cp->lock, flags);
458 }
459 #endif /* CP_VLAN_TAG_USED */
460
461 static inline void cp_set_rxbufsize (struct cp_private *cp)
462 {
463 unsigned int mtu = cp->dev->mtu;
464
465 if (mtu > ETH_DATA_LEN)
466 /* MTU + ethernet header + FCS + optional VLAN tag */
467 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
468 else
469 cp->rx_buf_sz = PKT_BUF_SZ;
470 }
471
472 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
473 struct cp_desc *desc)
474 {
475 skb->protocol = eth_type_trans (skb, cp->dev);
476
477 cp->net_stats.rx_packets++;
478 cp->net_stats.rx_bytes += skb->len;
479 cp->dev->last_rx = jiffies;
480
481 #if CP_VLAN_TAG_USED
482 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
483 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
484 be16_to_cpu(desc->opts2 & 0xffff));
485 } else
486 #endif
487 netif_receive_skb(skb);
488 }
489
490 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
491 u32 status, u32 len)
492 {
493 if (netif_msg_rx_err (cp))
494 printk (KERN_DEBUG
495 "%s: rx err, slot %d status 0x%x len %d\n",
496 cp->dev->name, rx_tail, status, len);
497 cp->net_stats.rx_errors++;
498 if (status & RxErrFrame)
499 cp->net_stats.rx_frame_errors++;
500 if (status & RxErrCRC)
501 cp->net_stats.rx_crc_errors++;
502 if ((status & RxErrRunt) || (status & RxErrLong))
503 cp->net_stats.rx_length_errors++;
504 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
505 cp->net_stats.rx_length_errors++;
506 if (status & RxErrFIFO)
507 cp->net_stats.rx_fifo_errors++;
508 }
509
510 static inline unsigned int cp_rx_csum_ok (u32 status)
511 {
512 unsigned int protocol = (status >> 16) & 0x3;
513
514 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
515 return 1;
516 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
517 return 1;
518 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 return 1;
520 return 0;
521 }
522
523 static int cp_rx_poll (struct net_device *dev, int *budget)
524 {
525 struct cp_private *cp = netdev_priv(dev);
526 unsigned rx_tail = cp->rx_tail;
527 unsigned rx_work = dev->quota;
528 unsigned rx;
529
530 rx_status_loop:
531 rx = 0;
532 cpw16(IntrStatus, cp_rx_intr_mask);
533
534 while (1) {
535 u32 status, len;
536 dma_addr_t mapping;
537 struct sk_buff *skb, *new_skb;
538 struct cp_desc *desc;
539 unsigned buflen;
540
541 skb = cp->rx_skb[rx_tail].skb;
542 BUG_ON(!skb);
543
544 desc = &cp->rx_ring[rx_tail];
545 status = le32_to_cpu(desc->opts1);
546 if (status & DescOwn)
547 break;
548
549 len = (status & 0x1fff) - 4;
550 mapping = cp->rx_skb[rx_tail].mapping;
551
552 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
553 /* we don't support incoming fragmented frames.
554 * instead, we attempt to ensure that the
555 * pre-allocated RX skbs are properly sized such
556 * that RX fragments are never encountered
557 */
558 cp_rx_err_acct(cp, rx_tail, status, len);
559 cp->net_stats.rx_dropped++;
560 cp->cp_stats.rx_frags++;
561 goto rx_next;
562 }
563
564 if (status & (RxError | RxErrFIFO)) {
565 cp_rx_err_acct(cp, rx_tail, status, len);
566 goto rx_next;
567 }
568
569 if (netif_msg_rx_status(cp))
570 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
571 cp->dev->name, rx_tail, status, len);
572
573 buflen = cp->rx_buf_sz + RX_OFFSET;
574 new_skb = dev_alloc_skb (buflen);
575 if (!new_skb) {
576 cp->net_stats.rx_dropped++;
577 goto rx_next;
578 }
579
580 skb_reserve(new_skb, RX_OFFSET);
581 new_skb->dev = cp->dev;
582
583 pci_unmap_single(cp->pdev, mapping,
584 buflen, PCI_DMA_FROMDEVICE);
585
586 /* Handle checksum offloading for incoming packets. */
587 if (cp_rx_csum_ok(status))
588 skb->ip_summed = CHECKSUM_UNNECESSARY;
589 else
590 skb->ip_summed = CHECKSUM_NONE;
591
592 skb_put(skb, len);
593
594 mapping =
595 cp->rx_skb[rx_tail].mapping =
596 pci_map_single(cp->pdev, new_skb->data,
597 buflen, PCI_DMA_FROMDEVICE);
598 cp->rx_skb[rx_tail].skb = new_skb;
599
600 cp_rx_skb(cp, skb, desc);
601 rx++;
602
603 rx_next:
604 cp->rx_ring[rx_tail].opts2 = 0;
605 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
606 if (rx_tail == (CP_RX_RING_SIZE - 1))
607 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
608 cp->rx_buf_sz);
609 else
610 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
611 rx_tail = NEXT_RX(rx_tail);
612
613 if (!rx_work--)
614 break;
615 }
616
617 cp->rx_tail = rx_tail;
618
619 dev->quota -= rx;
620 *budget -= rx;
621
622 /* if we did not reach work limit, then we're done with
623 * this round of polling
624 */
625 if (rx_work) {
626 if (cpr16(IntrStatus) & cp_rx_intr_mask)
627 goto rx_status_loop;
628
629 local_irq_disable();
630 cpw16_f(IntrMask, cp_intr_mask);
631 __netif_rx_complete(dev);
632 local_irq_enable();
633
634 return 0; /* done */
635 }
636
637 return 1; /* not done */
638 }
639
640 static irqreturn_t
641 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
642 {
643 struct net_device *dev = dev_instance;
644 struct cp_private *cp;
645 u16 status;
646
647 if (unlikely(dev == NULL))
648 return IRQ_NONE;
649 cp = netdev_priv(dev);
650
651 status = cpr16(IntrStatus);
652 if (!status || (status == 0xFFFF))
653 return IRQ_NONE;
654
655 if (netif_msg_intr(cp))
656 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
657 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
658
659 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
660
661 spin_lock(&cp->lock);
662
663 /* close possible race's with dev_close */
664 if (unlikely(!netif_running(dev))) {
665 cpw16(IntrMask, 0);
666 spin_unlock(&cp->lock);
667 return IRQ_HANDLED;
668 }
669
670 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
671 if (netif_rx_schedule_prep(dev)) {
672 cpw16_f(IntrMask, cp_norx_intr_mask);
673 __netif_rx_schedule(dev);
674 }
675
676 if (status & (TxOK | TxErr | TxEmpty | SWInt))
677 cp_tx(cp);
678 if (status & LinkChg)
679 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
680
681 spin_unlock(&cp->lock);
682
683 if (status & PciErr) {
684 u16 pci_status;
685
686 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
687 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
688 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
689 dev->name, status, pci_status);
690
691 /* TODO: reset hardware */
692 }
693
694 return IRQ_HANDLED;
695 }
696
697 #ifdef CONFIG_NET_POLL_CONTROLLER
698 /*
699 * Polling receive - used by netconsole and other diagnostic tools
700 * to allow network i/o with interrupts disabled.
701 */
702 static void cp_poll_controller(struct net_device *dev)
703 {
704 disable_irq(dev->irq);
705 cp_interrupt(dev->irq, dev, NULL);
706 enable_irq(dev->irq);
707 }
708 #endif
709
710 static void cp_tx (struct cp_private *cp)
711 {
712 unsigned tx_head = cp->tx_head;
713 unsigned tx_tail = cp->tx_tail;
714
715 while (tx_tail != tx_head) {
716 struct sk_buff *skb;
717 u32 status;
718
719 rmb();
720 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
721 if (status & DescOwn)
722 break;
723
724 skb = cp->tx_skb[tx_tail].skb;
725 BUG_ON(!skb);
726
727 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
728 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
729
730 if (status & LastFrag) {
731 if (status & (TxError | TxFIFOUnder)) {
732 if (netif_msg_tx_err(cp))
733 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
734 cp->dev->name, status);
735 cp->net_stats.tx_errors++;
736 if (status & TxOWC)
737 cp->net_stats.tx_window_errors++;
738 if (status & TxMaxCol)
739 cp->net_stats.tx_aborted_errors++;
740 if (status & TxLinkFail)
741 cp->net_stats.tx_carrier_errors++;
742 if (status & TxFIFOUnder)
743 cp->net_stats.tx_fifo_errors++;
744 } else {
745 cp->net_stats.collisions +=
746 ((status >> TxColCntShift) & TxColCntMask);
747 cp->net_stats.tx_packets++;
748 cp->net_stats.tx_bytes += skb->len;
749 if (netif_msg_tx_done(cp))
750 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
751 }
752 dev_kfree_skb_irq(skb);
753 }
754
755 cp->tx_skb[tx_tail].skb = NULL;
756
757 tx_tail = NEXT_TX(tx_tail);
758 }
759
760 cp->tx_tail = tx_tail;
761
762 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
763 netif_wake_queue(cp->dev);
764 }
765
766 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
767 {
768 struct cp_private *cp = netdev_priv(dev);
769 unsigned entry;
770 u32 eor, flags;
771 #if CP_VLAN_TAG_USED
772 u32 vlan_tag = 0;
773 #endif
774 int mss = 0;
775
776 spin_lock_irq(&cp->lock);
777
778 /* This is a hard error, log it. */
779 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
780 netif_stop_queue(dev);
781 spin_unlock_irq(&cp->lock);
782 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
783 dev->name);
784 return 1;
785 }
786
787 #if CP_VLAN_TAG_USED
788 if (cp->vlgrp && vlan_tx_tag_present(skb))
789 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
790 #endif
791
792 entry = cp->tx_head;
793 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
794 if (dev->features & NETIF_F_TSO)
795 mss = skb_shinfo(skb)->tso_size;
796
797 if (skb_shinfo(skb)->nr_frags == 0) {
798 struct cp_desc *txd = &cp->tx_ring[entry];
799 u32 len;
800 dma_addr_t mapping;
801
802 len = skb->len;
803 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
804 CP_VLAN_TX_TAG(txd, vlan_tag);
805 txd->addr = cpu_to_le64(mapping);
806 wmb();
807
808 flags = eor | len | DescOwn | FirstFrag | LastFrag;
809
810 if (mss)
811 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
812 else if (skb->ip_summed == CHECKSUM_HW) {
813 const struct iphdr *ip = skb->nh.iph;
814 if (ip->protocol == IPPROTO_TCP)
815 flags |= IPCS | TCPCS;
816 else if (ip->protocol == IPPROTO_UDP)
817 flags |= IPCS | UDPCS;
818 else
819 WARN_ON(1); /* we need a WARN() */
820 }
821
822 txd->opts1 = cpu_to_le32(flags);
823 wmb();
824
825 cp->tx_skb[entry].skb = skb;
826 cp->tx_skb[entry].mapping = mapping;
827 cp->tx_skb[entry].len = len;
828 entry = NEXT_TX(entry);
829 } else {
830 struct cp_desc *txd;
831 u32 first_len, first_eor;
832 dma_addr_t first_mapping;
833 int frag, first_entry = entry;
834 const struct iphdr *ip = skb->nh.iph;
835
836 /* We must give this initial chunk to the device last.
837 * Otherwise we could race with the device.
838 */
839 first_eor = eor;
840 first_len = skb_headlen(skb);
841 first_mapping = pci_map_single(cp->pdev, skb->data,
842 first_len, PCI_DMA_TODEVICE);
843 cp->tx_skb[entry].skb = skb;
844 cp->tx_skb[entry].mapping = first_mapping;
845 cp->tx_skb[entry].len = first_len;
846 entry = NEXT_TX(entry);
847
848 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
849 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
850 u32 len;
851 u32 ctrl;
852 dma_addr_t mapping;
853
854 len = this_frag->size;
855 mapping = pci_map_single(cp->pdev,
856 ((void *) page_address(this_frag->page) +
857 this_frag->page_offset),
858 len, PCI_DMA_TODEVICE);
859 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
860
861 ctrl = eor | len | DescOwn;
862
863 if (mss)
864 ctrl |= LargeSend |
865 ((mss & MSSMask) << MSSShift);
866 else if (skb->ip_summed == CHECKSUM_HW) {
867 if (ip->protocol == IPPROTO_TCP)
868 ctrl |= IPCS | TCPCS;
869 else if (ip->protocol == IPPROTO_UDP)
870 ctrl |= IPCS | UDPCS;
871 else
872 BUG();
873 }
874
875 if (frag == skb_shinfo(skb)->nr_frags - 1)
876 ctrl |= LastFrag;
877
878 txd = &cp->tx_ring[entry];
879 CP_VLAN_TX_TAG(txd, vlan_tag);
880 txd->addr = cpu_to_le64(mapping);
881 wmb();
882
883 txd->opts1 = cpu_to_le32(ctrl);
884 wmb();
885
886 cp->tx_skb[entry].skb = skb;
887 cp->tx_skb[entry].mapping = mapping;
888 cp->tx_skb[entry].len = len;
889 entry = NEXT_TX(entry);
890 }
891
892 txd = &cp->tx_ring[first_entry];
893 CP_VLAN_TX_TAG(txd, vlan_tag);
894 txd->addr = cpu_to_le64(first_mapping);
895 wmb();
896
897 if (skb->ip_summed == CHECKSUM_HW) {
898 if (ip->protocol == IPPROTO_TCP)
899 txd->opts1 = cpu_to_le32(first_eor | first_len |
900 FirstFrag | DescOwn |
901 IPCS | TCPCS);
902 else if (ip->protocol == IPPROTO_UDP)
903 txd->opts1 = cpu_to_le32(first_eor | first_len |
904 FirstFrag | DescOwn |
905 IPCS | UDPCS);
906 else
907 BUG();
908 } else
909 txd->opts1 = cpu_to_le32(first_eor | first_len |
910 FirstFrag | DescOwn);
911 wmb();
912 }
913 cp->tx_head = entry;
914 if (netif_msg_tx_queued(cp))
915 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
916 dev->name, entry, skb->len);
917 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
918 netif_stop_queue(dev);
919
920 spin_unlock_irq(&cp->lock);
921
922 cpw8(TxPoll, NormalTxPoll);
923 dev->trans_start = jiffies;
924
925 return 0;
926 }
927
928 /* Set or clear the multicast filter for this adaptor.
929 This routine is not state sensitive and need not be SMP locked. */
930
931 static void __cp_set_rx_mode (struct net_device *dev)
932 {
933 struct cp_private *cp = netdev_priv(dev);
934 u32 mc_filter[2]; /* Multicast hash filter */
935 int i, rx_mode;
936 u32 tmp;
937
938 /* Note: do not reorder, GCC is clever about common statements. */
939 if (dev->flags & IFF_PROMISC) {
940 /* Unconditionally log net taps. */
941 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
942 dev->name);
943 rx_mode =
944 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
945 AcceptAllPhys;
946 mc_filter[1] = mc_filter[0] = 0xffffffff;
947 } else if ((dev->mc_count > multicast_filter_limit)
948 || (dev->flags & IFF_ALLMULTI)) {
949 /* Too many to filter perfectly -- accept all multicasts. */
950 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
951 mc_filter[1] = mc_filter[0] = 0xffffffff;
952 } else {
953 struct dev_mc_list *mclist;
954 rx_mode = AcceptBroadcast | AcceptMyPhys;
955 mc_filter[1] = mc_filter[0] = 0;
956 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
957 i++, mclist = mclist->next) {
958 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
959
960 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
961 rx_mode |= AcceptMulticast;
962 }
963 }
964
965 /* We can safely update without stopping the chip. */
966 tmp = cp_rx_config | rx_mode;
967 if (cp->rx_config != tmp) {
968 cpw32_f (RxConfig, tmp);
969 cp->rx_config = tmp;
970 }
971 cpw32_f (MAR0 + 0, mc_filter[0]);
972 cpw32_f (MAR0 + 4, mc_filter[1]);
973 }
974
975 static void cp_set_rx_mode (struct net_device *dev)
976 {
977 unsigned long flags;
978 struct cp_private *cp = netdev_priv(dev);
979
980 spin_lock_irqsave (&cp->lock, flags);
981 __cp_set_rx_mode(dev);
982 spin_unlock_irqrestore (&cp->lock, flags);
983 }
984
985 static void __cp_get_stats(struct cp_private *cp)
986 {
987 /* only lower 24 bits valid; write any value to clear */
988 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
989 cpw32 (RxMissed, 0);
990 }
991
992 static struct net_device_stats *cp_get_stats(struct net_device *dev)
993 {
994 struct cp_private *cp = netdev_priv(dev);
995 unsigned long flags;
996
997 /* The chip only need report frame silently dropped. */
998 spin_lock_irqsave(&cp->lock, flags);
999 if (netif_running(dev) && netif_device_present(dev))
1000 __cp_get_stats(cp);
1001 spin_unlock_irqrestore(&cp->lock, flags);
1002
1003 return &cp->net_stats;
1004 }
1005
1006 static void cp_stop_hw (struct cp_private *cp)
1007 {
1008 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1009 cpw16_f(IntrMask, 0);
1010 cpw8(Cmd, 0);
1011 cpw16_f(CpCmd, 0);
1012 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1013
1014 cp->rx_tail = 0;
1015 cp->tx_head = cp->tx_tail = 0;
1016 }
1017
1018 static void cp_reset_hw (struct cp_private *cp)
1019 {
1020 unsigned work = 1000;
1021
1022 cpw8(Cmd, CmdReset);
1023
1024 while (work--) {
1025 if (!(cpr8(Cmd) & CmdReset))
1026 return;
1027
1028 schedule_timeout_uninterruptible(10);
1029 }
1030
1031 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1032 }
1033
1034 static inline void cp_start_hw (struct cp_private *cp)
1035 {
1036 cpw16(CpCmd, cp->cpcmd);
1037 cpw8(Cmd, RxOn | TxOn);
1038 }
1039
1040 static void cp_init_hw (struct cp_private *cp)
1041 {
1042 struct net_device *dev = cp->dev;
1043 dma_addr_t ring_dma;
1044
1045 cp_reset_hw(cp);
1046
1047 cpw8_f (Cfg9346, Cfg9346_Unlock);
1048
1049 /* Restore our idea of the MAC address. */
1050 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1051 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1052
1053 cp_start_hw(cp);
1054 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1055
1056 __cp_set_rx_mode(dev);
1057 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1058
1059 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1060 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1061 cpw8(Config3, PARMEnable);
1062 cp->wol_enabled = 0;
1063
1064 cpw8(Config5, cpr8(Config5) & PMEStatus);
1065
1066 cpw32_f(HiTxRingAddr, 0);
1067 cpw32_f(HiTxRingAddr + 4, 0);
1068
1069 ring_dma = cp->ring_dma;
1070 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1071 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1072
1073 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1074 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1075 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1076
1077 cpw16(MultiIntr, 0);
1078
1079 cpw16_f(IntrMask, cp_intr_mask);
1080
1081 cpw8_f(Cfg9346, Cfg9346_Lock);
1082 }
1083
1084 static int cp_refill_rx (struct cp_private *cp)
1085 {
1086 unsigned i;
1087
1088 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1089 struct sk_buff *skb;
1090
1091 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1092 if (!skb)
1093 goto err_out;
1094
1095 skb->dev = cp->dev;
1096 skb_reserve(skb, RX_OFFSET);
1097
1098 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1099 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1100 cp->rx_skb[i].skb = skb;
1101
1102 cp->rx_ring[i].opts2 = 0;
1103 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1104 if (i == (CP_RX_RING_SIZE - 1))
1105 cp->rx_ring[i].opts1 =
1106 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1107 else
1108 cp->rx_ring[i].opts1 =
1109 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1110 }
1111
1112 return 0;
1113
1114 err_out:
1115 cp_clean_rings(cp);
1116 return -ENOMEM;
1117 }
1118
1119 static void cp_init_rings_index (struct cp_private *cp)
1120 {
1121 cp->rx_tail = 0;
1122 cp->tx_head = cp->tx_tail = 0;
1123 }
1124
1125 static int cp_init_rings (struct cp_private *cp)
1126 {
1127 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1128 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1129
1130 cp_init_rings_index(cp);
1131
1132 return cp_refill_rx (cp);
1133 }
1134
1135 static int cp_alloc_rings (struct cp_private *cp)
1136 {
1137 void *mem;
1138
1139 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1140 if (!mem)
1141 return -ENOMEM;
1142
1143 cp->rx_ring = mem;
1144 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1145
1146 return cp_init_rings(cp);
1147 }
1148
1149 static void cp_clean_rings (struct cp_private *cp)
1150 {
1151 unsigned i;
1152
1153 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1154 if (cp->rx_skb[i].skb) {
1155 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1156 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1157 dev_kfree_skb(cp->rx_skb[i].skb);
1158 }
1159 }
1160
1161 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1162 if (cp->tx_skb[i].skb) {
1163 struct sk_buff *skb = cp->tx_skb[i].skb;
1164
1165 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1166 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1167 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1168 dev_kfree_skb(skb);
1169 cp->net_stats.tx_dropped++;
1170 }
1171 }
1172
1173 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1174 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1175
1176 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1177 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1178 }
1179
1180 static void cp_free_rings (struct cp_private *cp)
1181 {
1182 cp_clean_rings(cp);
1183 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1184 cp->rx_ring = NULL;
1185 cp->tx_ring = NULL;
1186 }
1187
1188 static int cp_open (struct net_device *dev)
1189 {
1190 struct cp_private *cp = netdev_priv(dev);
1191 int rc;
1192
1193 if (netif_msg_ifup(cp))
1194 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1195
1196 rc = cp_alloc_rings(cp);
1197 if (rc)
1198 return rc;
1199
1200 cp_init_hw(cp);
1201
1202 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1203 if (rc)
1204 goto err_out_hw;
1205
1206 netif_carrier_off(dev);
1207 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1208 netif_start_queue(dev);
1209
1210 return 0;
1211
1212 err_out_hw:
1213 cp_stop_hw(cp);
1214 cp_free_rings(cp);
1215 return rc;
1216 }
1217
1218 static int cp_close (struct net_device *dev)
1219 {
1220 struct cp_private *cp = netdev_priv(dev);
1221 unsigned long flags;
1222
1223 if (netif_msg_ifdown(cp))
1224 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1225
1226 spin_lock_irqsave(&cp->lock, flags);
1227
1228 netif_stop_queue(dev);
1229 netif_carrier_off(dev);
1230
1231 cp_stop_hw(cp);
1232
1233 spin_unlock_irqrestore(&cp->lock, flags);
1234
1235 synchronize_irq(dev->irq);
1236 free_irq(dev->irq, dev);
1237
1238 cp_free_rings(cp);
1239 return 0;
1240 }
1241
1242 #ifdef BROKEN
1243 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1244 {
1245 struct cp_private *cp = netdev_priv(dev);
1246 int rc;
1247 unsigned long flags;
1248
1249 /* check for invalid MTU, according to hardware limits */
1250 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1251 return -EINVAL;
1252
1253 /* if network interface not up, no need for complexity */
1254 if (!netif_running(dev)) {
1255 dev->mtu = new_mtu;
1256 cp_set_rxbufsize(cp); /* set new rx buf size */
1257 return 0;
1258 }
1259
1260 spin_lock_irqsave(&cp->lock, flags);
1261
1262 cp_stop_hw(cp); /* stop h/w and free rings */
1263 cp_clean_rings(cp);
1264
1265 dev->mtu = new_mtu;
1266 cp_set_rxbufsize(cp); /* set new rx buf size */
1267
1268 rc = cp_init_rings(cp); /* realloc and restart h/w */
1269 cp_start_hw(cp);
1270
1271 spin_unlock_irqrestore(&cp->lock, flags);
1272
1273 return rc;
1274 }
1275 #endif /* BROKEN */
1276
1277 static const char mii_2_8139_map[8] = {
1278 BasicModeCtrl,
1279 BasicModeStatus,
1280 0,
1281 0,
1282 NWayAdvert,
1283 NWayLPAR,
1284 NWayExpansion,
1285 0
1286 };
1287
1288 static int mdio_read(struct net_device *dev, int phy_id, int location)
1289 {
1290 struct cp_private *cp = netdev_priv(dev);
1291
1292 return location < 8 && mii_2_8139_map[location] ?
1293 readw(cp->regs + mii_2_8139_map[location]) : 0;
1294 }
1295
1296
1297 static void mdio_write(struct net_device *dev, int phy_id, int location,
1298 int value)
1299 {
1300 struct cp_private *cp = netdev_priv(dev);
1301
1302 if (location == 0) {
1303 cpw8(Cfg9346, Cfg9346_Unlock);
1304 cpw16(BasicModeCtrl, value);
1305 cpw8(Cfg9346, Cfg9346_Lock);
1306 } else if (location < 8 && mii_2_8139_map[location])
1307 cpw16(mii_2_8139_map[location], value);
1308 }
1309
1310 /* Set the ethtool Wake-on-LAN settings */
1311 static int netdev_set_wol (struct cp_private *cp,
1312 const struct ethtool_wolinfo *wol)
1313 {
1314 u8 options;
1315
1316 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1317 /* If WOL is being disabled, no need for complexity */
1318 if (wol->wolopts) {
1319 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1320 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1321 }
1322
1323 cpw8 (Cfg9346, Cfg9346_Unlock);
1324 cpw8 (Config3, options);
1325 cpw8 (Cfg9346, Cfg9346_Lock);
1326
1327 options = 0; /* Paranoia setting */
1328 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1329 /* If WOL is being disabled, no need for complexity */
1330 if (wol->wolopts) {
1331 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1332 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1333 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1334 }
1335
1336 cpw8 (Config5, options);
1337
1338 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1339
1340 return 0;
1341 }
1342
1343 /* Get the ethtool Wake-on-LAN settings */
1344 static void netdev_get_wol (struct cp_private *cp,
1345 struct ethtool_wolinfo *wol)
1346 {
1347 u8 options;
1348
1349 wol->wolopts = 0; /* Start from scratch */
1350 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1351 WAKE_MCAST | WAKE_UCAST;
1352 /* We don't need to go on if WOL is disabled */
1353 if (!cp->wol_enabled) return;
1354
1355 options = cpr8 (Config3);
1356 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1357 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1358
1359 options = 0; /* Paranoia setting */
1360 options = cpr8 (Config5);
1361 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1362 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1363 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1364 }
1365
1366 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1367 {
1368 struct cp_private *cp = netdev_priv(dev);
1369
1370 strcpy (info->driver, DRV_NAME);
1371 strcpy (info->version, DRV_VERSION);
1372 strcpy (info->bus_info, pci_name(cp->pdev));
1373 }
1374
1375 static int cp_get_regs_len(struct net_device *dev)
1376 {
1377 return CP_REGS_SIZE;
1378 }
1379
1380 static int cp_get_stats_count (struct net_device *dev)
1381 {
1382 return CP_NUM_STATS;
1383 }
1384
1385 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1386 {
1387 struct cp_private *cp = netdev_priv(dev);
1388 int rc;
1389 unsigned long flags;
1390
1391 spin_lock_irqsave(&cp->lock, flags);
1392 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1393 spin_unlock_irqrestore(&cp->lock, flags);
1394
1395 return rc;
1396 }
1397
1398 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1399 {
1400 struct cp_private *cp = netdev_priv(dev);
1401 int rc;
1402 unsigned long flags;
1403
1404 spin_lock_irqsave(&cp->lock, flags);
1405 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1406 spin_unlock_irqrestore(&cp->lock, flags);
1407
1408 return rc;
1409 }
1410
1411 static int cp_nway_reset(struct net_device *dev)
1412 {
1413 struct cp_private *cp = netdev_priv(dev);
1414 return mii_nway_restart(&cp->mii_if);
1415 }
1416
1417 static u32 cp_get_msglevel(struct net_device *dev)
1418 {
1419 struct cp_private *cp = netdev_priv(dev);
1420 return cp->msg_enable;
1421 }
1422
1423 static void cp_set_msglevel(struct net_device *dev, u32 value)
1424 {
1425 struct cp_private *cp = netdev_priv(dev);
1426 cp->msg_enable = value;
1427 }
1428
1429 static u32 cp_get_rx_csum(struct net_device *dev)
1430 {
1431 struct cp_private *cp = netdev_priv(dev);
1432 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1433 }
1434
1435 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1436 {
1437 struct cp_private *cp = netdev_priv(dev);
1438 u16 cmd = cp->cpcmd, newcmd;
1439
1440 newcmd = cmd;
1441
1442 if (data)
1443 newcmd |= RxChkSum;
1444 else
1445 newcmd &= ~RxChkSum;
1446
1447 if (newcmd != cmd) {
1448 unsigned long flags;
1449
1450 spin_lock_irqsave(&cp->lock, flags);
1451 cp->cpcmd = newcmd;
1452 cpw16_f(CpCmd, newcmd);
1453 spin_unlock_irqrestore(&cp->lock, flags);
1454 }
1455
1456 return 0;
1457 }
1458
1459 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1460 void *p)
1461 {
1462 struct cp_private *cp = netdev_priv(dev);
1463 unsigned long flags;
1464
1465 if (regs->len < CP_REGS_SIZE)
1466 return /* -EINVAL */;
1467
1468 regs->version = CP_REGS_VER;
1469
1470 spin_lock_irqsave(&cp->lock, flags);
1471 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1472 spin_unlock_irqrestore(&cp->lock, flags);
1473 }
1474
1475 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1476 {
1477 struct cp_private *cp = netdev_priv(dev);
1478 unsigned long flags;
1479
1480 spin_lock_irqsave (&cp->lock, flags);
1481 netdev_get_wol (cp, wol);
1482 spin_unlock_irqrestore (&cp->lock, flags);
1483 }
1484
1485 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1486 {
1487 struct cp_private *cp = netdev_priv(dev);
1488 unsigned long flags;
1489 int rc;
1490
1491 spin_lock_irqsave (&cp->lock, flags);
1492 rc = netdev_set_wol (cp, wol);
1493 spin_unlock_irqrestore (&cp->lock, flags);
1494
1495 return rc;
1496 }
1497
1498 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1499 {
1500 switch (stringset) {
1501 case ETH_SS_STATS:
1502 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1503 break;
1504 default:
1505 BUG();
1506 break;
1507 }
1508 }
1509
1510 static void cp_get_ethtool_stats (struct net_device *dev,
1511 struct ethtool_stats *estats, u64 *tmp_stats)
1512 {
1513 struct cp_private *cp = netdev_priv(dev);
1514 struct cp_dma_stats *nic_stats;
1515 dma_addr_t dma;
1516 int i;
1517
1518 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1519 if (!nic_stats)
1520 return;
1521
1522 /* begin NIC statistics dump */
1523 cpw32(StatsAddr + 4, (u64)dma >> 32);
1524 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1525 cpr32(StatsAddr);
1526
1527 for (i = 0; i < 1000; i++) {
1528 if ((cpr32(StatsAddr) & DumpStats) == 0)
1529 break;
1530 udelay(10);
1531 }
1532 cpw32(StatsAddr, 0);
1533 cpw32(StatsAddr + 4, 0);
1534 cpr32(StatsAddr);
1535
1536 i = 0;
1537 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1538 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1540 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1541 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1542 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1543 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1544 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1545 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1546 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1547 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1548 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1549 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1550 tmp_stats[i++] = cp->cp_stats.rx_frags;
1551 BUG_ON(i != CP_NUM_STATS);
1552
1553 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1554 }
1555
1556 static struct ethtool_ops cp_ethtool_ops = {
1557 .get_drvinfo = cp_get_drvinfo,
1558 .get_regs_len = cp_get_regs_len,
1559 .get_stats_count = cp_get_stats_count,
1560 .get_settings = cp_get_settings,
1561 .set_settings = cp_set_settings,
1562 .nway_reset = cp_nway_reset,
1563 .get_link = ethtool_op_get_link,
1564 .get_msglevel = cp_get_msglevel,
1565 .set_msglevel = cp_set_msglevel,
1566 .get_rx_csum = cp_get_rx_csum,
1567 .set_rx_csum = cp_set_rx_csum,
1568 .get_tx_csum = ethtool_op_get_tx_csum,
1569 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1570 .get_sg = ethtool_op_get_sg,
1571 .set_sg = ethtool_op_set_sg,
1572 .get_tso = ethtool_op_get_tso,
1573 .set_tso = ethtool_op_set_tso,
1574 .get_regs = cp_get_regs,
1575 .get_wol = cp_get_wol,
1576 .set_wol = cp_set_wol,
1577 .get_strings = cp_get_strings,
1578 .get_ethtool_stats = cp_get_ethtool_stats,
1579 .get_perm_addr = ethtool_op_get_perm_addr,
1580 };
1581
1582 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1583 {
1584 struct cp_private *cp = netdev_priv(dev);
1585 int rc;
1586 unsigned long flags;
1587
1588 if (!netif_running(dev))
1589 return -EINVAL;
1590
1591 spin_lock_irqsave(&cp->lock, flags);
1592 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1593 spin_unlock_irqrestore(&cp->lock, flags);
1594 return rc;
1595 }
1596
1597 /* Serial EEPROM section. */
1598
1599 /* EEPROM_Ctrl bits. */
1600 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1601 #define EE_CS 0x08 /* EEPROM chip select. */
1602 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1603 #define EE_WRITE_0 0x00
1604 #define EE_WRITE_1 0x02
1605 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1606 #define EE_ENB (0x80 | EE_CS)
1607
1608 /* Delay between EEPROM clock transitions.
1609 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1610 */
1611
1612 #define eeprom_delay() readl(ee_addr)
1613
1614 /* The EEPROM commands include the alway-set leading bit. */
1615 #define EE_WRITE_CMD (5)
1616 #define EE_READ_CMD (6)
1617 #define EE_ERASE_CMD (7)
1618
1619 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1620 {
1621 int i;
1622 unsigned retval = 0;
1623 void __iomem *ee_addr = ioaddr + Cfg9346;
1624 int read_cmd = location | (EE_READ_CMD << addr_len);
1625
1626 writeb (EE_ENB & ~EE_CS, ee_addr);
1627 writeb (EE_ENB, ee_addr);
1628 eeprom_delay ();
1629
1630 /* Shift the read command bits out. */
1631 for (i = 4 + addr_len; i >= 0; i--) {
1632 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1633 writeb (EE_ENB | dataval, ee_addr);
1634 eeprom_delay ();
1635 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1636 eeprom_delay ();
1637 }
1638 writeb (EE_ENB, ee_addr);
1639 eeprom_delay ();
1640
1641 for (i = 16; i > 0; i--) {
1642 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1643 eeprom_delay ();
1644 retval =
1645 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1646 0);
1647 writeb (EE_ENB, ee_addr);
1648 eeprom_delay ();
1649 }
1650
1651 /* Terminate the EEPROM access. */
1652 writeb (~EE_CS, ee_addr);
1653 eeprom_delay ();
1654
1655 return retval;
1656 }
1657
1658 /* Put the board into D3cold state and wait for WakeUp signal */
1659 static void cp_set_d3_state (struct cp_private *cp)
1660 {
1661 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1662 pci_set_power_state (cp->pdev, PCI_D3hot);
1663 }
1664
1665 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1666 {
1667 struct net_device *dev;
1668 struct cp_private *cp;
1669 int rc;
1670 void __iomem *regs;
1671 long pciaddr;
1672 unsigned int addr_len, i, pci_using_dac;
1673 u8 pci_rev;
1674
1675 #ifndef MODULE
1676 static int version_printed;
1677 if (version_printed++ == 0)
1678 printk("%s", version);
1679 #endif
1680
1681 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1682
1683 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1684 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1685 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1686 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1687 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1688 return -ENODEV;
1689 }
1690
1691 dev = alloc_etherdev(sizeof(struct cp_private));
1692 if (!dev)
1693 return -ENOMEM;
1694 SET_MODULE_OWNER(dev);
1695 SET_NETDEV_DEV(dev, &pdev->dev);
1696
1697 cp = netdev_priv(dev);
1698 cp->pdev = pdev;
1699 cp->dev = dev;
1700 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1701 spin_lock_init (&cp->lock);
1702 cp->mii_if.dev = dev;
1703 cp->mii_if.mdio_read = mdio_read;
1704 cp->mii_if.mdio_write = mdio_write;
1705 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1706 cp->mii_if.phy_id_mask = 0x1f;
1707 cp->mii_if.reg_num_mask = 0x1f;
1708 cp_set_rxbufsize(cp);
1709
1710 rc = pci_enable_device(pdev);
1711 if (rc)
1712 goto err_out_free;
1713
1714 rc = pci_set_mwi(pdev);
1715 if (rc)
1716 goto err_out_disable;
1717
1718 rc = pci_request_regions(pdev, DRV_NAME);
1719 if (rc)
1720 goto err_out_mwi;
1721
1722 pciaddr = pci_resource_start(pdev, 1);
1723 if (!pciaddr) {
1724 rc = -EIO;
1725 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1726 pci_name(pdev));
1727 goto err_out_res;
1728 }
1729 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1730 rc = -EIO;
1731 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1732 pci_resource_len(pdev, 1), pci_name(pdev));
1733 goto err_out_res;
1734 }
1735
1736 /* Configure DMA attributes. */
1737 if ((sizeof(dma_addr_t) > 4) &&
1738 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1739 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1740 pci_using_dac = 1;
1741 } else {
1742 pci_using_dac = 0;
1743
1744 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1745 if (rc) {
1746 printk(KERN_ERR PFX "No usable DMA configuration, "
1747 "aborting.\n");
1748 goto err_out_res;
1749 }
1750 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1751 if (rc) {
1752 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1753 "aborting.\n");
1754 goto err_out_res;
1755 }
1756 }
1757
1758 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1759 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1760
1761 regs = ioremap(pciaddr, CP_REGS_SIZE);
1762 if (!regs) {
1763 rc = -EIO;
1764 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1765 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1766 goto err_out_res;
1767 }
1768 dev->base_addr = (unsigned long) regs;
1769 cp->regs = regs;
1770
1771 cp_stop_hw(cp);
1772
1773 /* read MAC address from EEPROM */
1774 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1775 for (i = 0; i < 3; i++)
1776 ((u16 *) (dev->dev_addr))[i] =
1777 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1778 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1779
1780 dev->open = cp_open;
1781 dev->stop = cp_close;
1782 dev->set_multicast_list = cp_set_rx_mode;
1783 dev->hard_start_xmit = cp_start_xmit;
1784 dev->get_stats = cp_get_stats;
1785 dev->do_ioctl = cp_ioctl;
1786 dev->poll = cp_rx_poll;
1787 #ifdef CONFIG_NET_POLL_CONTROLLER
1788 dev->poll_controller = cp_poll_controller;
1789 #endif
1790 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1791 #ifdef BROKEN
1792 dev->change_mtu = cp_change_mtu;
1793 #endif
1794 dev->ethtool_ops = &cp_ethtool_ops;
1795 #if 0
1796 dev->tx_timeout = cp_tx_timeout;
1797 dev->watchdog_timeo = TX_TIMEOUT;
1798 #endif
1799
1800 #if CP_VLAN_TAG_USED
1801 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1802 dev->vlan_rx_register = cp_vlan_rx_register;
1803 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1804 #endif
1805
1806 if (pci_using_dac)
1807 dev->features |= NETIF_F_HIGHDMA;
1808
1809 #if 0 /* disabled by default until verified */
1810 dev->features |= NETIF_F_TSO;
1811 #endif
1812
1813 dev->irq = pdev->irq;
1814
1815 rc = register_netdev(dev);
1816 if (rc)
1817 goto err_out_iomap;
1818
1819 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1820 "%02x:%02x:%02x:%02x:%02x:%02x, "
1821 "IRQ %d\n",
1822 dev->name,
1823 dev->base_addr,
1824 dev->dev_addr[0], dev->dev_addr[1],
1825 dev->dev_addr[2], dev->dev_addr[3],
1826 dev->dev_addr[4], dev->dev_addr[5],
1827 dev->irq);
1828
1829 pci_set_drvdata(pdev, dev);
1830
1831 /* enable busmastering and memory-write-invalidate */
1832 pci_set_master(pdev);
1833
1834 if (cp->wol_enabled) cp_set_d3_state (cp);
1835
1836 return 0;
1837
1838 err_out_iomap:
1839 iounmap(regs);
1840 err_out_res:
1841 pci_release_regions(pdev);
1842 err_out_mwi:
1843 pci_clear_mwi(pdev);
1844 err_out_disable:
1845 pci_disable_device(pdev);
1846 err_out_free:
1847 free_netdev(dev);
1848 return rc;
1849 }
1850
1851 static void cp_remove_one (struct pci_dev *pdev)
1852 {
1853 struct net_device *dev = pci_get_drvdata(pdev);
1854 struct cp_private *cp = netdev_priv(dev);
1855
1856 BUG_ON(!dev);
1857 unregister_netdev(dev);
1858 iounmap(cp->regs);
1859 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1860 pci_release_regions(pdev);
1861 pci_clear_mwi(pdev);
1862 pci_disable_device(pdev);
1863 pci_set_drvdata(pdev, NULL);
1864 free_netdev(dev);
1865 }
1866
1867 #ifdef CONFIG_PM
1868 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1869 {
1870 struct net_device *dev;
1871 struct cp_private *cp;
1872 unsigned long flags;
1873
1874 dev = pci_get_drvdata (pdev);
1875 cp = netdev_priv(dev);
1876
1877 if (!dev || !netif_running (dev)) return 0;
1878
1879 netif_device_detach (dev);
1880 netif_stop_queue (dev);
1881
1882 spin_lock_irqsave (&cp->lock, flags);
1883
1884 /* Disable Rx and Tx */
1885 cpw16 (IntrMask, 0);
1886 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1887
1888 spin_unlock_irqrestore (&cp->lock, flags);
1889
1890 pci_save_state(pdev);
1891 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
1892 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1893
1894 return 0;
1895 }
1896
1897 static int cp_resume (struct pci_dev *pdev)
1898 {
1899 struct net_device *dev = pci_get_drvdata (pdev);
1900 struct cp_private *cp = netdev_priv(dev);
1901 unsigned long flags;
1902
1903 if (!netif_running(dev))
1904 return 0;
1905
1906 netif_device_attach (dev);
1907
1908 pci_set_power_state(pdev, PCI_D0);
1909 pci_restore_state(pdev);
1910 pci_enable_wake(pdev, PCI_D0, 0);
1911
1912 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
1913 cp_init_rings_index (cp);
1914 cp_init_hw (cp);
1915 netif_start_queue (dev);
1916
1917 spin_lock_irqsave (&cp->lock, flags);
1918
1919 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
1920
1921 spin_unlock_irqrestore (&cp->lock, flags);
1922
1923 return 0;
1924 }
1925 #endif /* CONFIG_PM */
1926
1927 static struct pci_driver cp_driver = {
1928 .name = DRV_NAME,
1929 .id_table = cp_pci_tbl,
1930 .probe = cp_init_one,
1931 .remove = cp_remove_one,
1932 #ifdef CONFIG_PM
1933 .resume = cp_resume,
1934 .suspend = cp_suspend,
1935 #endif
1936 };
1937
1938 static int __init cp_init (void)
1939 {
1940 #ifdef MODULE
1941 printk("%s", version);
1942 #endif
1943 return pci_module_init (&cp_driver);
1944 }
1945
1946 static void __exit cp_exit (void)
1947 {
1948 pci_unregister_driver (&cp_driver);
1949 }
1950
1951 module_init(cp_init);
1952 module_exit(cp_exit);
linux kernel for loongson