arch/arm/mach-pxa/gpio.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/gpio.c
   3  *
   4  *  Generic PXA GPIO handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/gpio.h>
  22 #include <mach/hardware.h>
  23 #include <mach/pxa-regs.h>
  24 #include <mach/pxa2xx-gpio.h>
  25
  26 #include "generic.h"
  27
  28 #define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
  29 #define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
  30 #define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
  31 #define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
  32
  33 #define GPLR_OFFSET     0x00
  34 #define GPDR_OFFSET     0x0C
  35 #define GPSR_OFFSET     0x18
  36 #define GPCR_OFFSET     0x24
  37 #define GRER_OFFSET     0x30
  38 #define GFER_OFFSET     0x3C
  39 #define GEDR_OFFSET     0x48
  40
  41 struct pxa_gpio_chip {
  42         struct gpio_chip chip;
  43         void __iomem     *regbase;
  44 };
  45
  46 int pxa_last_gpio;
  47
  48 #ifdef CONFIG_CPU_PXA26x
  49 /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
  50  * as well as their Alternate Function value being '1' for GPIO in GAFRx.
  51  */
  52 static int __gpio_is_inverted(unsigned gpio)
  53 {
  54         return cpu_is_pxa25x() && gpio > 85;
  55 }
  56 #else
  57 #define __gpio_is_inverted(gpio)        (0)
  58 #endif
  59
  60 /*
  61  * Configure pins for GPIO or other functions
  62  */
  63 int pxa_gpio_mode(int gpio_mode)
  64 {
  65         unsigned long flags;
  66         int gpio = gpio_mode & GPIO_MD_MASK_NR;
  67         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
  68         int gafr;
  69
  70         if (gpio > pxa_last_gpio)
  71                 return -EINVAL;
  72
  73         local_irq_save(flags);
  74         if (gpio_mode & GPIO_DFLT_LOW)
  75                 GPCR(gpio) = GPIO_bit(gpio);
  76         else if (gpio_mode & GPIO_DFLT_HIGH)
  77                 GPSR(gpio) = GPIO_bit(gpio);
  78         if (gpio_mode & GPIO_MD_MASK_DIR)
  79                 GPDR(gpio) |= GPIO_bit(gpio);
  80         else
  81                 GPDR(gpio) &= ~GPIO_bit(gpio);
  82         gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
  83         GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
  84         local_irq_restore(flags);
  85
  86         return 0;
  87 }
  88 EXPORT_SYMBOL(pxa_gpio_mode);
  89
  90 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  91 {
  92         unsigned long        flags;
  93         u32                  mask = 1 << offset;
  94         u32                  value;
  95         struct pxa_gpio_chip *pxa;
  96         void __iomem         *gpdr;
  97
  98         pxa = container_of(chip, struct pxa_gpio_chip, chip);
  99         gpdr = pxa->regbase + GPDR_OFFSET;
 100         local_irq_save(flags);
 101         value = __raw_readl(gpdr);
 102         if (__gpio_is_inverted(chip->base + offset))
 103                 value |= mask;
 104         else
 105                 value &= ~mask;
 106         __raw_writel(value, gpdr);
 107         local_irq_restore(flags);
 108
 109         return 0;
 110 }
 111
 112 static int pxa_gpio_direction_output(struct gpio_chip *chip,
 113                                         unsigned offset, int value)
 114 {
 115         unsigned long        flags;
 116         u32                  mask = 1 << offset;
 117         u32                  tmp;
 118         struct pxa_gpio_chip *pxa;
 119         void __iomem         *gpdr;
 120
 121         pxa = container_of(chip, struct pxa_gpio_chip, chip);
 122         __raw_writel(mask,
 123                         pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
 124         gpdr = pxa->regbase + GPDR_OFFSET;
 125         local_irq_save(flags);
 126         tmp = __raw_readl(gpdr);
 127         if (__gpio_is_inverted(chip->base + offset))
 128                 tmp &= ~mask;
 129         else
 130                 tmp |= mask;
 131         __raw_writel(tmp, gpdr);
 132         local_irq_restore(flags);
 133
 134         return 0;
 135 }
 136
 137 /*
 138  * Return GPIO level
 139  */
 140 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 141 {
 142         u32                  mask = 1 << offset;
 143         struct pxa_gpio_chip *pxa;
 144
 145         pxa = container_of(chip, struct pxa_gpio_chip, chip);
 146         return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
 147 }
 148
 149 /*
 150  * Set output GPIO level
 151  */
 152 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 153 {
 154         u32                  mask = 1 << offset;
 155         struct pxa_gpio_chip *pxa;
 156
 157         pxa = container_of(chip, struct pxa_gpio_chip, chip);
 158
 159         if (value)
 160                 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
 161         else
 162                 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
 163 }
 164
 165 #define GPIO_CHIP(_n)                                                   \
 166         [_n] = {                                                        \
 167                 .regbase = GPIO##_n##_BASE,                             \
 168                 .chip = {                                               \
 169                         .label            = "gpio-" #_n,                \
 170                         .direction_input  = pxa_gpio_direction_input,   \
 171                         .direction_output = pxa_gpio_direction_output,  \
 172                         .get              = pxa_gpio_get,               \
 173                         .set              = pxa_gpio_set,               \
 174                         .base             = (_n) * 32,                  \
 175                         .ngpio            = 32,                         \
 176                 },                                                      \
 177         }
 178
 179 static struct pxa_gpio_chip pxa_gpio_chip[] = {
 180         GPIO_CHIP(0),
 181         GPIO_CHIP(1),
 182         GPIO_CHIP(2),
 183 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 184         GPIO_CHIP(3),
 185 #endif
 186 };
 187
 188 /*
 189  * PXA GPIO edge detection for IRQs:
 190  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 191  * Use this instead of directly setting GRER/GFER.
 192  */
 193
 194 static unsigned long GPIO_IRQ_rising_edge[4];
 195 static unsigned long GPIO_IRQ_falling_edge[4];
 196 static unsigned long GPIO_IRQ_mask[4];
 197
 198 /*
 199  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 200  * function of a GPIO, and GPDRx cannot be altered once configured. It
 201  * is attributed as "occupied" here (I know this terminology isn't
 202  * accurate, you are welcome to propose a better one :-)
 203  */
 204 static int __gpio_is_occupied(unsigned gpio)
 205 {
 206         if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
 207                 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
 208                 int dir = GPDR(gpio) & GPIO_bit(gpio);
 209
 210                 if (__gpio_is_inverted(gpio))
 211                         return af != 1 || dir == 0;
 212                 else
 213                         return af != 0 || dir != 0;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 220 {
 221         int gpio, idx;
 222
 223         gpio = IRQ_TO_GPIO(irq);
 224         idx = gpio >> 5;
 225
 226         if (type == IRQ_TYPE_PROBE) {
 227                 /* Don't mess with enabled GPIOs using preconfigured edges or
 228                  * GPIOs set to alternate function or to output during probe
 229                  */
 230                 if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
 231                     (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
 232                         return 0;
 233
 234                 if (__gpio_is_occupied(gpio))
 235                         return 0;
 236
 237                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 238         }
 239
 240         if (__gpio_is_inverted(gpio))
 241                 GPDR(gpio) |= GPIO_bit(gpio);
 242         else
 243                 GPDR(gpio) &= ~GPIO_bit(gpio);
 244
 245         if (type & IRQ_TYPE_EDGE_RISING)
 246                 __set_bit(gpio, GPIO_IRQ_rising_edge);
 247         else
 248                 __clear_bit(gpio, GPIO_IRQ_rising_edge);
 249
 250         if (type & IRQ_TYPE_EDGE_FALLING)
 251                 __set_bit(gpio, GPIO_IRQ_falling_edge);
 252         else
 253                 __clear_bit(gpio, GPIO_IRQ_falling_edge);
 254
 255         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 256         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 257
 258         pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
 259                 ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
 260                 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
 261         return 0;
 262 }
 263
 264 /*
 265  * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
 266  */
 267
 268 static void pxa_ack_low_gpio(unsigned int irq)
 269 {
 270         GEDR0 = (1 << (irq - IRQ_GPIO0));
 271 }
 272
 273 static void pxa_mask_low_gpio(unsigned int irq)
 274 {
 275         ICMR &= ~(1 << (irq - PXA_IRQ(0)));
 276 }
 277
 278 static void pxa_unmask_low_gpio(unsigned int irq)
 279 {
 280         ICMR |= 1 << (irq - PXA_IRQ(0));
 281 }
 282
 283 static struct irq_chip pxa_low_gpio_chip = {
 284         .name           = "GPIO-l",
 285         .ack            = pxa_ack_low_gpio,
 286         .mask           = pxa_mask_low_gpio,
 287         .unmask         = pxa_unmask_low_gpio,
 288         .set_type       = pxa_gpio_irq_type,
 289 };
 290
 291 /*
 292  * Demux handler for GPIO>=2 edge detect interrupts
 293  */
 294
 295 #define GEDR_BITS       (sizeof(gedr) * BITS_PER_BYTE)
 296
 297 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 298 {
 299         int loop, bit, n;
 300         unsigned long gedr[4];
 301
 302         do {
 303                 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
 304                 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
 305                 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
 306                 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
 307
 308                 GEDR0 = gedr[0]; GEDR1 = gedr[1];
 309                 GEDR2 = gedr[2]; GEDR3 = gedr[3];
 310
 311                 loop = 0;
 312                 bit = find_first_bit(gedr, GEDR_BITS);
 313                 while (bit < GEDR_BITS) {
 314                         loop = 1;
 315
 316                         n = PXA_GPIO_IRQ_BASE + bit;
 317                         generic_handle_irq(n);
 318
 319                         bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
 320                 }
 321         } while (loop);
 322 }
 323
 324 static void pxa_ack_muxed_gpio(unsigned int irq)
 325 {
 326         int gpio = irq - IRQ_GPIO(2) + 2;
 327         GEDR(gpio) = GPIO_bit(gpio);
 328 }
 329
 330 static void pxa_mask_muxed_gpio(unsigned int irq)
 331 {
 332         int gpio = irq - IRQ_GPIO(2) + 2;
 333         __clear_bit(gpio, GPIO_IRQ_mask);
 334         GRER(gpio) &= ~GPIO_bit(gpio);
 335         GFER(gpio) &= ~GPIO_bit(gpio);
 336 }
 337
 338 static void pxa_unmask_muxed_gpio(unsigned int irq)
 339 {
 340         int gpio = irq - IRQ_GPIO(2) + 2;
 341         int idx = gpio >> 5;
 342         __set_bit(gpio, GPIO_IRQ_mask);
 343         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 344         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 345 }
 346
 347 static struct irq_chip pxa_muxed_gpio_chip = {
 348         .name           = "GPIO",
 349         .ack            = pxa_ack_muxed_gpio,
 350         .mask           = pxa_mask_muxed_gpio,
 351         .unmask         = pxa_unmask_muxed_gpio,
 352         .set_type       = pxa_gpio_irq_type,
 353 };
 354
 355 void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
 356 {
 357         int irq, i, gpio;
 358
 359         pxa_last_gpio = gpio_nr - 1;
 360
 361         /* clear all GPIO edge detects */
 362         for (i = 0; i < gpio_nr; i += 32) {
 363                 GFER(i) = 0;
 364                 GRER(i) = 0;
 365                 GEDR(i) = GEDR(i);
 366         }
 367
 368         /* GPIO 0 and 1 must have their mask bit always set */
 369         GPIO_IRQ_mask[0] = 3;
 370
 371         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 372                 set_irq_chip(irq, &pxa_low_gpio_chip);
 373                 set_irq_handler(irq, handle_edge_irq);
 374                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 375         }
 376
 377         for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
 378                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 379                 set_irq_handler(irq, handle_edge_irq);
 380                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 381         }
 382
 383         /* Install handler for GPIO>=2 edge detect interrupts */
 384         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 385
 386         pxa_low_gpio_chip.set_wake = fn;
 387         pxa_muxed_gpio_chip.set_wake = fn;
 388
 389         /* add a GPIO chip for each register bank.
 390          * the last PXA25x register only contains 21 GPIOs
 391          */
 392         for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
 393                 if (gpio + 32 > gpio_nr)
 394                         pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
 395                 gpiochip_add(&pxa_gpio_chip[i].chip);
 396         }
 397 }
 398
 399 #ifdef CONFIG_PM
 400
 401 static unsigned long saved_gplr[4];
 402 static unsigned long saved_gpdr[4];
 403 static unsigned long saved_grer[4];
 404 static unsigned long saved_gfer[4];
 405
 406 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
 407 {
 408         int i, gpio;
 409
 410         for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
 411                 saved_gplr[i] = GPLR(gpio);
 412                 saved_gpdr[i] = GPDR(gpio);
 413                 saved_grer[i] = GRER(gpio);
 414                 saved_gfer[i] = GFER(gpio);
 415
 416                 /* Clear GPIO transition detect bits */
 417                 GEDR(gpio) = GEDR(gpio);
 418         }
 419         return 0;
 420 }
 421
 422 static int pxa_gpio_resume(struct sys_device *dev)
 423 {
 424         int i, gpio;
 425
 426         for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
 427                 /* restore level with set/clear */
 428                 GPSR(gpio) = saved_gplr[i];
 429                 GPCR(gpio) = ~saved_gplr[i];
 430
 431                 GRER(gpio) = saved_grer[i];
 432                 GFER(gpio) = saved_gfer[i];
 433                 GPDR(gpio) = saved_gpdr[i];
 434         }
 435         return 0;
 436 }
 437 #else
 438 #define pxa_gpio_suspend        NULL
 439 #define pxa_gpio_resume         NULL
 440 #endif
 441
 442 struct sysdev_class pxa_gpio_sysclass = {
 443         .name           = "gpio",
 444         .suspend        = pxa_gpio_suspend,
 445         .resume         = pxa_gpio_resume,
 446 };
 447
 448 static int __init pxa_gpio_init(void)
 449 {
 450         return sysdev_class_register(&pxa_gpio_sysclass);
 451 }
 452
 453 core_initcall(pxa_gpio_init);