?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] exit: fix crash case
[linux-2.6/linux-loongson.git] / drivers / mtd / chips / cfi_cmdset_0002.c
blob702ae4cd8691c510e33ecc3892bccd0c16653f61
1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
17 *
18 * This code is GPL
19 *
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
29 #include <asm/io.h>
30 #include <asm/byteorder.h>
31
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_WORD_RETRIES 3
46
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_ATMEL 0x001F
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF008A 0x005a
52 #define AT49BV6416 0x00d6
53
54 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
55 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
56 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
57 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
58 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
59 static void cfi_amdstd_sync (struct mtd_info *);
60 static int cfi_amdstd_suspend (struct mtd_info *);
61 static void cfi_amdstd_resume (struct mtd_info *);
62 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63
64 static void cfi_amdstd_destroy(struct mtd_info *);
65
66 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
67 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
68
69 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
70 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
71 #include "fwh_lock.h"
72
73 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len);
74 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
75
76 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
77 .probe = NULL, /* Not usable directly */
78 .destroy = cfi_amdstd_destroy,
79 .name = "cfi_cmdset_0002",
80 .module = THIS_MODULE
81 };
82
83
84 /* #define DEBUG_CFI_FEATURES */
85
86
87 #ifdef DEBUG_CFI_FEATURES
88 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
89 {
90 const char* erase_suspend[3] = {
91 "Not supported", "Read only", "Read/write"
92 };
93 const char* top_bottom[6] = {
94 "No WP", "8x8KiB sectors at top & bottom, no WP",
95 "Bottom boot", "Top boot",
96 "Uniform, Bottom WP", "Uniform, Top WP"
97 };
98
99 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
100 printk(" Address sensitive unlock: %s\n",
101 (extp->SiliconRevision & 1) ? "Not required" : "Required");
102
103 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
104 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
105 else
106 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
107
108 if (extp->BlkProt == 0)
109 printk(" Block protection: Not supported\n");
110 else
111 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
112
113
114 printk(" Temporary block unprotect: %s\n",
115 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
116 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
117 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
118 printk(" Burst mode: %s\n",
119 extp->BurstMode ? "Supported" : "Not supported");
120 if (extp->PageMode == 0)
121 printk(" Page mode: Not supported\n");
122 else
123 printk(" Page mode: %d word page\n", extp->PageMode << 2);
124
125 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
126 extp->VppMin >> 4, extp->VppMin & 0xf);
127 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
128 extp->VppMax >> 4, extp->VppMax & 0xf);
129
130 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
131 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
132 else
133 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
134 }
135 #endif
136
137 #ifdef AMD_BOOTLOC_BUG
138 /* Wheee. Bring me the head of someone at AMD. */
139 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
140 {
141 struct map_info *map = mtd->priv;
142 struct cfi_private *cfi = map->fldrv_priv;
143 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
144 __u8 major = extp->MajorVersion;
145 __u8 minor = extp->MinorVersion;
146
147 if (((major << 8) | minor) < 0x3131) {
148 /* CFI version 1.0 => don't trust bootloc */
149 if (cfi->id & 0x80) {
150 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
151 extp->TopBottom = 3; /* top boot */
152 } else {
153 extp->TopBottom = 2; /* bottom boot */
154 }
155 }
156 }
157 #endif
158
159 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
160 {
161 struct map_info *map = mtd->priv;
162 struct cfi_private *cfi = map->fldrv_priv;
163 if (cfi->cfiq->BufWriteTimeoutTyp) {
164 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
165 mtd->write = cfi_amdstd_write_buffers;
166 }
167 }
168
169 /* Atmel chips don't use the same PRI format as AMD chips */
170 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
171 {
172 struct map_info *map = mtd->priv;
173 struct cfi_private *cfi = map->fldrv_priv;
174 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
175 struct cfi_pri_atmel atmel_pri;
176
177 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
178 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
179
180 if (atmel_pri.Features & 0x02)
181 extp->EraseSuspend = 2;
182
183 if (atmel_pri.BottomBoot)
184 extp->TopBottom = 2;
185 else
186 extp->TopBottom = 3;
187 }
188
189 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
190 {
191 /* Setup for chips with a secsi area */
192 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
193 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
194 }
195
196 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
197 {
198 struct map_info *map = mtd->priv;
199 struct cfi_private *cfi = map->fldrv_priv;
200 if ((cfi->cfiq->NumEraseRegions == 1) &&
201 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
202 mtd->erase = cfi_amdstd_erase_chip;
203 }
204
205 }
206
207 /*
208 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
209 * locked by default.
210 */
211 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
212 {
213 mtd->lock = cfi_atmel_lock;
214 mtd->unlock = cfi_atmel_unlock;
215 mtd->flags |= MTD_STUPID_LOCK;
216 }
217
218 static struct cfi_fixup cfi_fixup_table[] = {
219 #ifdef AMD_BOOTLOC_BUG
220 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
221 #endif
222 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
223 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
224 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
225 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
226 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
227 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
228 #if !FORCE_WORD_WRITE
229 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
230 #endif
231 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
232 { 0, 0, NULL, NULL }
233 };
234 static struct cfi_fixup jedec_fixup_table[] = {
235 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
236 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
237 { 0, 0, NULL, NULL }
238 };
239
240 static struct cfi_fixup fixup_table[] = {
241 /* The CFI vendor ids and the JEDEC vendor IDs appear
242 * to be common. It is like the devices id's are as
243 * well. This table is to pick all cases where
244 * we know that is the case.
245 */
246 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
247 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
248 { 0, 0, NULL, NULL }
249 };
250
251
252 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
253 {
254 struct cfi_private *cfi = map->fldrv_priv;
255 struct mtd_info *mtd;
256 int i;
257
258 mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
259 if (!mtd) {
260 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
261 return NULL;
262 }
263 memset(mtd, 0, sizeof(*mtd));
264 mtd->priv = map;
265 mtd->type = MTD_NORFLASH;
266
267 /* Fill in the default mtd operations */
268 mtd->erase = cfi_amdstd_erase_varsize;
269 mtd->write = cfi_amdstd_write_words;
270 mtd->read = cfi_amdstd_read;
271 mtd->sync = cfi_amdstd_sync;
272 mtd->suspend = cfi_amdstd_suspend;
273 mtd->resume = cfi_amdstd_resume;
274 mtd->flags = MTD_CAP_NORFLASH;
275 mtd->name = map->name;
276 mtd->writesize = 1;
277
278 if (cfi->cfi_mode==CFI_MODE_CFI){
279 unsigned char bootloc;
280 /*
281 * It's a real CFI chip, not one for which the probe
282 * routine faked a CFI structure. So we read the feature
283 * table from it.
284 */
285 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
286 struct cfi_pri_amdstd *extp;
287
288 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
289 if (!extp) {
290 kfree(mtd);
291 return NULL;
292 }
293
294 if (extp->MajorVersion != '1' ||
295 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
296 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
297 "version %c.%c.\n", extp->MajorVersion,
298 extp->MinorVersion);
299 kfree(extp);
300 kfree(mtd);
301 return NULL;
302 }
303
304 /* Install our own private info structure */
305 cfi->cmdset_priv = extp;
306
307 /* Apply cfi device specific fixups */
308 cfi_fixup(mtd, cfi_fixup_table);
309
310 #ifdef DEBUG_CFI_FEATURES
311 /* Tell the user about it in lots of lovely detail */
312 cfi_tell_features(extp);
313 #endif
314
315 bootloc = extp->TopBottom;
316 if ((bootloc != 2) && (bootloc != 3)) {
317 printk(KERN_WARNING "%s: CFI does not contain boot "
318 "bank location. Assuming top.\n", map->name);
319 bootloc = 2;
320 }
321
322 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
323 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
324
325 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
326 int j = (cfi->cfiq->NumEraseRegions-1)-i;
327 __u32 swap;
328
329 swap = cfi->cfiq->EraseRegionInfo[i];
330 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
331 cfi->cfiq->EraseRegionInfo[j] = swap;
332 }
333 }
334 /* Set the default CFI lock/unlock addresses */
335 cfi->addr_unlock1 = 0x555;
336 cfi->addr_unlock2 = 0x2aa;
337 /* Modify the unlock address if we are in compatibility mode */
338 if ( /* x16 in x8 mode */
339 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
340 (cfi->cfiq->InterfaceDesc == 2)) ||
341 /* x32 in x16 mode */
342 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
343 (cfi->cfiq->InterfaceDesc == 4)))
344 {
345 cfi->addr_unlock1 = 0xaaa;
346 cfi->addr_unlock2 = 0x555;
347 }
348
349 } /* CFI mode */
350 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
351 /* Apply jedec specific fixups */
352 cfi_fixup(mtd, jedec_fixup_table);
353 }
354 /* Apply generic fixups */
355 cfi_fixup(mtd, fixup_table);
356
357 for (i=0; i< cfi->numchips; i++) {
358 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
359 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
360 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
361 }
362
363 map->fldrv = &cfi_amdstd_chipdrv;
364
365 return cfi_amdstd_setup(mtd);
366 }
367 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
368
369 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
370 {
371 struct map_info *map = mtd->priv;
372 struct cfi_private *cfi = map->fldrv_priv;
373 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
374 unsigned long offset = 0;
375 int i,j;
376
377 printk(KERN_NOTICE "number of %s chips: %d\n",
378 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
379 /* Select the correct geometry setup */
380 mtd->size = devsize * cfi->numchips;
381
382 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
383 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
384 * mtd->numeraseregions, GFP_KERNEL);
385 if (!mtd->eraseregions) {
386 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
387 goto setup_err;
388 }
389
390 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
391 unsigned long ernum, ersize;
392 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
393 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
394
395 if (mtd->erasesize < ersize) {
396 mtd->erasesize = ersize;
397 }
398 for (j=0; j<cfi->numchips; j++) {
399 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
400 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
401 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
402 }
403 offset += (ersize * ernum);
404 }
405 if (offset != devsize) {
406 /* Argh */
407 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
408 goto setup_err;
409 }
410 #if 0
411 // debug
412 for (i=0; i<mtd->numeraseregions;i++){
413 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
414 i,mtd->eraseregions[i].offset,
415 mtd->eraseregions[i].erasesize,
416 mtd->eraseregions[i].numblocks);
417 }
418 #endif
419
420 /* FIXME: erase-suspend-program is broken. See
421 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
422 printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
423
424 __module_get(THIS_MODULE);
425 return mtd;
426
427 setup_err:
428 if(mtd) {
429 kfree(mtd->eraseregions);
430 kfree(mtd);
431 }
432 kfree(cfi->cmdset_priv);
433 kfree(cfi->cfiq);
434 return NULL;
435 }
436
437 /*
438 * Return true if the chip is ready.
439 *
440 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
441 * non-suspended sector) and is indicated by no toggle bits toggling.
442 *
443 * Note that anything more complicated than checking if no bits are toggling
444 * (including checking DQ5 for an error status) is tricky to get working
445 * correctly and is therefore not done (particulary with interleaved chips
446 * as each chip must be checked independantly of the others).
447 */
448 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
449 {
450 map_word d, t;
451
452 d = map_read(map, addr);
453 t = map_read(map, addr);
454
455 return map_word_equal(map, d, t);
456 }
457
458 /*
459 * Return true if the chip is ready and has the correct value.
460 *
461 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
462 * non-suspended sector) and it is indicated by no bits toggling.
463 *
464 * Error are indicated by toggling bits or bits held with the wrong value,
465 * or with bits toggling.
466 *
467 * Note that anything more complicated than checking if no bits are toggling
468 * (including checking DQ5 for an error status) is tricky to get working
469 * correctly and is therefore not done (particulary with interleaved chips
470 * as each chip must be checked independantly of the others).
471 *
472 */
473 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
474 {
475 map_word oldd, curd;
476
477 oldd = map_read(map, addr);
478 curd = map_read(map, addr);
479
480 return map_word_equal(map, oldd, curd) &&
481 map_word_equal(map, curd, expected);
482 }
483
484 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
485 {
486 DECLARE_WAITQUEUE(wait, current);
487 struct cfi_private *cfi = map->fldrv_priv;
488 unsigned long timeo;
489 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
490
491 resettime:
492 timeo = jiffies + HZ;
493 retry:
494 switch (chip->state) {
495
496 case FL_STATUS:
497 for (;;) {
498 if (chip_ready(map, adr))
499 break;
500
501 if (time_after(jiffies, timeo)) {
502 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
503 spin_unlock(chip->mutex);
504 return -EIO;
505 }
506 spin_unlock(chip->mutex);
507 cfi_udelay(1);
508 spin_lock(chip->mutex);
509 /* Someone else might have been playing with it. */
510 goto retry;
511 }
512
513 case FL_READY:
514 case FL_CFI_QUERY:
515 case FL_JEDEC_QUERY:
516 return 0;
517
518 case FL_ERASING:
519 if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */
520 goto sleep;
521
522 if (!(mode == FL_READY || mode == FL_POINT
523 || !cfip
524 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))
525 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1))))
526 goto sleep;
527
528 /* We could check to see if we're trying to access the sector
529 * that is currently being erased. However, no user will try
530 * anything like that so we just wait for the timeout. */
531
532 /* Erase suspend */
533 /* It's harmless to issue the Erase-Suspend and Erase-Resume
534 * commands when the erase algorithm isn't in progress. */
535 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
536 chip->oldstate = FL_ERASING;
537 chip->state = FL_ERASE_SUSPENDING;
538 chip->erase_suspended = 1;
539 for (;;) {
540 if (chip_ready(map, adr))
541 break;
542
543 if (time_after(jiffies, timeo)) {
544 /* Should have suspended the erase by now.
545 * Send an Erase-Resume command as either
546 * there was an error (so leave the erase
547 * routine to recover from it) or we trying to
548 * use the erase-in-progress sector. */
549 map_write(map, CMD(0x30), chip->in_progress_block_addr);
550 chip->state = FL_ERASING;
551 chip->oldstate = FL_READY;
552 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
553 return -EIO;
554 }
555
556 spin_unlock(chip->mutex);
557 cfi_udelay(1);
558 spin_lock(chip->mutex);
559 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
560 So we can just loop here. */
561 }
562 chip->state = FL_READY;
563 return 0;
564
565 case FL_XIP_WHILE_ERASING:
566 if (mode != FL_READY && mode != FL_POINT &&
567 (!cfip || !(cfip->EraseSuspend&2)))
568 goto sleep;
569 chip->oldstate = chip->state;
570 chip->state = FL_READY;
571 return 0;
572
573 case FL_POINT:
574 /* Only if there's no operation suspended... */
575 if (mode == FL_READY && chip->oldstate == FL_READY)
576 return 0;
577
578 default:
579 sleep:
580 set_current_state(TASK_UNINTERRUPTIBLE);
581 add_wait_queue(&chip->wq, &wait);
582 spin_unlock(chip->mutex);
583 schedule();
584 remove_wait_queue(&chip->wq, &wait);
585 spin_lock(chip->mutex);
586 goto resettime;
587 }
588 }
589
590
591 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
592 {
593 struct cfi_private *cfi = map->fldrv_priv;
594
595 switch(chip->oldstate) {
596 case FL_ERASING:
597 chip->state = chip->oldstate;
598 map_write(map, CMD(0x30), chip->in_progress_block_addr);
599 chip->oldstate = FL_READY;
600 chip->state = FL_ERASING;
601 break;
602
603 case FL_XIP_WHILE_ERASING:
604 chip->state = chip->oldstate;
605 chip->oldstate = FL_READY;
606 break;
607
608 case FL_READY:
609 case FL_STATUS:
610 /* We should really make set_vpp() count, rather than doing this */
611 DISABLE_VPP(map);
612 break;
613 default:
614 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
615 }
616 wake_up(&chip->wq);
617 }
618
619 #ifdef CONFIG_MTD_XIP
620
621 /*
622 * No interrupt what so ever can be serviced while the flash isn't in array
623 * mode. This is ensured by the xip_disable() and xip_enable() functions
624 * enclosing any code path where the flash is known not to be in array mode.
625 * And within a XIP disabled code path, only functions marked with __xipram
626 * may be called and nothing else (it's a good thing to inspect generated
627 * assembly to make sure inline functions were actually inlined and that gcc
628 * didn't emit calls to its own support functions). Also configuring MTD CFI
629 * support to a single buswidth and a single interleave is also recommended.
630 */
631
632 static void xip_disable(struct map_info *map, struct flchip *chip,
633 unsigned long adr)
634 {
635 /* TODO: chips with no XIP use should ignore and return */
636 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
637 local_irq_disable();
638 }
639
640 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
641 unsigned long adr)
642 {
643 struct cfi_private *cfi = map->fldrv_priv;
644
645 if (chip->state != FL_POINT && chip->state != FL_READY) {
646 map_write(map, CMD(0xf0), adr);
647 chip->state = FL_READY;
648 }
649 (void) map_read(map, adr);
650 xip_iprefetch();
651 local_irq_enable();
652 }
653
654 /*
655 * When a delay is required for the flash operation to complete, the
656 * xip_udelay() function is polling for both the given timeout and pending
657 * (but still masked) hardware interrupts. Whenever there is an interrupt
658 * pending then the flash erase operation is suspended, array mode restored
659 * and interrupts unmasked. Task scheduling might also happen at that
660 * point. The CPU eventually returns from the interrupt or the call to
661 * schedule() and the suspended flash operation is resumed for the remaining
662 * of the delay period.
663 *
664 * Warning: this function _will_ fool interrupt latency tracing tools.
665 */
666
667 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
668 unsigned long adr, int usec)
669 {
670 struct cfi_private *cfi = map->fldrv_priv;
671 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
672 map_word status, OK = CMD(0x80);
673 unsigned long suspended, start = xip_currtime();
674 flstate_t oldstate;
675
676 do {
677 cpu_relax();
678 if (xip_irqpending() && extp &&
679 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
680 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
681 /*
682 * Let's suspend the erase operation when supported.
683 * Note that we currently don't try to suspend
684 * interleaved chips if there is already another
685 * operation suspended (imagine what happens
686 * when one chip was already done with the current
687 * operation while another chip suspended it, then
688 * we resume the whole thing at once). Yes, it
689 * can happen!
690 */
691 map_write(map, CMD(0xb0), adr);
692 usec -= xip_elapsed_since(start);
693 suspended = xip_currtime();
694 do {
695 if (xip_elapsed_since(suspended) > 100000) {
696 /*
697 * The chip doesn't want to suspend
698 * after waiting for 100 msecs.
699 * This is a critical error but there
700 * is not much we can do here.
701 */
702 return;
703 }
704 status = map_read(map, adr);
705 } while (!map_word_andequal(map, status, OK, OK));
706
707 /* Suspend succeeded */
708 oldstate = chip->state;
709 if (!map_word_bitsset(map, status, CMD(0x40)))
710 break;
711 chip->state = FL_XIP_WHILE_ERASING;
712 chip->erase_suspended = 1;
713 map_write(map, CMD(0xf0), adr);
714 (void) map_read(map, adr);
715 asm volatile (".rep 8; nop; .endr");
716 local_irq_enable();
717 spin_unlock(chip->mutex);
718 asm volatile (".rep 8; nop; .endr");
719 cond_resched();
720
721 /*
722 * We're back. However someone else might have
723 * decided to go write to the chip if we are in
724 * a suspended erase state. If so let's wait
725 * until it's done.
726 */
727 spin_lock(chip->mutex);
728 while (chip->state != FL_XIP_WHILE_ERASING) {
729 DECLARE_WAITQUEUE(wait, current);
730 set_current_state(TASK_UNINTERRUPTIBLE);
731 add_wait_queue(&chip->wq, &wait);
732 spin_unlock(chip->mutex);
733 schedule();
734 remove_wait_queue(&chip->wq, &wait);
735 spin_lock(chip->mutex);
736 }
737 /* Disallow XIP again */
738 local_irq_disable();
739
740 /* Resume the write or erase operation */
741 map_write(map, CMD(0x30), adr);
742 chip->state = oldstate;
743 start = xip_currtime();
744 } else if (usec >= 1000000/HZ) {
745 /*
746 * Try to save on CPU power when waiting delay
747 * is at least a system timer tick period.
748 * No need to be extremely accurate here.
749 */
750 xip_cpu_idle();
751 }
752 status = map_read(map, adr);
753 } while (!map_word_andequal(map, status, OK, OK)
754 && xip_elapsed_since(start) < usec);
755 }
756
757 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
758
759 /*
760 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
761 * the flash is actively programming or erasing since we have to poll for
762 * the operation to complete anyway. We can't do that in a generic way with
763 * a XIP setup so do it before the actual flash operation in this case
764 * and stub it out from INVALIDATE_CACHE_UDELAY.
765 */
766 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
767 INVALIDATE_CACHED_RANGE(map, from, size)
768
769 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
770 UDELAY(map, chip, adr, usec)
771
772 /*
773 * Extra notes:
774 *
775 * Activating this XIP support changes the way the code works a bit. For
776 * example the code to suspend the current process when concurrent access
777 * happens is never executed because xip_udelay() will always return with the
778 * same chip state as it was entered with. This is why there is no care for
779 * the presence of add_wait_queue() or schedule() calls from within a couple
780 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
781 * The queueing and scheduling are always happening within xip_udelay().
782 *
783 * Similarly, get_chip() and put_chip() just happen to always be executed
784 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
785 * is in array mode, therefore never executing many cases therein and not
786 * causing any problem with XIP.
787 */
788
789 #else
790
791 #define xip_disable(map, chip, adr)
792 #define xip_enable(map, chip, adr)
793 #define XIP_INVAL_CACHED_RANGE(x...)
794
795 #define UDELAY(map, chip, adr, usec) \
796 do { \
797 spin_unlock(chip->mutex); \
798 cfi_udelay(usec); \
799 spin_lock(chip->mutex); \
800 } while (0)
801
802 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
803 do { \
804 spin_unlock(chip->mutex); \
805 INVALIDATE_CACHED_RANGE(map, adr, len); \
806 cfi_udelay(usec); \
807 spin_lock(chip->mutex); \
808 } while (0)
809
810 #endif
811
812 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
813 {
814 unsigned long cmd_addr;
815 struct cfi_private *cfi = map->fldrv_priv;
816 int ret;
817
818 adr += chip->start;
819
820 /* Ensure cmd read/writes are aligned. */
821 cmd_addr = adr & ~(map_bankwidth(map)-1);
822
823 spin_lock(chip->mutex);
824 ret = get_chip(map, chip, cmd_addr, FL_READY);
825 if (ret) {
826 spin_unlock(chip->mutex);
827 return ret;
828 }
829
830 if (chip->state != FL_POINT && chip->state != FL_READY) {
831 map_write(map, CMD(0xf0), cmd_addr);
832 chip->state = FL_READY;
833 }
834
835 map_copy_from(map, buf, adr, len);
836
837 put_chip(map, chip, cmd_addr);
838
839 spin_unlock(chip->mutex);
840 return 0;
841 }
842
843
844 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
845 {
846 struct map_info *map = mtd->priv;
847 struct cfi_private *cfi = map->fldrv_priv;
848 unsigned long ofs;
849 int chipnum;
850 int ret = 0;
851
852 /* ofs: offset within the first chip that the first read should start */
853
854 chipnum = (from >> cfi->chipshift);
855 ofs = from - (chipnum << cfi->chipshift);
856
857
858 *retlen = 0;
859
860 while (len) {
861 unsigned long thislen;
862
863 if (chipnum >= cfi->numchips)
864 break;
865
866 if ((len + ofs -1) >> cfi->chipshift)
867 thislen = (1<<cfi->chipshift) - ofs;
868 else
869 thislen = len;
870
871 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
872 if (ret)
873 break;
874
875 *retlen += thislen;
876 len -= thislen;
877 buf += thislen;
878
879 ofs = 0;
880 chipnum++;
881 }
882 return ret;
883 }
884
885
886 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
887 {
888 DECLARE_WAITQUEUE(wait, current);
889 unsigned long timeo = jiffies + HZ;
890 struct cfi_private *cfi = map->fldrv_priv;
891
892 retry:
893 spin_lock(chip->mutex);
894
895 if (chip->state != FL_READY){
896 #if 0
897 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
898 #endif
899 set_current_state(TASK_UNINTERRUPTIBLE);
900 add_wait_queue(&chip->wq, &wait);
901
902 spin_unlock(chip->mutex);
903
904 schedule();
905 remove_wait_queue(&chip->wq, &wait);
906 #if 0
907 if(signal_pending(current))
908 return -EINTR;
909 #endif
910 timeo = jiffies + HZ;
911
912 goto retry;
913 }
914
915 adr += chip->start;
916
917 chip->state = FL_READY;
918
919 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
920 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
921 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
922
923 map_copy_from(map, buf, adr, len);
924
925 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
926 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
927 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
928 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
929
930 wake_up(&chip->wq);
931 spin_unlock(chip->mutex);
932
933 return 0;
934 }
935
936 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
937 {
938 struct map_info *map = mtd->priv;
939 struct cfi_private *cfi = map->fldrv_priv;
940 unsigned long ofs;
941 int chipnum;
942 int ret = 0;
943
944
945 /* ofs: offset within the first chip that the first read should start */
946
947 /* 8 secsi bytes per chip */
948 chipnum=from>>3;
949 ofs=from & 7;
950
951
952 *retlen = 0;
953
954 while (len) {
955 unsigned long thislen;
956
957 if (chipnum >= cfi->numchips)
958 break;
959
960 if ((len + ofs -1) >> 3)
961 thislen = (1<<3) - ofs;
962 else
963 thislen = len;
964
965 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
966 if (ret)
967 break;
968
969 *retlen += thislen;
970 len -= thislen;
971 buf += thislen;
972
973 ofs = 0;
974 chipnum++;
975 }
976 return ret;
977 }
978
979
980 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
981 {
982 struct cfi_private *cfi = map->fldrv_priv;
983 unsigned long timeo = jiffies + HZ;
984 /*
985 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
986 * have a max write time of a few hundreds usec). However, we should
987 * use the maximum timeout value given by the chip at probe time
988 * instead. Unfortunately, struct flchip does have a field for
989 * maximum timeout, only for typical which can be far too short
990 * depending of the conditions. The ' + 1' is to avoid having a
991 * timeout of 0 jiffies if HZ is smaller than 1000.
992 */
993 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
994 int ret = 0;
995 map_word oldd;
996 int retry_cnt = 0;
997
998 adr += chip->start;
999
1000 spin_lock(chip->mutex);
1001 ret = get_chip(map, chip, adr, FL_WRITING);
1002 if (ret) {
1003 spin_unlock(chip->mutex);
1004 return ret;
1005 }
1006
1007 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1008 __func__, adr, datum.x[0] );
1009
1010 /*
1011 * Check for a NOP for the case when the datum to write is already
1012 * present - it saves time and works around buggy chips that corrupt
1013 * data at other locations when 0xff is written to a location that
1014 * already contains 0xff.
1015 */
1016 oldd = map_read(map, adr);
1017 if (map_word_equal(map, oldd, datum)) {
1018 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1019 __func__);
1020 goto op_done;
1021 }
1022
1023 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1024 ENABLE_VPP(map);
1025 xip_disable(map, chip, adr);
1026 retry:
1027 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1028 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1029 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1030 map_write(map, datum, adr);
1031 chip->state = FL_WRITING;
1032
1033 INVALIDATE_CACHE_UDELAY(map, chip,
1034 adr, map_bankwidth(map),
1035 chip->word_write_time);
1036
1037 /* See comment above for timeout value. */
1038 timeo = jiffies + uWriteTimeout;
1039 for (;;) {
1040 if (chip->state != FL_WRITING) {
1041 /* Someone's suspended the write. Sleep */
1042 DECLARE_WAITQUEUE(wait, current);
1043
1044 set_current_state(TASK_UNINTERRUPTIBLE);
1045 add_wait_queue(&chip->wq, &wait);
1046 spin_unlock(chip->mutex);
1047 schedule();
1048 remove_wait_queue(&chip->wq, &wait);
1049 timeo = jiffies + (HZ / 2); /* FIXME */
1050 spin_lock(chip->mutex);
1051 continue;
1052 }
1053
1054 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1055 xip_enable(map, chip, adr);
1056 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1057 xip_disable(map, chip, adr);
1058 break;
1059 }
1060
1061 if (chip_ready(map, adr))
1062 break;
1063
1064 /* Latency issues. Drop the lock, wait a while and retry */
1065 UDELAY(map, chip, adr, 1);
1066 }
1067 /* Did we succeed? */
1068 if (!chip_good(map, adr, datum)) {
1069 /* reset on all failures. */
1070 map_write( map, CMD(0xF0), chip->start );
1071 /* FIXME - should have reset delay before continuing */
1072
1073 if (++retry_cnt <= MAX_WORD_RETRIES)
1074 goto retry;
1075
1076 ret = -EIO;
1077 }
1078 xip_enable(map, chip, adr);
1079 op_done:
1080 chip->state = FL_READY;
1081 put_chip(map, chip, adr);
1082 spin_unlock(chip->mutex);
1083
1084 return ret;
1085 }
1086
1087
1088 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1089 size_t *retlen, const u_char *buf)
1090 {
1091 struct map_info *map = mtd->priv;
1092 struct cfi_private *cfi = map->fldrv_priv;
1093 int ret = 0;
1094 int chipnum;
1095 unsigned long ofs, chipstart;
1096 DECLARE_WAITQUEUE(wait, current);
1097
1098 *retlen = 0;
1099 if (!len)
1100 return 0;
1101
1102 chipnum = to >> cfi->chipshift;
1103 ofs = to - (chipnum << cfi->chipshift);
1104 chipstart = cfi->chips[chipnum].start;
1105
1106 /* If it's not bus-aligned, do the first byte write */
1107 if (ofs & (map_bankwidth(map)-1)) {
1108 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1109 int i = ofs - bus_ofs;
1110 int n = 0;
1111 map_word tmp_buf;
1112
1113 retry:
1114 spin_lock(cfi->chips[chipnum].mutex);
1115
1116 if (cfi->chips[chipnum].state != FL_READY) {
1117 #if 0
1118 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1119 #endif
1120 set_current_state(TASK_UNINTERRUPTIBLE);
1121 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1122
1123 spin_unlock(cfi->chips[chipnum].mutex);
1124
1125 schedule();
1126 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1127 #if 0
1128 if(signal_pending(current))
1129 return -EINTR;
1130 #endif
1131 goto retry;
1132 }
1133
1134 /* Load 'tmp_buf' with old contents of flash */
1135 tmp_buf = map_read(map, bus_ofs+chipstart);
1136
1137 spin_unlock(cfi->chips[chipnum].mutex);
1138
1139 /* Number of bytes to copy from buffer */
1140 n = min_t(int, len, map_bankwidth(map)-i);
1141
1142 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1143
1144 ret = do_write_oneword(map, &cfi->chips[chipnum],
1145 bus_ofs, tmp_buf);
1146 if (ret)
1147 return ret;
1148
1149 ofs += n;
1150 buf += n;
1151 (*retlen) += n;
1152 len -= n;
1153
1154 if (ofs >> cfi->chipshift) {
1155 chipnum ++;
1156 ofs = 0;
1157 if (chipnum == cfi->numchips)
1158 return 0;
1159 }
1160 }
1161
1162 /* We are now aligned, write as much as possible */
1163 while(len >= map_bankwidth(map)) {
1164 map_word datum;
1165
1166 datum = map_word_load(map, buf);
1167
1168 ret = do_write_oneword(map, &cfi->chips[chipnum],
1169 ofs, datum);
1170 if (ret)
1171 return ret;
1172
1173 ofs += map_bankwidth(map);
1174 buf += map_bankwidth(map);
1175 (*retlen) += map_bankwidth(map);
1176 len -= map_bankwidth(map);
1177
1178 if (ofs >> cfi->chipshift) {
1179 chipnum ++;
1180 ofs = 0;
1181 if (chipnum == cfi->numchips)
1182 return 0;
1183 chipstart = cfi->chips[chipnum].start;
1184 }
1185 }
1186
1187 /* Write the trailing bytes if any */
1188 if (len & (map_bankwidth(map)-1)) {
1189 map_word tmp_buf;
1190
1191 retry1:
1192 spin_lock(cfi->chips[chipnum].mutex);
1193
1194 if (cfi->chips[chipnum].state != FL_READY) {
1195 #if 0
1196 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1197 #endif
1198 set_current_state(TASK_UNINTERRUPTIBLE);
1199 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1200
1201 spin_unlock(cfi->chips[chipnum].mutex);
1202
1203 schedule();
1204 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1205 #if 0
1206 if(signal_pending(current))
1207 return -EINTR;
1208 #endif
1209 goto retry1;
1210 }
1211
1212 tmp_buf = map_read(map, ofs + chipstart);
1213
1214 spin_unlock(cfi->chips[chipnum].mutex);
1215
1216 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1217
1218 ret = do_write_oneword(map, &cfi->chips[chipnum],
1219 ofs, tmp_buf);
1220 if (ret)
1221 return ret;
1222
1223 (*retlen) += len;
1224 }
1225
1226 return 0;
1227 }
1228
1229
1230 /*
1231 * FIXME: interleaved mode not tested, and probably not supported!
1232 */
1233 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1234 unsigned long adr, const u_char *buf,
1235 int len)
1236 {
1237 struct cfi_private *cfi = map->fldrv_priv;
1238 unsigned long timeo = jiffies + HZ;
1239 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1240 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1241 int ret = -EIO;
1242 unsigned long cmd_adr;
1243 int z, words;
1244 map_word datum;
1245
1246 adr += chip->start;
1247 cmd_adr = adr;
1248
1249 spin_lock(chip->mutex);
1250 ret = get_chip(map, chip, adr, FL_WRITING);
1251 if (ret) {
1252 spin_unlock(chip->mutex);
1253 return ret;
1254 }
1255
1256 datum = map_word_load(map, buf);
1257
1258 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1259 __func__, adr, datum.x[0] );
1260
1261 XIP_INVAL_CACHED_RANGE(map, adr, len);
1262 ENABLE_VPP(map);
1263 xip_disable(map, chip, cmd_adr);
1264
1265 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1266 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1267 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1268
1269 /* Write Buffer Load */
1270 map_write(map, CMD(0x25), cmd_adr);
1271
1272 chip->state = FL_WRITING_TO_BUFFER;
1273
1274 /* Write length of data to come */
1275 words = len / map_bankwidth(map);
1276 map_write(map, CMD(words - 1), cmd_adr);
1277 /* Write data */
1278 z = 0;
1279 while(z < words * map_bankwidth(map)) {
1280 datum = map_word_load(map, buf);
1281 map_write(map, datum, adr + z);
1282
1283 z += map_bankwidth(map);
1284 buf += map_bankwidth(map);
1285 }
1286 z -= map_bankwidth(map);
1287
1288 adr += z;
1289
1290 /* Write Buffer Program Confirm: GO GO GO */
1291 map_write(map, CMD(0x29), cmd_adr);
1292 chip->state = FL_WRITING;
1293
1294 INVALIDATE_CACHE_UDELAY(map, chip,
1295 adr, map_bankwidth(map),
1296 chip->word_write_time);
1297
1298 timeo = jiffies + uWriteTimeout;
1299
1300 for (;;) {
1301 if (chip->state != FL_WRITING) {
1302 /* Someone's suspended the write. Sleep */
1303 DECLARE_WAITQUEUE(wait, current);
1304
1305 set_current_state(TASK_UNINTERRUPTIBLE);
1306 add_wait_queue(&chip->wq, &wait);
1307 spin_unlock(chip->mutex);
1308 schedule();
1309 remove_wait_queue(&chip->wq, &wait);
1310 timeo = jiffies + (HZ / 2); /* FIXME */
1311 spin_lock(chip->mutex);
1312 continue;
1313 }
1314
1315 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1316 break;
1317
1318 if (chip_ready(map, adr)) {
1319 xip_enable(map, chip, adr);
1320 goto op_done;
1321 }
1322
1323 /* Latency issues. Drop the lock, wait a while and retry */
1324 UDELAY(map, chip, adr, 1);
1325 }
1326
1327 /* reset on all failures. */
1328 map_write( map, CMD(0xF0), chip->start );
1329 xip_enable(map, chip, adr);
1330 /* FIXME - should have reset delay before continuing */
1331
1332 printk(KERN_WARNING "MTD %s(): software timeout\n",
1333 __func__ );
1334
1335 ret = -EIO;
1336 op_done:
1337 chip->state = FL_READY;
1338 put_chip(map, chip, adr);
1339 spin_unlock(chip->mutex);
1340
1341 return ret;
1342 }
1343
1344
1345 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1346 size_t *retlen, const u_char *buf)
1347 {
1348 struct map_info *map = mtd->priv;
1349 struct cfi_private *cfi = map->fldrv_priv;
1350 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1351 int ret = 0;
1352 int chipnum;
1353 unsigned long ofs;
1354
1355 *retlen = 0;
1356 if (!len)
1357 return 0;
1358
1359 chipnum = to >> cfi->chipshift;
1360 ofs = to - (chipnum << cfi->chipshift);
1361
1362 /* If it's not bus-aligned, do the first word write */
1363 if (ofs & (map_bankwidth(map)-1)) {
1364 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1365 if (local_len > len)
1366 local_len = len;
1367 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1368 local_len, retlen, buf);
1369 if (ret)
1370 return ret;
1371 ofs += local_len;
1372 buf += local_len;
1373 len -= local_len;
1374
1375 if (ofs >> cfi->chipshift) {
1376 chipnum ++;
1377 ofs = 0;
1378 if (chipnum == cfi->numchips)
1379 return 0;
1380 }
1381 }
1382
1383 /* Write buffer is worth it only if more than one word to write... */
1384 while (len >= map_bankwidth(map) * 2) {
1385 /* We must not cross write block boundaries */
1386 int size = wbufsize - (ofs & (wbufsize-1));
1387
1388 if (size > len)
1389 size = len;
1390 if (size % map_bankwidth(map))
1391 size -= size % map_bankwidth(map);
1392
1393 ret = do_write_buffer(map, &cfi->chips[chipnum],
1394 ofs, buf, size);
1395 if (ret)
1396 return ret;
1397
1398 ofs += size;
1399 buf += size;
1400 (*retlen) += size;
1401 len -= size;
1402
1403 if (ofs >> cfi->chipshift) {
1404 chipnum ++;
1405 ofs = 0;
1406 if (chipnum == cfi->numchips)
1407 return 0;
1408 }
1409 }
1410
1411 if (len) {
1412 size_t retlen_dregs = 0;
1413
1414 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1415 len, &retlen_dregs, buf);
1416
1417 *retlen += retlen_dregs;
1418 return ret;
1419 }
1420
1421 return 0;
1422 }
1423
1424
1425 /*
1426 * Handle devices with one erase region, that only implement
1427 * the chip erase command.
1428 */
1429 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1430 {
1431 struct cfi_private *cfi = map->fldrv_priv;
1432 unsigned long timeo = jiffies + HZ;
1433 unsigned long int adr;
1434 DECLARE_WAITQUEUE(wait, current);
1435 int ret = 0;
1436
1437 adr = cfi->addr_unlock1;
1438
1439 spin_lock(chip->mutex);
1440 ret = get_chip(map, chip, adr, FL_WRITING);
1441 if (ret) {
1442 spin_unlock(chip->mutex);
1443 return ret;
1444 }
1445
1446 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1447 __func__, chip->start );
1448
1449 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1450 ENABLE_VPP(map);
1451 xip_disable(map, chip, adr);
1452
1453 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1454 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1455 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1456 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1457 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1458 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1459
1460 chip->state = FL_ERASING;
1461 chip->erase_suspended = 0;
1462 chip->in_progress_block_addr = adr;
1463
1464 INVALIDATE_CACHE_UDELAY(map, chip,
1465 adr, map->size,
1466 chip->erase_time*500);
1467
1468 timeo = jiffies + (HZ*20);
1469
1470 for (;;) {
1471 if (chip->state != FL_ERASING) {
1472 /* Someone's suspended the erase. Sleep */
1473 set_current_state(TASK_UNINTERRUPTIBLE);
1474 add_wait_queue(&chip->wq, &wait);
1475 spin_unlock(chip->mutex);
1476 schedule();
1477 remove_wait_queue(&chip->wq, &wait);
1478 spin_lock(chip->mutex);
1479 continue;
1480 }
1481 if (chip->erase_suspended) {
1482 /* This erase was suspended and resumed.
1483 Adjust the timeout */
1484 timeo = jiffies + (HZ*20); /* FIXME */
1485 chip->erase_suspended = 0;
1486 }
1487
1488 if (chip_ready(map, adr))
1489 break;
1490
1491 if (time_after(jiffies, timeo)) {
1492 printk(KERN_WARNING "MTD %s(): software timeout\n",
1493 __func__ );
1494 break;
1495 }
1496
1497 /* Latency issues. Drop the lock, wait a while and retry */
1498 UDELAY(map, chip, adr, 1000000/HZ);
1499 }
1500 /* Did we succeed? */
1501 if (!chip_good(map, adr, map_word_ff(map))) {
1502 /* reset on all failures. */
1503 map_write( map, CMD(0xF0), chip->start );
1504 /* FIXME - should have reset delay before continuing */
1505
1506 ret = -EIO;
1507 }
1508
1509 chip->state = FL_READY;
1510 xip_enable(map, chip, adr);
1511 put_chip(map, chip, adr);
1512 spin_unlock(chip->mutex);
1513
1514 return ret;
1515 }
1516
1517
1518 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1519 {
1520 struct cfi_private *cfi = map->fldrv_priv;
1521 unsigned long timeo = jiffies + HZ;
1522 DECLARE_WAITQUEUE(wait, current);
1523 int ret = 0;
1524
1525 adr += chip->start;
1526
1527 spin_lock(chip->mutex);
1528 ret = get_chip(map, chip, adr, FL_ERASING);
1529 if (ret) {
1530 spin_unlock(chip->mutex);
1531 return ret;
1532 }
1533
1534 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1535 __func__, adr );
1536
1537 XIP_INVAL_CACHED_RANGE(map, adr, len);
1538 ENABLE_VPP(map);
1539 xip_disable(map, chip, adr);
1540
1541 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1542 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1543 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1544 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1545 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1546 map_write(map, CMD(0x30), adr);
1547
1548 chip->state = FL_ERASING;
1549 chip->erase_suspended = 0;
1550 chip->in_progress_block_addr = adr;
1551
1552 INVALIDATE_CACHE_UDELAY(map, chip,
1553 adr, len,
1554 chip->erase_time*500);
1555
1556 timeo = jiffies + (HZ*20);
1557
1558 for (;;) {
1559 if (chip->state != FL_ERASING) {
1560 /* Someone's suspended the erase. Sleep */
1561 set_current_state(TASK_UNINTERRUPTIBLE);
1562 add_wait_queue(&chip->wq, &wait);
1563 spin_unlock(chip->mutex);
1564 schedule();
1565 remove_wait_queue(&chip->wq, &wait);
1566 spin_lock(chip->mutex);
1567 continue;
1568 }
1569 if (chip->erase_suspended) {
1570 /* This erase was suspended and resumed.
1571 Adjust the timeout */
1572 timeo = jiffies + (HZ*20); /* FIXME */
1573 chip->erase_suspended = 0;
1574 }
1575
1576 if (chip_ready(map, adr)) {
1577 xip_enable(map, chip, adr);
1578 break;
1579 }
1580
1581 if (time_after(jiffies, timeo)) {
1582 xip_enable(map, chip, adr);
1583 printk(KERN_WARNING "MTD %s(): software timeout\n",
1584 __func__ );
1585 break;
1586 }
1587
1588 /* Latency issues. Drop the lock, wait a while and retry */
1589 UDELAY(map, chip, adr, 1000000/HZ);
1590 }
1591 /* Did we succeed? */
1592 if (!chip_good(map, adr, map_word_ff(map))) {
1593 /* reset on all failures. */
1594 map_write( map, CMD(0xF0), chip->start );
1595 /* FIXME - should have reset delay before continuing */
1596
1597 ret = -EIO;
1598 }
1599
1600 chip->state = FL_READY;
1601 put_chip(map, chip, adr);
1602 spin_unlock(chip->mutex);
1603 return ret;
1604 }
1605
1606
1607 int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1608 {
1609 unsigned long ofs, len;
1610 int ret;
1611
1612 ofs = instr->addr;
1613 len = instr->len;
1614
1615 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1616 if (ret)
1617 return ret;
1618
1619 instr->state = MTD_ERASE_DONE;
1620 mtd_erase_callback(instr);
1621
1622 return 0;
1623 }
1624
1625
1626 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1627 {
1628 struct map_info *map = mtd->priv;
1629 struct cfi_private *cfi = map->fldrv_priv;
1630 int ret = 0;
1631
1632 if (instr->addr != 0)
1633 return -EINVAL;
1634
1635 if (instr->len != mtd->size)
1636 return -EINVAL;
1637
1638 ret = do_erase_chip(map, &cfi->chips[0]);
1639 if (ret)
1640 return ret;
1641
1642 instr->state = MTD_ERASE_DONE;
1643 mtd_erase_callback(instr);
1644
1645 return 0;
1646 }
1647
1648 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1649 unsigned long adr, int len, void *thunk)
1650 {
1651 struct cfi_private *cfi = map->fldrv_priv;
1652 int ret;
1653
1654 spin_lock(chip->mutex);
1655 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1656 if (ret)
1657 goto out_unlock;
1658 chip->state = FL_LOCKING;
1659
1660 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1661 __func__, adr, len);
1662
1663 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1664 cfi->device_type, NULL);
1665 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1666 cfi->device_type, NULL);
1667 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1668 cfi->device_type, NULL);
1669 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1670 cfi->device_type, NULL);
1671 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1672 cfi->device_type, NULL);
1673 map_write(map, CMD(0x40), chip->start + adr);
1674
1675 chip->state = FL_READY;
1676 put_chip(map, chip, adr + chip->start);
1677 ret = 0;
1678
1679 out_unlock:
1680 spin_unlock(chip->mutex);
1681 return ret;
1682 }
1683
1684 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1685 unsigned long adr, int len, void *thunk)
1686 {
1687 struct cfi_private *cfi = map->fldrv_priv;
1688 int ret;
1689
1690 spin_lock(chip->mutex);
1691 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1692 if (ret)
1693 goto out_unlock;
1694 chip->state = FL_UNLOCKING;
1695
1696 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1697 __func__, adr, len);
1698
1699 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1700 cfi->device_type, NULL);
1701 map_write(map, CMD(0x70), adr);
1702
1703 chip->state = FL_READY;
1704 put_chip(map, chip, adr + chip->start);
1705 ret = 0;
1706
1707 out_unlock:
1708 spin_unlock(chip->mutex);
1709 return ret;
1710 }
1711
1712 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
1713 {
1714 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1715 }
1716
1717 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
1718 {
1719 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1720 }
1721
1722
1723 static void cfi_amdstd_sync (struct mtd_info *mtd)
1724 {
1725 struct map_info *map = mtd->priv;
1726 struct cfi_private *cfi = map->fldrv_priv;
1727 int i;
1728 struct flchip *chip;
1729 int ret = 0;
1730 DECLARE_WAITQUEUE(wait, current);
1731
1732 for (i=0; !ret && i<cfi->numchips; i++) {
1733 chip = &cfi->chips[i];
1734
1735 retry:
1736 spin_lock(chip->mutex);
1737
1738 switch(chip->state) {
1739 case FL_READY:
1740 case FL_STATUS:
1741 case FL_CFI_QUERY:
1742 case FL_JEDEC_QUERY:
1743 chip->oldstate = chip->state;
1744 chip->state = FL_SYNCING;
1745 /* No need to wake_up() on this state change -
1746 * as the whole point is that nobody can do anything
1747 * with the chip now anyway.
1748 */
1749 case FL_SYNCING:
1750 spin_unlock(chip->mutex);
1751 break;
1752
1753 default:
1754 /* Not an idle state */
1755 add_wait_queue(&chip->wq, &wait);
1756
1757 spin_unlock(chip->mutex);
1758
1759 schedule();
1760
1761 remove_wait_queue(&chip->wq, &wait);
1762
1763 goto retry;
1764 }
1765 }
1766
1767 /* Unlock the chips again */
1768
1769 for (i--; i >=0; i--) {
1770 chip = &cfi->chips[i];
1771
1772 spin_lock(chip->mutex);
1773
1774 if (chip->state == FL_SYNCING) {
1775 chip->state = chip->oldstate;
1776 wake_up(&chip->wq);
1777 }
1778 spin_unlock(chip->mutex);
1779 }
1780 }
1781
1782
1783 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1784 {
1785 struct map_info *map = mtd->priv;
1786 struct cfi_private *cfi = map->fldrv_priv;
1787 int i;
1788 struct flchip *chip;
1789 int ret = 0;
1790
1791 for (i=0; !ret && i<cfi->numchips; i++) {
1792 chip = &cfi->chips[i];
1793
1794 spin_lock(chip->mutex);
1795
1796 switch(chip->state) {
1797 case FL_READY:
1798 case FL_STATUS:
1799 case FL_CFI_QUERY:
1800 case FL_JEDEC_QUERY:
1801 chip->oldstate = chip->state;
1802 chip->state = FL_PM_SUSPENDED;
1803 /* No need to wake_up() on this state change -
1804 * as the whole point is that nobody can do anything
1805 * with the chip now anyway.
1806 */
1807 case FL_PM_SUSPENDED:
1808 break;
1809
1810 default:
1811 ret = -EAGAIN;
1812 break;
1813 }
1814 spin_unlock(chip->mutex);
1815 }
1816
1817 /* Unlock the chips again */
1818
1819 if (ret) {
1820 for (i--; i >=0; i--) {
1821 chip = &cfi->chips[i];
1822
1823 spin_lock(chip->mutex);
1824
1825 if (chip->state == FL_PM_SUSPENDED) {
1826 chip->state = chip->oldstate;
1827 wake_up(&chip->wq);
1828 }
1829 spin_unlock(chip->mutex);
1830 }
1831 }
1832
1833 return ret;
1834 }
1835
1836
1837 static void cfi_amdstd_resume(struct mtd_info *mtd)
1838 {
1839 struct map_info *map = mtd->priv;
1840 struct cfi_private *cfi = map->fldrv_priv;
1841 int i;
1842 struct flchip *chip;
1843
1844 for (i=0; i<cfi->numchips; i++) {
1845
1846 chip = &cfi->chips[i];
1847
1848 spin_lock(chip->mutex);
1849
1850 if (chip->state == FL_PM_SUSPENDED) {
1851 chip->state = FL_READY;
1852 map_write(map, CMD(0xF0), chip->start);
1853 wake_up(&chip->wq);
1854 }
1855 else
1856 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1857
1858 spin_unlock(chip->mutex);
1859 }
1860 }
1861
1862 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1863 {
1864 struct map_info *map = mtd->priv;
1865 struct cfi_private *cfi = map->fldrv_priv;
1866
1867 kfree(cfi->cmdset_priv);
1868 kfree(cfi->cfiq);
1869 kfree(cfi);
1870 kfree(mtd->eraseregions);
1871 }
1872
1873 MODULE_LICENSE("GPL");
1874 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1875 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
linux kernel for loongson