?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: OMAP: Implement workaround for GPIO wakeup bug in OMAP2420 silicon
[linux-2.6/linux-loongson.git] / drivers / net / sky2.c
blobac36152c68bf1261206e86f5373ff5eac21b09a7
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
42
43 #include <asm/irq.h>
44
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
47 #endif
48
49 #include "sky2.h"
50
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.14"
53 #define PFX DRV_NAME " "
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
101
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 #ifdef broken
127 /* This device causes data corruption problems that are not resolved */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 #endif
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { 0 }
137 };
138
139 MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
145
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
153 };
154
155 /* Access to external PHY */
156 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 {
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
165 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
166 return 0;
167 udelay(1);
168 }
169
170 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
171 return -ETIMEDOUT;
172 }
173
174 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
175 {
176 int i;
177
178 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
179 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
180
181 for (i = 0; i < PHY_RETRIES; i++) {
182 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
183 *val = gma_read16(hw, port, GM_SMI_DATA);
184 return 0;
185 }
186
187 udelay(1);
188 }
189
190 return -ETIMEDOUT;
191 }
192
193 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
194 {
195 u16 v;
196
197 if (__gm_phy_read(hw, port, reg, &v) != 0)
198 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
199 return v;
200 }
201
202
203 static void sky2_power_on(struct sky2_hw *hw)
204 {
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208
209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220
221 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
222 u32 reg1;
223
224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
226 reg1 &= P_ASPM_CONTROL_MSK;
227 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
228 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
229 }
230 }
231
232 static void sky2_power_aux(struct sky2_hw *hw)
233 {
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 else
237 /* enable bits are inverted */
238 sky2_write8(hw, B2_Y2_CLK_GATE,
239 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
240 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
241 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
242
243 /* switch power to VAUX */
244 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
245 sky2_write8(hw, B0_POWER_CTRL,
246 (PC_VAUX_ENA | PC_VCC_ENA |
247 PC_VAUX_ON | PC_VCC_OFF));
248 }
249
250 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
251 {
252 u16 reg;
253
254 /* disable all GMAC IRQ's */
255 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
256 /* disable PHY IRQs */
257 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
258
259 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
260 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
261 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
263
264 reg = gma_read16(hw, port, GM_RX_CTRL);
265 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
266 gma_write16(hw, port, GM_RX_CTRL, reg);
267 }
268
269 /* flow control to advertise bits */
270 static const u16 copper_fc_adv[] = {
271 [FC_NONE] = 0,
272 [FC_TX] = PHY_M_AN_ASP,
273 [FC_RX] = PHY_M_AN_PC,
274 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
275 };
276
277 /* flow control to advertise bits when using 1000BaseX */
278 static const u16 fiber_fc_adv[] = {
279 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
280 [FC_TX] = PHY_M_P_ASYM_MD_X,
281 [FC_RX] = PHY_M_P_SYM_MD_X,
282 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
283 };
284
285 /* flow control to GMA disable bits */
286 static const u16 gm_fc_disable[] = {
287 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
288 [FC_TX] = GM_GPCR_FC_RX_DIS,
289 [FC_RX] = GM_GPCR_FC_TX_DIS,
290 [FC_BOTH] = 0,
291 };
292
293
294 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295 {
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
298
299 if (sky2->autoneg == AUTONEG_ENABLE
300 && !(hw->chip_id == CHIP_ID_YUKON_XL
301 || hw->chip_id == CHIP_ID_YUKON_EC_U
302 || hw->chip_id == CHIP_ID_YUKON_EX)) {
303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
304
305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
306 PHY_M_EC_MAC_S_MSK);
307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
308
309 if (hw->chip_id == CHIP_ID_YUKON_EC)
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
312 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
313
314 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
315 }
316
317 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
318 if (sky2_is_copper(hw)) {
319 if (hw->chip_id == CHIP_ID_YUKON_FE) {
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
322 } else {
323 /* disable energy detect */
324 ctrl &= ~PHY_M_PC_EN_DET_MSK;
325
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
328
329 if (sky2->autoneg == AUTONEG_ENABLE
330 && (hw->chip_id == CHIP_ID_YUKON_XL
331 || hw->chip_id == CHIP_ID_YUKON_EC_U
332 || hw->chip_id == CHIP_ID_YUKON_EX)) {
333 ctrl &= ~PHY_M_PC_DSC_MSK;
334 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 }
336 }
337 } else {
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
340
341 ctrl &= ~PHY_M_PC_MDIX_MSK;
342 }
343
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* special setup for PHY 88E1112 Fiber */
347 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
348 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
349
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
357 if (hw->pmd_type == 'P') {
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
360
361 /* for SFP-module set SIGDET polarity to low */
362 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
363 ctrl |= PHY_M_FIB_SIGD_POL;
364 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
365 }
366
367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
368 }
369
370 ctrl = PHY_CT_RESET;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373 reg = 0;
374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2_is_copper(hw)) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
389
390 adv |= copper_fc_adv[sky2->flow_mode];
391 } else { /* special defines for FIBER (88E1040S only) */
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 adv |= PHY_M_AN_1000X_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 adv |= PHY_M_AN_1000X_AHD;
396
397 adv |= fiber_fc_adv[sky2->flow_mode];
398 }
399
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 } else {
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
405
406 /* Disable auto update for duplex flow control and speed */
407 reg |= GM_GPCR_AU_ALL_DIS;
408
409 switch (sky2->speed) {
410 case SPEED_1000:
411 ctrl |= PHY_CT_SP1000;
412 reg |= GM_GPCR_SPEED_1000;
413 break;
414 case SPEED_100:
415 ctrl |= PHY_CT_SP100;
416 reg |= GM_GPCR_SPEED_100;
417 break;
418 }
419
420 if (sky2->duplex == DUPLEX_FULL) {
421 reg |= GM_GPCR_DUP_FULL;
422 ctrl |= PHY_CT_DUP_MD;
423 } else if (sky2->speed < SPEED_1000)
424 sky2->flow_mode = FC_NONE;
425
426
427 reg |= gm_fc_disable[sky2->flow_mode];
428
429 /* Forward pause packets to GMAC? */
430 if (sky2->flow_mode & FC_RX)
431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
432 else
433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
434 }
435
436 gma_write16(hw, port, GM_GP_CTRL, reg);
437
438 if (hw->chip_id != CHIP_ID_YUKON_FE)
439 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
440
441 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
442 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
443
444 /* Setup Phy LED's */
445 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
446 ledover = 0;
447
448 switch (hw->chip_id) {
449 case CHIP_ID_YUKON_FE:
450 /* on 88E3082 these bits are at 11..9 (shifted left) */
451 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
452
453 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
454
455 /* delete ACT LED control bits */
456 ctrl &= ~PHY_M_FELP_LED1_MSK;
457 /* change ACT LED control to blink mode */
458 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
459 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
460 break;
461
462 case CHIP_ID_YUKON_XL:
463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
464
465 /* select page 3 to access LED control register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
467
468 /* set LED Function Control register */
469 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
470 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
471 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
472 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
473 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
474
475 /* set Polarity Control register */
476 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
477 (PHY_M_POLC_LS1_P_MIX(4) |
478 PHY_M_POLC_IS0_P_MIX(4) |
479 PHY_M_POLC_LOS_CTRL(2) |
480 PHY_M_POLC_INIT_CTRL(2) |
481 PHY_M_POLC_STA1_CTRL(2) |
482 PHY_M_POLC_STA0_CTRL(2)));
483
484 /* restore page register */
485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
486 break;
487
488 case CHIP_ID_YUKON_EC_U:
489 case CHIP_ID_YUKON_EX:
490 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
491
492 /* select page 3 to access LED control register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
494
495 /* set LED Function Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
497 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
498 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
499 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
500 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
501
502 /* set Blink Rate in LED Timer Control Register */
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
504 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
505 /* restore page register */
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
507 break;
508
509 default:
510 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
512 /* turn off the Rx LED (LED_RX) */
513 ledover &= ~PHY_M_LED_MO_RX;
514 }
515
516 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
517 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
518 /* apply fixes in PHY AFE */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
520
521 /* increase differential signal amplitude in 10BASE-T */
522 gm_phy_write(hw, port, 0x18, 0xaa99);
523 gm_phy_write(hw, port, 0x17, 0x2011);
524
525 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
526 gm_phy_write(hw, port, 0x18, 0xa204);
527 gm_phy_write(hw, port, 0x17, 0x2002);
528
529 /* set page register to 0 */
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
531 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
532 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
533
534 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
535 /* turn on 100 Mbps LED (LED_LINK100) */
536 ledover |= PHY_M_LED_MO_100;
537 }
538
539 if (ledover)
540 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
541
542 }
543
544 /* Enable phy interrupt on auto-negotiation complete (or link up) */
545 if (sky2->autoneg == AUTONEG_ENABLE)
546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
547 else
548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
549 }
550
551 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
552 {
553 u32 reg1;
554 static const u32 phy_power[]
555 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
556
557 /* looks like this XL is back asswards .. */
558 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
559 onoff = !onoff;
560
561 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
562 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
563 if (onoff)
564 /* Turn off phy power saving */
565 reg1 &= ~phy_power[port];
566 else
567 reg1 |= phy_power[port];
568
569 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
570 sky2_pci_read32(hw, PCI_DEV_REG1);
571 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
572 udelay(100);
573 }
574
575 /* Force a renegotiation */
576 static void sky2_phy_reinit(struct sky2_port *sky2)
577 {
578 spin_lock_bh(&sky2->phy_lock);
579 sky2_phy_init(sky2->hw, sky2->port);
580 spin_unlock_bh(&sky2->phy_lock);
581 }
582
583 /* Put device in state to listen for Wake On Lan */
584 static void sky2_wol_init(struct sky2_port *sky2)
585 {
586 struct sky2_hw *hw = sky2->hw;
587 unsigned port = sky2->port;
588 enum flow_control save_mode;
589 u16 ctrl;
590 u32 reg1;
591
592 /* Bring hardware out of reset */
593 sky2_write16(hw, B0_CTST, CS_RST_CLR);
594 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
595
596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
598
599 /* Force to 10/100
600 * sky2_reset will re-enable on resume
601 */
602 save_mode = sky2->flow_mode;
603 ctrl = sky2->advertising;
604
605 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
606 sky2->flow_mode = FC_NONE;
607 sky2_phy_power(hw, port, 1);
608 sky2_phy_reinit(sky2);
609
610 sky2->flow_mode = save_mode;
611 sky2->advertising = ctrl;
612
613 /* Set GMAC to no flow control and auto update for speed/duplex */
614 gma_write16(hw, port, GM_GP_CTRL,
615 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
616 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
617
618 /* Set WOL address */
619 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
620 sky2->netdev->dev_addr, ETH_ALEN);
621
622 /* Turn on appropriate WOL control bits */
623 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
624 ctrl = 0;
625 if (sky2->wol & WAKE_PHY)
626 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
627 else
628 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
629
630 if (sky2->wol & WAKE_MAGIC)
631 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
632 else
633 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
634
635 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
636 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
637
638 /* Turn on legacy PCI-Express PME mode */
639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
640 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
641 reg1 |= PCI_Y2_PME_LEGACY;
642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
644
645 /* block receiver */
646 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
647
648 }
649
650 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
651 {
652 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
653 u16 reg;
654 int i;
655 const u8 *addr = hw->dev[port]->dev_addr;
656
657 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
659
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
661
662 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
663 /* WA DEV_472 -- looks like crossed wires on port 2 */
664 /* clear GMAC 1 Control reset */
665 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
666 do {
667 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
669 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
670 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
671 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
672 }
673
674 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
675
676 /* Enable Transmit FIFO Underrun */
677 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
678
679 spin_lock_bh(&sky2->phy_lock);
680 sky2_phy_init(hw, port);
681 spin_unlock_bh(&sky2->phy_lock);
682
683 /* MIB clear */
684 reg = gma_read16(hw, port, GM_PHY_ADDR);
685 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
686
687 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
688 gma_read16(hw, port, i);
689 gma_write16(hw, port, GM_PHY_ADDR, reg);
690
691 /* transmit control */
692 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
693
694 /* receive control reg: unicast + multicast + no FCS */
695 gma_write16(hw, port, GM_RX_CTRL,
696 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
697
698 /* transmit flow control */
699 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
700
701 /* transmit parameter */
702 gma_write16(hw, port, GM_TX_PARAM,
703 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
704 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
705 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
706 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
707
708 /* serial mode register */
709 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
710 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
711
712 if (hw->dev[port]->mtu > ETH_DATA_LEN)
713 reg |= GM_SMOD_JUMBO_ENA;
714
715 gma_write16(hw, port, GM_SERIAL_MODE, reg);
716
717 /* virtual address for data */
718 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
719
720 /* physical address: used for pause frames */
721 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
722
723 /* ignore counter overflows */
724 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
725 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
727
728 /* Configure Rx MAC FIFO */
729 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
730 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
731 GMF_OPER_ON | GMF_RX_F_FL_ON);
732
733 /* Flush Rx MAC FIFO on any flow control or error */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
735
736 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
738
739 /* Configure Tx MAC FIFO */
740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
741 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
742
743 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
744 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
745 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
746
747 /* set Tx GMAC FIFO Almost Empty Threshold */
748 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
749 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
750
751 if (hw->dev[port]->mtu > ETH_DATA_LEN)
752 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
753 TX_JUMBO_ENA | TX_STFW_DIS);
754 else
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_DIS | TX_STFW_ENA);
757 }
758
759 }
760
761 /* Assign Ram Buffer allocation to queue */
762 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
763 {
764 u32 end;
765
766 /* convert from K bytes to qwords used for hw register */
767 start *= 1024/8;
768 space *= 1024/8;
769 end = start + space - 1;
770
771 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
772 sky2_write32(hw, RB_ADDR(q, RB_START), start);
773 sky2_write32(hw, RB_ADDR(q, RB_END), end);
774 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
775 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
776
777 if (q == Q_R1 || q == Q_R2) {
778 u32 tp = space - space/4;
779
780 /* On receive queue's set the thresholds
781 * give receiver priority when > 3/4 full
782 * send pause when down to 2K
783 */
784 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
785 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
786
787 tp = space - 2048/8;
788 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
789 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
790 } else {
791 /* Enable store & forward on Tx queue's because
792 * Tx FIFO is only 1K on Yukon
793 */
794 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
795 }
796
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
798 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
799 }
800
801 /* Setup Bus Memory Interface */
802 static void sky2_qset(struct sky2_hw *hw, u16 q)
803 {
804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
807 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
808 }
809
810 /* Setup prefetch unit registers. This is the interface between
811 * hardware and driver list elements
812 */
813 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
814 u64 addr, u32 last)
815 {
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
820 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
822
823 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
824 }
825
826 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
827 {
828 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
829
830 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
831 le->ctrl = 0;
832 return le;
833 }
834
835 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
836 struct sky2_tx_le *le)
837 {
838 return sky2->tx_ring + (le - sky2->tx_le);
839 }
840
841 /* Update chip's next pointer */
842 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
843 {
844 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
845 wmb();
846 sky2_write16(hw, q, idx);
847 sky2_read16(hw, q);
848 }
849
850
851 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
852 {
853 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
854 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
855 le->ctrl = 0;
856 return le;
857 }
858
859 /* Return high part of DMA address (could be 32 or 64 bit) */
860 static inline u32 high32(dma_addr_t a)
861 {
862 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
863 }
864
865 /* Build description to hardware for one receive segment */
866 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
867 dma_addr_t map, unsigned len)
868 {
869 struct sky2_rx_le *le;
870 u32 hi = high32(map);
871
872 if (sky2->rx_addr64 != hi) {
873 le = sky2_next_rx(sky2);
874 le->addr = cpu_to_le32(hi);
875 le->opcode = OP_ADDR64 | HW_OWNER;
876 sky2->rx_addr64 = high32(map + len);
877 }
878
879 le = sky2_next_rx(sky2);
880 le->addr = cpu_to_le32((u32) map);
881 le->length = cpu_to_le16(len);
882 le->opcode = op | HW_OWNER;
883 }
884
885 /* Build description to hardware for one possibly fragmented skb */
886 static void sky2_rx_submit(struct sky2_port *sky2,
887 const struct rx_ring_info *re)
888 {
889 int i;
890
891 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
892
893 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
894 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
895 }
896
897
898 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
899 unsigned size)
900 {
901 struct sk_buff *skb = re->skb;
902 int i;
903
904 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
905 pci_unmap_len_set(re, data_size, size);
906
907 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
908 re->frag_addr[i] = pci_map_page(pdev,
909 skb_shinfo(skb)->frags[i].page,
910 skb_shinfo(skb)->frags[i].page_offset,
911 skb_shinfo(skb)->frags[i].size,
912 PCI_DMA_FROMDEVICE);
913 }
914
915 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
916 {
917 struct sk_buff *skb = re->skb;
918 int i;
919
920 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
921 PCI_DMA_FROMDEVICE);
922
923 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
924 pci_unmap_page(pdev, re->frag_addr[i],
925 skb_shinfo(skb)->frags[i].size,
926 PCI_DMA_FROMDEVICE);
927 }
928
929 /* Tell chip where to start receive checksum.
930 * Actually has two checksums, but set both same to avoid possible byte
931 * order problems.
932 */
933 static void rx_set_checksum(struct sky2_port *sky2)
934 {
935 struct sky2_rx_le *le;
936
937 le = sky2_next_rx(sky2);
938 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
939 le->ctrl = 0;
940 le->opcode = OP_TCPSTART | HW_OWNER;
941
942 sky2_write32(sky2->hw,
943 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
944 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
945
946 }
947
948 /*
949 * The RX Stop command will not work for Yukon-2 if the BMU does not
950 * reach the end of packet and since we can't make sure that we have
951 * incoming data, we must reset the BMU while it is not doing a DMA
952 * transfer. Since it is possible that the RX path is still active,
953 * the RX RAM buffer will be stopped first, so any possible incoming
954 * data will not trigger a DMA. After the RAM buffer is stopped, the
955 * BMU is polled until any DMA in progress is ended and only then it
956 * will be reset.
957 */
958 static void sky2_rx_stop(struct sky2_port *sky2)
959 {
960 struct sky2_hw *hw = sky2->hw;
961 unsigned rxq = rxqaddr[sky2->port];
962 int i;
963
964 /* disable the RAM Buffer receive queue */
965 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
966
967 for (i = 0; i < 0xffff; i++)
968 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
969 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
970 goto stopped;
971
972 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
973 sky2->netdev->name);
974 stopped:
975 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
976
977 /* reset the Rx prefetch unit */
978 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
979 }
980
981 /* Clean out receive buffer area, assumes receiver hardware stopped */
982 static void sky2_rx_clean(struct sky2_port *sky2)
983 {
984 unsigned i;
985
986 memset(sky2->rx_le, 0, RX_LE_BYTES);
987 for (i = 0; i < sky2->rx_pending; i++) {
988 struct rx_ring_info *re = sky2->rx_ring + i;
989
990 if (re->skb) {
991 sky2_rx_unmap_skb(sky2->hw->pdev, re);
992 kfree_skb(re->skb);
993 re->skb = NULL;
994 }
995 }
996 }
997
998 /* Basic MII support */
999 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1000 {
1001 struct mii_ioctl_data *data = if_mii(ifr);
1002 struct sky2_port *sky2 = netdev_priv(dev);
1003 struct sky2_hw *hw = sky2->hw;
1004 int err = -EOPNOTSUPP;
1005
1006 if (!netif_running(dev))
1007 return -ENODEV; /* Phy still in reset */
1008
1009 switch (cmd) {
1010 case SIOCGMIIPHY:
1011 data->phy_id = PHY_ADDR_MARV;
1012
1013 /* fallthru */
1014 case SIOCGMIIREG: {
1015 u16 val = 0;
1016
1017 spin_lock_bh(&sky2->phy_lock);
1018 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1019 spin_unlock_bh(&sky2->phy_lock);
1020
1021 data->val_out = val;
1022 break;
1023 }
1024
1025 case SIOCSMIIREG:
1026 if (!capable(CAP_NET_ADMIN))
1027 return -EPERM;
1028
1029 spin_lock_bh(&sky2->phy_lock);
1030 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1031 data->val_in);
1032 spin_unlock_bh(&sky2->phy_lock);
1033 break;
1034 }
1035 return err;
1036 }
1037
1038 #ifdef SKY2_VLAN_TAG_USED
1039 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1040 {
1041 struct sky2_port *sky2 = netdev_priv(dev);
1042 struct sky2_hw *hw = sky2->hw;
1043 u16 port = sky2->port;
1044
1045 netif_tx_lock_bh(dev);
1046
1047 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1048 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1049 sky2->vlgrp = grp;
1050
1051 netif_tx_unlock_bh(dev);
1052 }
1053
1054 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1055 {
1056 struct sky2_port *sky2 = netdev_priv(dev);
1057 struct sky2_hw *hw = sky2->hw;
1058 u16 port = sky2->port;
1059
1060 netif_tx_lock_bh(dev);
1061
1062 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1063 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1064 vlan_group_set_device(sky2->vlgrp, vid, NULL);
1065
1066 netif_tx_unlock_bh(dev);
1067 }
1068 #endif
1069
1070 /*
1071 * Allocate an skb for receiving. If the MTU is large enough
1072 * make the skb non-linear with a fragment list of pages.
1073 *
1074 * It appears the hardware has a bug in the FIFO logic that
1075 * cause it to hang if the FIFO gets overrun and the receive buffer
1076 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1077 * aligned except if slab debugging is enabled.
1078 */
1079 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1080 {
1081 struct sk_buff *skb;
1082 unsigned long p;
1083 int i;
1084
1085 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1086 if (!skb)
1087 goto nomem;
1088
1089 p = (unsigned long) skb->data;
1090 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1091
1092 for (i = 0; i < sky2->rx_nfrags; i++) {
1093 struct page *page = alloc_page(GFP_ATOMIC);
1094
1095 if (!page)
1096 goto free_partial;
1097 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1098 }
1099
1100 return skb;
1101 free_partial:
1102 kfree_skb(skb);
1103 nomem:
1104 return NULL;
1105 }
1106
1107 /*
1108 * Allocate and setup receiver buffer pool.
1109 * Normal case this ends up creating one list element for skb
1110 * in the receive ring. Worst case if using large MTU and each
1111 * allocation falls on a different 64 bit region, that results
1112 * in 6 list elements per ring entry.
1113 * One element is used for checksum enable/disable, and one
1114 * extra to avoid wrap.
1115 */
1116 static int sky2_rx_start(struct sky2_port *sky2)
1117 {
1118 struct sky2_hw *hw = sky2->hw;
1119 struct rx_ring_info *re;
1120 unsigned rxq = rxqaddr[sky2->port];
1121 unsigned i, size, space, thresh;
1122
1123 sky2->rx_put = sky2->rx_next = 0;
1124 sky2_qset(hw, rxq);
1125
1126 /* On PCI express lowering the watermark gives better performance */
1127 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1128 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1129
1130 /* These chips have no ram buffer?
1131 * MAC Rx RAM Read is controlled by hardware */
1132 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1133 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1134 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1135 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1136
1137 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1138
1139 rx_set_checksum(sky2);
1140
1141 /* Space needed for frame data + headers rounded up */
1142 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1143 + 8;
1144
1145 /* Stopping point for hardware truncation */
1146 thresh = (size - 8) / sizeof(u32);
1147
1148 /* Account for overhead of skb - to avoid order > 0 allocation */
1149 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1150 + sizeof(struct skb_shared_info);
1151
1152 sky2->rx_nfrags = space >> PAGE_SHIFT;
1153 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1154
1155 if (sky2->rx_nfrags != 0) {
1156 /* Compute residue after pages */
1157 space = sky2->rx_nfrags << PAGE_SHIFT;
1158
1159 if (space < size)
1160 size -= space;
1161 else
1162 size = 0;
1163
1164 /* Optimize to handle small packets and headers */
1165 if (size < copybreak)
1166 size = copybreak;
1167 if (size < ETH_HLEN)
1168 size = ETH_HLEN;
1169 }
1170 sky2->rx_data_size = size;
1171
1172 /* Fill Rx ring */
1173 for (i = 0; i < sky2->rx_pending; i++) {
1174 re = sky2->rx_ring + i;
1175
1176 re->skb = sky2_rx_alloc(sky2);
1177 if (!re->skb)
1178 goto nomem;
1179
1180 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1181 sky2_rx_submit(sky2, re);
1182 }
1183
1184 /*
1185 * The receiver hangs if it receives frames larger than the
1186 * packet buffer. As a workaround, truncate oversize frames, but
1187 * the register is limited to 9 bits, so if you do frames > 2052
1188 * you better get the MTU right!
1189 */
1190 if (thresh > 0x1ff)
1191 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1192 else {
1193 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1194 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1195 }
1196
1197 /* Tell chip about available buffers */
1198 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1199 return 0;
1200 nomem:
1201 sky2_rx_clean(sky2);
1202 return -ENOMEM;
1203 }
1204
1205 /* Bring up network interface. */
1206 static int sky2_up(struct net_device *dev)
1207 {
1208 struct sky2_port *sky2 = netdev_priv(dev);
1209 struct sky2_hw *hw = sky2->hw;
1210 unsigned port = sky2->port;
1211 u32 ramsize, imask;
1212 int cap, err = -ENOMEM;
1213 struct net_device *otherdev = hw->dev[sky2->port^1];
1214
1215 /*
1216 * On dual port PCI-X card, there is an problem where status
1217 * can be received out of order due to split transactions
1218 */
1219 if (otherdev && netif_running(otherdev) &&
1220 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1221 struct sky2_port *osky2 = netdev_priv(otherdev);
1222 u16 cmd;
1223
1224 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1225 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1226 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1227
1228 sky2->rx_csum = 0;
1229 osky2->rx_csum = 0;
1230 }
1231
1232 if (netif_msg_ifup(sky2))
1233 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1234
1235 /* must be power of 2 */
1236 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1237 TX_RING_SIZE *
1238 sizeof(struct sky2_tx_le),
1239 &sky2->tx_le_map);
1240 if (!sky2->tx_le)
1241 goto err_out;
1242
1243 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1244 GFP_KERNEL);
1245 if (!sky2->tx_ring)
1246 goto err_out;
1247 sky2->tx_prod = sky2->tx_cons = 0;
1248
1249 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1250 &sky2->rx_le_map);
1251 if (!sky2->rx_le)
1252 goto err_out;
1253 memset(sky2->rx_le, 0, RX_LE_BYTES);
1254
1255 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1256 GFP_KERNEL);
1257 if (!sky2->rx_ring)
1258 goto err_out;
1259
1260 sky2_phy_power(hw, port, 1);
1261
1262 sky2_mac_init(hw, port);
1263
1264 /* Register is number of 4K blocks on internal RAM buffer. */
1265 ramsize = sky2_read8(hw, B2_E_0) * 4;
1266 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1267
1268 if (ramsize > 0) {
1269 u32 rxspace;
1270
1271 if (ramsize < 16)
1272 rxspace = ramsize / 2;
1273 else
1274 rxspace = 8 + (2*(ramsize - 16))/3;
1275
1276 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1277 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1278
1279 /* Make sure SyncQ is disabled */
1280 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1281 RB_RST_SET);
1282 }
1283
1284 sky2_qset(hw, txqaddr[port]);
1285
1286 /* Set almost empty threshold */
1287 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1288 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1289 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1290
1291 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1292 TX_RING_SIZE - 1);
1293
1294 err = sky2_rx_start(sky2);
1295 if (err)
1296 goto err_out;
1297
1298 /* Enable interrupts from phy/mac for port */
1299 imask = sky2_read32(hw, B0_IMSK);
1300 imask |= portirq_msk[port];
1301 sky2_write32(hw, B0_IMSK, imask);
1302
1303 return 0;
1304
1305 err_out:
1306 if (sky2->rx_le) {
1307 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1308 sky2->rx_le, sky2->rx_le_map);
1309 sky2->rx_le = NULL;
1310 }
1311 if (sky2->tx_le) {
1312 pci_free_consistent(hw->pdev,
1313 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1314 sky2->tx_le, sky2->tx_le_map);
1315 sky2->tx_le = NULL;
1316 }
1317 kfree(sky2->tx_ring);
1318 kfree(sky2->rx_ring);
1319
1320 sky2->tx_ring = NULL;
1321 sky2->rx_ring = NULL;
1322 return err;
1323 }
1324
1325 /* Modular subtraction in ring */
1326 static inline int tx_dist(unsigned tail, unsigned head)
1327 {
1328 return (head - tail) & (TX_RING_SIZE - 1);
1329 }
1330
1331 /* Number of list elements available for next tx */
1332 static inline int tx_avail(const struct sky2_port *sky2)
1333 {
1334 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1335 }
1336
1337 /* Estimate of number of transmit list elements required */
1338 static unsigned tx_le_req(const struct sk_buff *skb)
1339 {
1340 unsigned count;
1341
1342 count = sizeof(dma_addr_t) / sizeof(u32);
1343 count += skb_shinfo(skb)->nr_frags * count;
1344
1345 if (skb_is_gso(skb))
1346 ++count;
1347
1348 if (skb->ip_summed == CHECKSUM_PARTIAL)
1349 ++count;
1350
1351 return count;
1352 }
1353
1354 /*
1355 * Put one packet in ring for transmit.
1356 * A single packet can generate multiple list elements, and
1357 * the number of ring elements will probably be less than the number
1358 * of list elements used.
1359 */
1360 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1361 {
1362 struct sky2_port *sky2 = netdev_priv(dev);
1363 struct sky2_hw *hw = sky2->hw;
1364 struct sky2_tx_le *le = NULL;
1365 struct tx_ring_info *re;
1366 unsigned i, len;
1367 dma_addr_t mapping;
1368 u32 addr64;
1369 u16 mss;
1370 u8 ctrl;
1371
1372 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1373 return NETDEV_TX_BUSY;
1374
1375 if (unlikely(netif_msg_tx_queued(sky2)))
1376 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1377 dev->name, sky2->tx_prod, skb->len);
1378
1379 len = skb_headlen(skb);
1380 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1381 addr64 = high32(mapping);
1382
1383 /* Send high bits if changed or crosses boundary */
1384 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1385 le = get_tx_le(sky2);
1386 le->addr = cpu_to_le32(addr64);
1387 le->opcode = OP_ADDR64 | HW_OWNER;
1388 sky2->tx_addr64 = high32(mapping + len);
1389 }
1390
1391 /* Check for TCP Segmentation Offload */
1392 mss = skb_shinfo(skb)->gso_size;
1393 if (mss != 0) {
1394 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1395 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1396 mss += ETH_HLEN;
1397
1398 if (mss != sky2->tx_last_mss) {
1399 le = get_tx_le(sky2);
1400 le->addr = cpu_to_le32(mss);
1401 le->opcode = OP_LRGLEN | HW_OWNER;
1402 sky2->tx_last_mss = mss;
1403 }
1404 }
1405
1406 ctrl = 0;
1407 #ifdef SKY2_VLAN_TAG_USED
1408 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1409 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1410 if (!le) {
1411 le = get_tx_le(sky2);
1412 le->addr = 0;
1413 le->opcode = OP_VLAN|HW_OWNER;
1414 } else
1415 le->opcode |= OP_VLAN;
1416 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1417 ctrl |= INS_VLAN;
1418 }
1419 #endif
1420
1421 /* Handle TCP checksum offload */
1422 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1423 unsigned offset = skb->h.raw - skb->data;
1424 u32 tcpsum;
1425
1426 tcpsum = offset << 16; /* sum start */
1427 tcpsum |= offset + skb->csum_offset; /* sum write */
1428
1429 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1430 if (skb->nh.iph->protocol == IPPROTO_UDP)
1431 ctrl |= UDPTCP;
1432
1433 if (tcpsum != sky2->tx_tcpsum) {
1434 sky2->tx_tcpsum = tcpsum;
1435
1436 le = get_tx_le(sky2);
1437 le->addr = cpu_to_le32(tcpsum);
1438 le->length = 0; /* initial checksum value */
1439 le->ctrl = 1; /* one packet */
1440 le->opcode = OP_TCPLISW | HW_OWNER;
1441 }
1442 }
1443
1444 le = get_tx_le(sky2);
1445 le->addr = cpu_to_le32((u32) mapping);
1446 le->length = cpu_to_le16(len);
1447 le->ctrl = ctrl;
1448 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1449
1450 re = tx_le_re(sky2, le);
1451 re->skb = skb;
1452 pci_unmap_addr_set(re, mapaddr, mapping);
1453 pci_unmap_len_set(re, maplen, len);
1454
1455 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1456 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1457
1458 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1459 frag->size, PCI_DMA_TODEVICE);
1460 addr64 = high32(mapping);
1461 if (addr64 != sky2->tx_addr64) {
1462 le = get_tx_le(sky2);
1463 le->addr = cpu_to_le32(addr64);
1464 le->ctrl = 0;
1465 le->opcode = OP_ADDR64 | HW_OWNER;
1466 sky2->tx_addr64 = addr64;
1467 }
1468
1469 le = get_tx_le(sky2);
1470 le->addr = cpu_to_le32((u32) mapping);
1471 le->length = cpu_to_le16(frag->size);
1472 le->ctrl = ctrl;
1473 le->opcode = OP_BUFFER | HW_OWNER;
1474
1475 re = tx_le_re(sky2, le);
1476 re->skb = skb;
1477 pci_unmap_addr_set(re, mapaddr, mapping);
1478 pci_unmap_len_set(re, maplen, frag->size);
1479 }
1480
1481 le->ctrl |= EOP;
1482
1483 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1484 netif_stop_queue(dev);
1485
1486 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1487
1488 dev->trans_start = jiffies;
1489 return NETDEV_TX_OK;
1490 }
1491
1492 /*
1493 * Free ring elements from starting at tx_cons until "done"
1494 *
1495 * NB: the hardware will tell us about partial completion of multi-part
1496 * buffers so make sure not to free skb to early.
1497 */
1498 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1499 {
1500 struct net_device *dev = sky2->netdev;
1501 struct pci_dev *pdev = sky2->hw->pdev;
1502 unsigned idx;
1503
1504 BUG_ON(done >= TX_RING_SIZE);
1505
1506 for (idx = sky2->tx_cons; idx != done;
1507 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1508 struct sky2_tx_le *le = sky2->tx_le + idx;
1509 struct tx_ring_info *re = sky2->tx_ring + idx;
1510
1511 switch(le->opcode & ~HW_OWNER) {
1512 case OP_LARGESEND:
1513 case OP_PACKET:
1514 pci_unmap_single(pdev,
1515 pci_unmap_addr(re, mapaddr),
1516 pci_unmap_len(re, maplen),
1517 PCI_DMA_TODEVICE);
1518 break;
1519 case OP_BUFFER:
1520 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1521 pci_unmap_len(re, maplen),
1522 PCI_DMA_TODEVICE);
1523 break;
1524 }
1525
1526 if (le->ctrl & EOP) {
1527 if (unlikely(netif_msg_tx_done(sky2)))
1528 printk(KERN_DEBUG "%s: tx done %u\n",
1529 dev->name, idx);
1530 sky2->net_stats.tx_packets++;
1531 sky2->net_stats.tx_bytes += re->skb->len;
1532
1533 dev_kfree_skb_any(re->skb);
1534 }
1535
1536 le->opcode = 0; /* paranoia */
1537 }
1538
1539 sky2->tx_cons = idx;
1540 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1541 netif_wake_queue(dev);
1542 }
1543
1544 /* Cleanup all untransmitted buffers, assume transmitter not running */
1545 static void sky2_tx_clean(struct net_device *dev)
1546 {
1547 struct sky2_port *sky2 = netdev_priv(dev);
1548
1549 netif_tx_lock_bh(dev);
1550 sky2_tx_complete(sky2, sky2->tx_prod);
1551 netif_tx_unlock_bh(dev);
1552 }
1553
1554 /* Network shutdown */
1555 static int sky2_down(struct net_device *dev)
1556 {
1557 struct sky2_port *sky2 = netdev_priv(dev);
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1560 u16 ctrl;
1561 u32 imask;
1562
1563 /* Never really got started! */
1564 if (!sky2->tx_le)
1565 return 0;
1566
1567 if (netif_msg_ifdown(sky2))
1568 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1569
1570 /* Stop more packets from being queued */
1571 netif_stop_queue(dev);
1572 netif_carrier_off(dev);
1573
1574 /* Disable port IRQ */
1575 imask = sky2_read32(hw, B0_IMSK);
1576 imask &= ~portirq_msk[port];
1577 sky2_write32(hw, B0_IMSK, imask);
1578
1579 /*
1580 * Both ports share the NAPI poll on port 0, so if necessary undo the
1581 * the disable that is done in dev_close.
1582 */
1583 if (sky2->port == 0 && hw->ports > 1)
1584 netif_poll_enable(dev);
1585
1586 sky2_gmac_reset(hw, port);
1587
1588 /* Stop transmitter */
1589 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1590 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1591
1592 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1593 RB_RST_SET | RB_DIS_OP_MD);
1594
1595 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1596 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1597 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1598
1599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1600
1601 /* Workaround shared GMAC reset */
1602 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1603 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1605
1606 /* Disable Force Sync bit and Enable Alloc bit */
1607 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1608 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1609
1610 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1611 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1612 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1613
1614 /* Reset the PCI FIFO of the async Tx queue */
1615 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1616 BMU_RST_SET | BMU_FIFO_RST);
1617
1618 /* Reset the Tx prefetch units */
1619 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1620 PREF_UNIT_RST_SET);
1621
1622 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1623
1624 sky2_rx_stop(sky2);
1625
1626 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1627 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1628
1629 sky2_phy_power(hw, port, 0);
1630
1631 /* turn off LED's */
1632 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1633
1634 synchronize_irq(hw->pdev->irq);
1635
1636 sky2_tx_clean(dev);
1637 sky2_rx_clean(sky2);
1638
1639 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1640 sky2->rx_le, sky2->rx_le_map);
1641 kfree(sky2->rx_ring);
1642
1643 pci_free_consistent(hw->pdev,
1644 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1645 sky2->tx_le, sky2->tx_le_map);
1646 kfree(sky2->tx_ring);
1647
1648 sky2->tx_le = NULL;
1649 sky2->rx_le = NULL;
1650
1651 sky2->rx_ring = NULL;
1652 sky2->tx_ring = NULL;
1653
1654 return 0;
1655 }
1656
1657 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1658 {
1659 if (!sky2_is_copper(hw))
1660 return SPEED_1000;
1661
1662 if (hw->chip_id == CHIP_ID_YUKON_FE)
1663 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1664
1665 switch (aux & PHY_M_PS_SPEED_MSK) {
1666 case PHY_M_PS_SPEED_1000:
1667 return SPEED_1000;
1668 case PHY_M_PS_SPEED_100:
1669 return SPEED_100;
1670 default:
1671 return SPEED_10;
1672 }
1673 }
1674
1675 static void sky2_link_up(struct sky2_port *sky2)
1676 {
1677 struct sky2_hw *hw = sky2->hw;
1678 unsigned port = sky2->port;
1679 u16 reg;
1680 static const char *fc_name[] = {
1681 [FC_NONE] = "none",
1682 [FC_TX] = "tx",
1683 [FC_RX] = "rx",
1684 [FC_BOTH] = "both",
1685 };
1686
1687 /* enable Rx/Tx */
1688 reg = gma_read16(hw, port, GM_GP_CTRL);
1689 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1690 gma_write16(hw, port, GM_GP_CTRL, reg);
1691
1692 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1693
1694 netif_carrier_on(sky2->netdev);
1695 netif_wake_queue(sky2->netdev);
1696
1697 /* Turn on link LED */
1698 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1699 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1700
1701 if (hw->chip_id == CHIP_ID_YUKON_XL
1702 || hw->chip_id == CHIP_ID_YUKON_EC_U
1703 || hw->chip_id == CHIP_ID_YUKON_EX) {
1704 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1705 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1706
1707 switch(sky2->speed) {
1708 case SPEED_10:
1709 led |= PHY_M_LEDC_INIT_CTRL(7);
1710 break;
1711
1712 case SPEED_100:
1713 led |= PHY_M_LEDC_STA1_CTRL(7);
1714 break;
1715
1716 case SPEED_1000:
1717 led |= PHY_M_LEDC_STA0_CTRL(7);
1718 break;
1719 }
1720
1721 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1722 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1724 }
1725
1726 if (netif_msg_link(sky2))
1727 printk(KERN_INFO PFX
1728 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1729 sky2->netdev->name, sky2->speed,
1730 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1731 fc_name[sky2->flow_status]);
1732 }
1733
1734 static void sky2_link_down(struct sky2_port *sky2)
1735 {
1736 struct sky2_hw *hw = sky2->hw;
1737 unsigned port = sky2->port;
1738 u16 reg;
1739
1740 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1741
1742 reg = gma_read16(hw, port, GM_GP_CTRL);
1743 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1744 gma_write16(hw, port, GM_GP_CTRL, reg);
1745
1746 netif_carrier_off(sky2->netdev);
1747 netif_stop_queue(sky2->netdev);
1748
1749 /* Turn on link LED */
1750 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1751
1752 if (netif_msg_link(sky2))
1753 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1754
1755 sky2_phy_init(hw, port);
1756 }
1757
1758 static enum flow_control sky2_flow(int rx, int tx)
1759 {
1760 if (rx)
1761 return tx ? FC_BOTH : FC_RX;
1762 else
1763 return tx ? FC_TX : FC_NONE;
1764 }
1765
1766 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1767 {
1768 struct sky2_hw *hw = sky2->hw;
1769 unsigned port = sky2->port;
1770 u16 advert, lpa;
1771
1772 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1773 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1774 if (lpa & PHY_M_AN_RF) {
1775 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1776 return -1;
1777 }
1778
1779 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1780 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1781 sky2->netdev->name);
1782 return -1;
1783 }
1784
1785 sky2->speed = sky2_phy_speed(hw, aux);
1786 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1787
1788 /* Since the pause result bits seem to in different positions on
1789 * different chips. look at registers.
1790 */
1791 if (!sky2_is_copper(hw)) {
1792 /* Shift for bits in fiber PHY */
1793 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1794 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1795
1796 if (advert & ADVERTISE_1000XPAUSE)
1797 advert |= ADVERTISE_PAUSE_CAP;
1798 if (advert & ADVERTISE_1000XPSE_ASYM)
1799 advert |= ADVERTISE_PAUSE_ASYM;
1800 if (lpa & LPA_1000XPAUSE)
1801 lpa |= LPA_PAUSE_CAP;
1802 if (lpa & LPA_1000XPAUSE_ASYM)
1803 lpa |= LPA_PAUSE_ASYM;
1804 }
1805
1806 sky2->flow_status = FC_NONE;
1807 if (advert & ADVERTISE_PAUSE_CAP) {
1808 if (lpa & LPA_PAUSE_CAP)
1809 sky2->flow_status = FC_BOTH;
1810 else if (advert & ADVERTISE_PAUSE_ASYM)
1811 sky2->flow_status = FC_RX;
1812 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1813 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1814 sky2->flow_status = FC_TX;
1815 }
1816
1817 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1818 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1819 sky2->flow_status = FC_NONE;
1820
1821 if (sky2->flow_status & FC_TX)
1822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1823 else
1824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1825
1826 return 0;
1827 }
1828
1829 /* Interrupt from PHY */
1830 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1831 {
1832 struct net_device *dev = hw->dev[port];
1833 struct sky2_port *sky2 = netdev_priv(dev);
1834 u16 istatus, phystat;
1835
1836 if (!netif_running(dev))
1837 return;
1838
1839 spin_lock(&sky2->phy_lock);
1840 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1841 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1842
1843 if (netif_msg_intr(sky2))
1844 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1845 sky2->netdev->name, istatus, phystat);
1846
1847 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1848 if (sky2_autoneg_done(sky2, phystat) == 0)
1849 sky2_link_up(sky2);
1850 goto out;
1851 }
1852
1853 if (istatus & PHY_M_IS_LSP_CHANGE)
1854 sky2->speed = sky2_phy_speed(hw, phystat);
1855
1856 if (istatus & PHY_M_IS_DUP_CHANGE)
1857 sky2->duplex =
1858 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1859
1860 if (istatus & PHY_M_IS_LST_CHANGE) {
1861 if (phystat & PHY_M_PS_LINK_UP)
1862 sky2_link_up(sky2);
1863 else
1864 sky2_link_down(sky2);
1865 }
1866 out:
1867 spin_unlock(&sky2->phy_lock);
1868 }
1869
1870 /* Transmit timeout is only called if we are running, carrier is up
1871 * and tx queue is full (stopped).
1872 */
1873 static void sky2_tx_timeout(struct net_device *dev)
1874 {
1875 struct sky2_port *sky2 = netdev_priv(dev);
1876 struct sky2_hw *hw = sky2->hw;
1877
1878 if (netif_msg_timer(sky2))
1879 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1880
1881 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1882 dev->name, sky2->tx_cons, sky2->tx_prod,
1883 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1884 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1885
1886 /* can't restart safely under softirq */
1887 schedule_work(&hw->restart_work);
1888 }
1889
1890 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1891 {
1892 struct sky2_port *sky2 = netdev_priv(dev);
1893 struct sky2_hw *hw = sky2->hw;
1894 unsigned port = sky2->port;
1895 int err;
1896 u16 ctl, mode;
1897 u32 imask;
1898
1899 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1900 return -EINVAL;
1901
1902 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1903 return -EINVAL;
1904
1905 if (!netif_running(dev)) {
1906 dev->mtu = new_mtu;
1907 return 0;
1908 }
1909
1910 imask = sky2_read32(hw, B0_IMSK);
1911 sky2_write32(hw, B0_IMSK, 0);
1912
1913 dev->trans_start = jiffies; /* prevent tx timeout */
1914 netif_stop_queue(dev);
1915 netif_poll_disable(hw->dev[0]);
1916
1917 synchronize_irq(hw->pdev->irq);
1918
1919 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1920 if (new_mtu > ETH_DATA_LEN) {
1921 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1922 TX_JUMBO_ENA | TX_STFW_DIS);
1923 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1924 } else
1925 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1926 TX_JUMBO_DIS | TX_STFW_ENA);
1927 }
1928
1929 ctl = gma_read16(hw, port, GM_GP_CTRL);
1930 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1931 sky2_rx_stop(sky2);
1932 sky2_rx_clean(sky2);
1933
1934 dev->mtu = new_mtu;
1935
1936 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1937 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1938
1939 if (dev->mtu > ETH_DATA_LEN)
1940 mode |= GM_SMOD_JUMBO_ENA;
1941
1942 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1943
1944 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1945
1946 err = sky2_rx_start(sky2);
1947 sky2_write32(hw, B0_IMSK, imask);
1948
1949 if (err)
1950 dev_close(dev);
1951 else {
1952 gma_write16(hw, port, GM_GP_CTRL, ctl);
1953
1954 netif_poll_enable(hw->dev[0]);
1955 netif_wake_queue(dev);
1956 }
1957
1958 return err;
1959 }
1960
1961 /* For small just reuse existing skb for next receive */
1962 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1963 const struct rx_ring_info *re,
1964 unsigned length)
1965 {
1966 struct sk_buff *skb;
1967
1968 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1969 if (likely(skb)) {
1970 skb_reserve(skb, 2);
1971 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1972 length, PCI_DMA_FROMDEVICE);
1973 memcpy(skb->data, re->skb->data, length);
1974 skb->ip_summed = re->skb->ip_summed;
1975 skb->csum = re->skb->csum;
1976 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1977 length, PCI_DMA_FROMDEVICE);
1978 re->skb->ip_summed = CHECKSUM_NONE;
1979 skb_put(skb, length);
1980 }
1981 return skb;
1982 }
1983
1984 /* Adjust length of skb with fragments to match received data */
1985 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1986 unsigned int length)
1987 {
1988 int i, num_frags;
1989 unsigned int size;
1990
1991 /* put header into skb */
1992 size = min(length, hdr_space);
1993 skb->tail += size;
1994 skb->len += size;
1995 length -= size;
1996
1997 num_frags = skb_shinfo(skb)->nr_frags;
1998 for (i = 0; i < num_frags; i++) {
1999 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2000
2001 if (length == 0) {
2002 /* don't need this page */
2003 __free_page(frag->page);
2004 --skb_shinfo(skb)->nr_frags;
2005 } else {
2006 size = min(length, (unsigned) PAGE_SIZE);
2007
2008 frag->size = size;
2009 skb->data_len += size;
2010 skb->truesize += size;
2011 skb->len += size;
2012 length -= size;
2013 }
2014 }
2015 }
2016
2017 /* Normal packet - take skb from ring element and put in a new one */
2018 static struct sk_buff *receive_new(struct sky2_port *sky2,
2019 struct rx_ring_info *re,
2020 unsigned int length)
2021 {
2022 struct sk_buff *skb, *nskb;
2023 unsigned hdr_space = sky2->rx_data_size;
2024
2025 pr_debug(PFX "receive new length=%d\n", length);
2026
2027 /* Don't be tricky about reusing pages (yet) */
2028 nskb = sky2_rx_alloc(sky2);
2029 if (unlikely(!nskb))
2030 return NULL;
2031
2032 skb = re->skb;
2033 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2034
2035 prefetch(skb->data);
2036 re->skb = nskb;
2037 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2038
2039 if (skb_shinfo(skb)->nr_frags)
2040 skb_put_frags(skb, hdr_space, length);
2041 else
2042 skb_put(skb, length);
2043 return skb;
2044 }
2045
2046 /*
2047 * Receive one packet.
2048 * For larger packets, get new buffer.
2049 */
2050 static struct sk_buff *sky2_receive(struct net_device *dev,
2051 u16 length, u32 status)
2052 {
2053 struct sky2_port *sky2 = netdev_priv(dev);
2054 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2055 struct sk_buff *skb = NULL;
2056
2057 if (unlikely(netif_msg_rx_status(sky2)))
2058 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2059 dev->name, sky2->rx_next, status, length);
2060
2061 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2062 prefetch(sky2->rx_ring + sky2->rx_next);
2063
2064 if (status & GMR_FS_ANY_ERR)
2065 goto error;
2066
2067 if (!(status & GMR_FS_RX_OK))
2068 goto resubmit;
2069
2070 if (length < copybreak)
2071 skb = receive_copy(sky2, re, length);
2072 else
2073 skb = receive_new(sky2, re, length);
2074 resubmit:
2075 sky2_rx_submit(sky2, re);
2076
2077 return skb;
2078
2079 error:
2080 ++sky2->net_stats.rx_errors;
2081 if (status & GMR_FS_RX_FF_OV) {
2082 sky2->net_stats.rx_over_errors++;
2083 goto resubmit;
2084 }
2085
2086 if (netif_msg_rx_err(sky2) && net_ratelimit())
2087 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2088 dev->name, status, length);
2089
2090 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2091 sky2->net_stats.rx_length_errors++;
2092 if (status & GMR_FS_FRAGMENT)
2093 sky2->net_stats.rx_frame_errors++;
2094 if (status & GMR_FS_CRC_ERR)
2095 sky2->net_stats.rx_crc_errors++;
2096
2097 goto resubmit;
2098 }
2099
2100 /* Transmit complete */
2101 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2102 {
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104
2105 if (netif_running(dev)) {
2106 netif_tx_lock(dev);
2107 sky2_tx_complete(sky2, last);
2108 netif_tx_unlock(dev);
2109 }
2110 }
2111
2112 /* Process status response ring */
2113 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2114 {
2115 struct sky2_port *sky2;
2116 int work_done = 0;
2117 unsigned buf_write[2] = { 0, 0 };
2118 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2119
2120 rmb();
2121
2122 while (hw->st_idx != hwidx) {
2123 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2124 struct net_device *dev;
2125 struct sk_buff *skb;
2126 u32 status;
2127 u16 length;
2128
2129 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2130
2131 BUG_ON(le->link >= 2);
2132 dev = hw->dev[le->link];
2133
2134 sky2 = netdev_priv(dev);
2135 length = le16_to_cpu(le->length);
2136 status = le32_to_cpu(le->status);
2137
2138 switch (le->opcode & ~HW_OWNER) {
2139 case OP_RXSTAT:
2140 skb = sky2_receive(dev, length, status);
2141 if (!skb)
2142 goto force_update;
2143
2144 skb->protocol = eth_type_trans(skb, dev);
2145 sky2->net_stats.rx_packets++;
2146 sky2->net_stats.rx_bytes += skb->len;
2147 dev->last_rx = jiffies;
2148
2149 #ifdef SKY2_VLAN_TAG_USED
2150 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2151 vlan_hwaccel_receive_skb(skb,
2152 sky2->vlgrp,
2153 be16_to_cpu(sky2->rx_tag));
2154 } else
2155 #endif
2156 netif_receive_skb(skb);
2157
2158 /* Update receiver after 16 frames */
2159 if (++buf_write[le->link] == RX_BUF_WRITE) {
2160 force_update:
2161 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2162 buf_write[le->link] = 0;
2163 }
2164
2165 /* Stop after net poll weight */
2166 if (++work_done >= to_do)
2167 goto exit_loop;
2168 break;
2169
2170 #ifdef SKY2_VLAN_TAG_USED
2171 case OP_RXVLAN:
2172 sky2->rx_tag = length;
2173 break;
2174
2175 case OP_RXCHKSVLAN:
2176 sky2->rx_tag = length;
2177 /* fall through */
2178 #endif
2179 case OP_RXCHKS:
2180 if (!sky2->rx_csum)
2181 break;
2182
2183 /* Both checksum counters are programmed to start at
2184 * the same offset, so unless there is a problem they
2185 * should match. This failure is an early indication that
2186 * hardware receive checksumming won't work.
2187 */
2188 if (likely(status >> 16 == (status & 0xffff))) {
2189 skb = sky2->rx_ring[sky2->rx_next].skb;
2190 skb->ip_summed = CHECKSUM_COMPLETE;
2191 skb->csum = status & 0xffff;
2192 } else {
2193 printk(KERN_NOTICE PFX "%s: hardware receive "
2194 "checksum problem (status = %#x)\n",
2195 dev->name, status);
2196 sky2->rx_csum = 0;
2197 sky2_write32(sky2->hw,
2198 Q_ADDR(rxqaddr[le->link], Q_CSR),
2199 BMU_DIS_RX_CHKSUM);
2200 }
2201 break;
2202
2203 case OP_TXINDEXLE:
2204 /* TX index reports status for both ports */
2205 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2206 sky2_tx_done(hw->dev[0], status & 0xfff);
2207 if (hw->dev[1])
2208 sky2_tx_done(hw->dev[1],
2209 ((status >> 24) & 0xff)
2210 | (u16)(length & 0xf) << 8);
2211 break;
2212
2213 default:
2214 if (net_ratelimit())
2215 printk(KERN_WARNING PFX
2216 "unknown status opcode 0x%x\n", le->opcode);
2217 goto exit_loop;
2218 }
2219 }
2220
2221 /* Fully processed status ring so clear irq */
2222 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2223
2224 exit_loop:
2225 if (buf_write[0]) {
2226 sky2 = netdev_priv(hw->dev[0]);
2227 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2228 }
2229
2230 if (buf_write[1]) {
2231 sky2 = netdev_priv(hw->dev[1]);
2232 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2233 }
2234
2235 return work_done;
2236 }
2237
2238 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2239 {
2240 struct net_device *dev = hw->dev[port];
2241
2242 if (net_ratelimit())
2243 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2244 dev->name, status);
2245
2246 if (status & Y2_IS_PAR_RD1) {
2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2249 dev->name);
2250 /* Clear IRQ */
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_WR1) {
2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2257 dev->name);
2258
2259 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2260 }
2261
2262 if (status & Y2_IS_PAR_MAC1) {
2263 if (net_ratelimit())
2264 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2265 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2266 }
2267
2268 if (status & Y2_IS_PAR_RX1) {
2269 if (net_ratelimit())
2270 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2271 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2272 }
2273
2274 if (status & Y2_IS_TCP_TXA1) {
2275 if (net_ratelimit())
2276 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2277 dev->name);
2278 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2279 }
2280 }
2281
2282 static void sky2_hw_intr(struct sky2_hw *hw)
2283 {
2284 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2285
2286 if (status & Y2_IS_TIST_OV)
2287 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2288
2289 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2290 u16 pci_err;
2291
2292 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2293 if (net_ratelimit())
2294 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2295 pci_err);
2296
2297 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2298 sky2_pci_write16(hw, PCI_STATUS,
2299 pci_err | PCI_STATUS_ERROR_BITS);
2300 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2301 }
2302
2303 if (status & Y2_IS_PCI_EXP) {
2304 /* PCI-Express uncorrectable Error occurred */
2305 u32 pex_err;
2306
2307 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2308
2309 if (net_ratelimit())
2310 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2311 pex_err);
2312
2313 /* clear the interrupt */
2314 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2315 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2316 0xffffffffUL);
2317 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2318
2319 if (pex_err & PEX_FATAL_ERRORS) {
2320 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2321 hwmsk &= ~Y2_IS_PCI_EXP;
2322 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2323 }
2324 }
2325
2326 if (status & Y2_HWE_L1_MASK)
2327 sky2_hw_error(hw, 0, status);
2328 status >>= 8;
2329 if (status & Y2_HWE_L1_MASK)
2330 sky2_hw_error(hw, 1, status);
2331 }
2332
2333 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2334 {
2335 struct net_device *dev = hw->dev[port];
2336 struct sky2_port *sky2 = netdev_priv(dev);
2337 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2338
2339 if (netif_msg_intr(sky2))
2340 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2341 dev->name, status);
2342
2343 if (status & GM_IS_RX_FF_OR) {
2344 ++sky2->net_stats.rx_fifo_errors;
2345 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2346 }
2347
2348 if (status & GM_IS_TX_FF_UR) {
2349 ++sky2->net_stats.tx_fifo_errors;
2350 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2351 }
2352 }
2353
2354 /* This should never happen it is a bug. */
2355 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2356 u16 q, unsigned ring_size)
2357 {
2358 struct net_device *dev = hw->dev[port];
2359 struct sky2_port *sky2 = netdev_priv(dev);
2360 unsigned idx;
2361 const u64 *le = (q == Q_R1 || q == Q_R2)
2362 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2363
2364 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2365 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2366 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2367 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2368
2369 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2370 }
2371
2372 /* If idle then force a fake soft NAPI poll once a second
2373 * to work around cases where sharing an edge triggered interrupt.
2374 */
2375 static inline void sky2_idle_start(struct sky2_hw *hw)
2376 {
2377 if (idle_timeout > 0)
2378 mod_timer(&hw->idle_timer,
2379 jiffies + msecs_to_jiffies(idle_timeout));
2380 }
2381
2382 static void sky2_idle(unsigned long arg)
2383 {
2384 struct sky2_hw *hw = (struct sky2_hw *) arg;
2385 struct net_device *dev = hw->dev[0];
2386
2387 if (__netif_rx_schedule_prep(dev))
2388 __netif_rx_schedule(dev);
2389
2390 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2391 }
2392
2393 /* Hardware/software error handling */
2394 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2395 {
2396 if (net_ratelimit())
2397 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2398
2399 if (status & Y2_IS_HW_ERR)
2400 sky2_hw_intr(hw);
2401
2402 if (status & Y2_IS_IRQ_MAC1)
2403 sky2_mac_intr(hw, 0);
2404
2405 if (status & Y2_IS_IRQ_MAC2)
2406 sky2_mac_intr(hw, 1);
2407
2408 if (status & Y2_IS_CHK_RX1)
2409 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2410
2411 if (status & Y2_IS_CHK_RX2)
2412 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2413
2414 if (status & Y2_IS_CHK_TXA1)
2415 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2416
2417 if (status & Y2_IS_CHK_TXA2)
2418 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2419 }
2420
2421 static int sky2_poll(struct net_device *dev0, int *budget)
2422 {
2423 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2424 int work_limit = min(dev0->quota, *budget);
2425 int work_done = 0;
2426 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2427
2428 if (unlikely(status & Y2_IS_ERROR))
2429 sky2_err_intr(hw, status);
2430
2431 if (status & Y2_IS_IRQ_PHY1)
2432 sky2_phy_intr(hw, 0);
2433
2434 if (status & Y2_IS_IRQ_PHY2)
2435 sky2_phy_intr(hw, 1);
2436
2437 work_done = sky2_status_intr(hw, work_limit);
2438 if (work_done < work_limit) {
2439 netif_rx_complete(dev0);
2440
2441 sky2_read32(hw, B0_Y2_SP_LISR);
2442 return 0;
2443 } else {
2444 *budget -= work_done;
2445 dev0->quota -= work_done;
2446 return 1;
2447 }
2448 }
2449
2450 static irqreturn_t sky2_intr(int irq, void *dev_id)
2451 {
2452 struct sky2_hw *hw = dev_id;
2453 struct net_device *dev0 = hw->dev[0];
2454 u32 status;
2455
2456 /* Reading this mask interrupts as side effect */
2457 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2458 if (status == 0 || status == ~0)
2459 return IRQ_NONE;
2460
2461 prefetch(&hw->st_le[hw->st_idx]);
2462 if (likely(__netif_rx_schedule_prep(dev0)))
2463 __netif_rx_schedule(dev0);
2464
2465 return IRQ_HANDLED;
2466 }
2467
2468 #ifdef CONFIG_NET_POLL_CONTROLLER
2469 static void sky2_netpoll(struct net_device *dev)
2470 {
2471 struct sky2_port *sky2 = netdev_priv(dev);
2472 struct net_device *dev0 = sky2->hw->dev[0];
2473
2474 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2475 __netif_rx_schedule(dev0);
2476 }
2477 #endif
2478
2479 /* Chip internal frequency for clock calculations */
2480 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2481 {
2482 switch (hw->chip_id) {
2483 case CHIP_ID_YUKON_EC:
2484 case CHIP_ID_YUKON_EC_U:
2485 case CHIP_ID_YUKON_EX:
2486 return 125; /* 125 Mhz */
2487 case CHIP_ID_YUKON_FE:
2488 return 100; /* 100 Mhz */
2489 default: /* YUKON_XL */
2490 return 156; /* 156 Mhz */
2491 }
2492 }
2493
2494 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2495 {
2496 return sky2_mhz(hw) * us;
2497 }
2498
2499 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2500 {
2501 return clk / sky2_mhz(hw);
2502 }
2503
2504
2505 static int __devinit sky2_init(struct sky2_hw *hw)
2506 {
2507 u8 t8;
2508
2509 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2510
2511 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2512 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2513 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2514 hw->chip_id);
2515 return -EOPNOTSUPP;
2516 }
2517
2518 if (hw->chip_id == CHIP_ID_YUKON_EX)
2519 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2520 "Please report success or failure to <netdev@vger.kernel.org>\n");
2521
2522 /* Make sure and enable all clocks */
2523 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2524 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2525
2526 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2527
2528 /* This rev is really old, and requires untested workarounds */
2529 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2530 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2531 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2532 hw->chip_id, hw->chip_rev);
2533 return -EOPNOTSUPP;
2534 }
2535
2536 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2537 hw->ports = 1;
2538 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2539 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2540 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2541 ++hw->ports;
2542 }
2543
2544 return 0;
2545 }
2546
2547 static void sky2_reset(struct sky2_hw *hw)
2548 {
2549 u16 status;
2550 int i;
2551
2552 /* disable ASF */
2553 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2554 status = sky2_read16(hw, HCU_CCSR);
2555 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2556 HCU_CCSR_UC_STATE_MSK);
2557 sky2_write16(hw, HCU_CCSR, status);
2558 } else
2559 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2560 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2561
2562 /* do a SW reset */
2563 sky2_write8(hw, B0_CTST, CS_RST_SET);
2564 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2565
2566 /* clear PCI errors, if any */
2567 status = sky2_pci_read16(hw, PCI_STATUS);
2568
2569 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2570 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2571
2572
2573 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2574
2575 /* clear any PEX errors */
2576 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2577 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2578
2579
2580 sky2_power_on(hw);
2581
2582 for (i = 0; i < hw->ports; i++) {
2583 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2584 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2585 }
2586
2587 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2588
2589 /* Clear I2C IRQ noise */
2590 sky2_write32(hw, B2_I2C_IRQ, 1);
2591
2592 /* turn off hardware timer (unused) */
2593 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2594 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2595
2596 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2597
2598 /* Turn off descriptor polling */
2599 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2600
2601 /* Turn off receive timestamp */
2602 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2603 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2604
2605 /* enable the Tx Arbiters */
2606 for (i = 0; i < hw->ports; i++)
2607 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2608
2609 /* Initialize ram interface */
2610 for (i = 0; i < hw->ports; i++) {
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2612
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2625 }
2626
2627 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2628
2629 for (i = 0; i < hw->ports; i++)
2630 sky2_gmac_reset(hw, i);
2631
2632 memset(hw->st_le, 0, STATUS_LE_BYTES);
2633 hw->st_idx = 0;
2634
2635 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2636 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2637
2638 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2639 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2640
2641 /* Set the list last index */
2642 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2643
2644 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2645 sky2_write8(hw, STAT_FIFO_WM, 16);
2646
2647 /* set Status-FIFO ISR watermark */
2648 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2649 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2650 else
2651 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2652
2653 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2654 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2655 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2656
2657 /* enable status unit */
2658 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2659
2660 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2661 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2662 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2663 }
2664
2665 static void sky2_restart(struct work_struct *work)
2666 {
2667 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2668 struct net_device *dev;
2669 int i, err;
2670
2671 dev_dbg(&hw->pdev->dev, "restarting\n");
2672
2673 del_timer_sync(&hw->idle_timer);
2674
2675 rtnl_lock();
2676 sky2_write32(hw, B0_IMSK, 0);
2677 sky2_read32(hw, B0_IMSK);
2678
2679 netif_poll_disable(hw->dev[0]);
2680
2681 for (i = 0; i < hw->ports; i++) {
2682 dev = hw->dev[i];
2683 if (netif_running(dev))
2684 sky2_down(dev);
2685 }
2686
2687 sky2_reset(hw);
2688 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2689 netif_poll_enable(hw->dev[0]);
2690
2691 for (i = 0; i < hw->ports; i++) {
2692 dev = hw->dev[i];
2693 if (netif_running(dev)) {
2694 err = sky2_up(dev);
2695 if (err) {
2696 printk(KERN_INFO PFX "%s: could not restart %d\n",
2697 dev->name, err);
2698 dev_close(dev);
2699 }
2700 }
2701 }
2702
2703 sky2_idle_start(hw);
2704
2705 rtnl_unlock();
2706 }
2707
2708 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2709 {
2710 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2711 }
2712
2713 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2714 {
2715 const struct sky2_port *sky2 = netdev_priv(dev);
2716
2717 wol->supported = sky2_wol_supported(sky2->hw);
2718 wol->wolopts = sky2->wol;
2719 }
2720
2721 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2722 {
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725
2726 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2727 return -EOPNOTSUPP;
2728
2729 sky2->wol = wol->wolopts;
2730
2731 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2732 sky2_write32(hw, B0_CTST, sky2->wol
2733 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2734
2735 if (!netif_running(dev))
2736 sky2_wol_init(sky2);
2737 return 0;
2738 }
2739
2740 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2741 {
2742 if (sky2_is_copper(hw)) {
2743 u32 modes = SUPPORTED_10baseT_Half
2744 | SUPPORTED_10baseT_Full
2745 | SUPPORTED_100baseT_Half
2746 | SUPPORTED_100baseT_Full
2747 | SUPPORTED_Autoneg | SUPPORTED_TP;
2748
2749 if (hw->chip_id != CHIP_ID_YUKON_FE)
2750 modes |= SUPPORTED_1000baseT_Half
2751 | SUPPORTED_1000baseT_Full;
2752 return modes;
2753 } else
2754 return SUPPORTED_1000baseT_Half
2755 | SUPPORTED_1000baseT_Full
2756 | SUPPORTED_Autoneg
2757 | SUPPORTED_FIBRE;
2758 }
2759
2760 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2761 {
2762 struct sky2_port *sky2 = netdev_priv(dev);
2763 struct sky2_hw *hw = sky2->hw;
2764
2765 ecmd->transceiver = XCVR_INTERNAL;
2766 ecmd->supported = sky2_supported_modes(hw);
2767 ecmd->phy_address = PHY_ADDR_MARV;
2768 if (sky2_is_copper(hw)) {
2769 ecmd->supported = SUPPORTED_10baseT_Half
2770 | SUPPORTED_10baseT_Full
2771 | SUPPORTED_100baseT_Half
2772 | SUPPORTED_100baseT_Full
2773 | SUPPORTED_1000baseT_Half
2774 | SUPPORTED_1000baseT_Full
2775 | SUPPORTED_Autoneg | SUPPORTED_TP;
2776 ecmd->port = PORT_TP;
2777 ecmd->speed = sky2->speed;
2778 } else {
2779 ecmd->speed = SPEED_1000;
2780 ecmd->port = PORT_FIBRE;
2781 }
2782
2783 ecmd->advertising = sky2->advertising;
2784 ecmd->autoneg = sky2->autoneg;
2785 ecmd->duplex = sky2->duplex;
2786 return 0;
2787 }
2788
2789 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2790 {
2791 struct sky2_port *sky2 = netdev_priv(dev);
2792 const struct sky2_hw *hw = sky2->hw;
2793 u32 supported = sky2_supported_modes(hw);
2794
2795 if (ecmd->autoneg == AUTONEG_ENABLE) {
2796 ecmd->advertising = supported;
2797 sky2->duplex = -1;
2798 sky2->speed = -1;
2799 } else {
2800 u32 setting;
2801
2802 switch (ecmd->speed) {
2803 case SPEED_1000:
2804 if (ecmd->duplex == DUPLEX_FULL)
2805 setting = SUPPORTED_1000baseT_Full;
2806 else if (ecmd->duplex == DUPLEX_HALF)
2807 setting = SUPPORTED_1000baseT_Half;
2808 else
2809 return -EINVAL;
2810 break;
2811 case SPEED_100:
2812 if (ecmd->duplex == DUPLEX_FULL)
2813 setting = SUPPORTED_100baseT_Full;
2814 else if (ecmd->duplex == DUPLEX_HALF)
2815 setting = SUPPORTED_100baseT_Half;
2816 else
2817 return -EINVAL;
2818 break;
2819
2820 case SPEED_10:
2821 if (ecmd->duplex == DUPLEX_FULL)
2822 setting = SUPPORTED_10baseT_Full;
2823 else if (ecmd->duplex == DUPLEX_HALF)
2824 setting = SUPPORTED_10baseT_Half;
2825 else
2826 return -EINVAL;
2827 break;
2828 default:
2829 return -EINVAL;
2830 }
2831
2832 if ((setting & supported) == 0)
2833 return -EINVAL;
2834
2835 sky2->speed = ecmd->speed;
2836 sky2->duplex = ecmd->duplex;
2837 }
2838
2839 sky2->autoneg = ecmd->autoneg;
2840 sky2->advertising = ecmd->advertising;
2841
2842 if (netif_running(dev))
2843 sky2_phy_reinit(sky2);
2844
2845 return 0;
2846 }
2847
2848 static void sky2_get_drvinfo(struct net_device *dev,
2849 struct ethtool_drvinfo *info)
2850 {
2851 struct sky2_port *sky2 = netdev_priv(dev);
2852
2853 strcpy(info->driver, DRV_NAME);
2854 strcpy(info->version, DRV_VERSION);
2855 strcpy(info->fw_version, "N/A");
2856 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2857 }
2858
2859 static const struct sky2_stat {
2860 char name[ETH_GSTRING_LEN];
2861 u16 offset;
2862 } sky2_stats[] = {
2863 { "tx_bytes", GM_TXO_OK_HI },
2864 { "rx_bytes", GM_RXO_OK_HI },
2865 { "tx_broadcast", GM_TXF_BC_OK },
2866 { "rx_broadcast", GM_RXF_BC_OK },
2867 { "tx_multicast", GM_TXF_MC_OK },
2868 { "rx_multicast", GM_RXF_MC_OK },
2869 { "tx_unicast", GM_TXF_UC_OK },
2870 { "rx_unicast", GM_RXF_UC_OK },
2871 { "tx_mac_pause", GM_TXF_MPAUSE },
2872 { "rx_mac_pause", GM_RXF_MPAUSE },
2873 { "collisions", GM_TXF_COL },
2874 { "late_collision",GM_TXF_LAT_COL },
2875 { "aborted", GM_TXF_ABO_COL },
2876 { "single_collisions", GM_TXF_SNG_COL },
2877 { "multi_collisions", GM_TXF_MUL_COL },
2878
2879 { "rx_short", GM_RXF_SHT },
2880 { "rx_runt", GM_RXE_FRAG },
2881 { "rx_64_byte_packets", GM_RXF_64B },
2882 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2883 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2884 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2885 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2886 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2887 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2888 { "rx_too_long", GM_RXF_LNG_ERR },
2889 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2890 { "rx_jabber", GM_RXF_JAB_PKT },
2891 { "rx_fcs_error", GM_RXF_FCS_ERR },
2892
2893 { "tx_64_byte_packets", GM_TXF_64B },
2894 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2895 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2896 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2897 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2898 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2899 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2900 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2901 };
2902
2903 static u32 sky2_get_rx_csum(struct net_device *dev)
2904 {
2905 struct sky2_port *sky2 = netdev_priv(dev);
2906
2907 return sky2->rx_csum;
2908 }
2909
2910 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2911 {
2912 struct sky2_port *sky2 = netdev_priv(dev);
2913
2914 sky2->rx_csum = data;
2915
2916 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2917 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2918
2919 return 0;
2920 }
2921
2922 static u32 sky2_get_msglevel(struct net_device *netdev)
2923 {
2924 struct sky2_port *sky2 = netdev_priv(netdev);
2925 return sky2->msg_enable;
2926 }
2927
2928 static int sky2_nway_reset(struct net_device *dev)
2929 {
2930 struct sky2_port *sky2 = netdev_priv(dev);
2931
2932 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2933 return -EINVAL;
2934
2935 sky2_phy_reinit(sky2);
2936
2937 return 0;
2938 }
2939
2940 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2941 {
2942 struct sky2_hw *hw = sky2->hw;
2943 unsigned port = sky2->port;
2944 int i;
2945
2946 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2947 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2948 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2949 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2950
2951 for (i = 2; i < count; i++)
2952 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2953 }
2954
2955 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2956 {
2957 struct sky2_port *sky2 = netdev_priv(netdev);
2958 sky2->msg_enable = value;
2959 }
2960
2961 static int sky2_get_stats_count(struct net_device *dev)
2962 {
2963 return ARRAY_SIZE(sky2_stats);
2964 }
2965
2966 static void sky2_get_ethtool_stats(struct net_device *dev,
2967 struct ethtool_stats *stats, u64 * data)
2968 {
2969 struct sky2_port *sky2 = netdev_priv(dev);
2970
2971 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2972 }
2973
2974 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2975 {
2976 int i;
2977
2978 switch (stringset) {
2979 case ETH_SS_STATS:
2980 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2981 memcpy(data + i * ETH_GSTRING_LEN,
2982 sky2_stats[i].name, ETH_GSTRING_LEN);
2983 break;
2984 }
2985 }
2986
2987 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2988 {
2989 struct sky2_port *sky2 = netdev_priv(dev);
2990 return &sky2->net_stats;
2991 }
2992
2993 static int sky2_set_mac_address(struct net_device *dev, void *p)
2994 {
2995 struct sky2_port *sky2 = netdev_priv(dev);
2996 struct sky2_hw *hw = sky2->hw;
2997 unsigned port = sky2->port;
2998 const struct sockaddr *addr = p;
2999
3000 if (!is_valid_ether_addr(addr->sa_data))
3001 return -EADDRNOTAVAIL;
3002
3003 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3004 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3005 dev->dev_addr, ETH_ALEN);
3006 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3007 dev->dev_addr, ETH_ALEN);
3008
3009 /* virtual address for data */
3010 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3011
3012 /* physical address: used for pause frames */
3013 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3014
3015 return 0;
3016 }
3017
3018 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3019 {
3020 u32 bit;
3021
3022 bit = ether_crc(ETH_ALEN, addr) & 63;
3023 filter[bit >> 3] |= 1 << (bit & 7);
3024 }
3025
3026 static void sky2_set_multicast(struct net_device *dev)
3027 {
3028 struct sky2_port *sky2 = netdev_priv(dev);
3029 struct sky2_hw *hw = sky2->hw;
3030 unsigned port = sky2->port;
3031 struct dev_mc_list *list = dev->mc_list;
3032 u16 reg;
3033 u8 filter[8];
3034 int rx_pause;
3035 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3036
3037 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3038 memset(filter, 0, sizeof(filter));
3039
3040 reg = gma_read16(hw, port, GM_RX_CTRL);
3041 reg |= GM_RXCR_UCF_ENA;
3042
3043 if (dev->flags & IFF_PROMISC) /* promiscuous */
3044 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3045 else if (dev->flags & IFF_ALLMULTI)
3046 memset(filter, 0xff, sizeof(filter));
3047 else if (dev->mc_count == 0 && !rx_pause)
3048 reg &= ~GM_RXCR_MCF_ENA;
3049 else {
3050 int i;
3051 reg |= GM_RXCR_MCF_ENA;
3052
3053 if (rx_pause)
3054 sky2_add_filter(filter, pause_mc_addr);
3055
3056 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3057 sky2_add_filter(filter, list->dmi_addr);
3058 }
3059
3060 gma_write16(hw, port, GM_MC_ADDR_H1,
3061 (u16) filter[0] | ((u16) filter[1] << 8));
3062 gma_write16(hw, port, GM_MC_ADDR_H2,
3063 (u16) filter[2] | ((u16) filter[3] << 8));
3064 gma_write16(hw, port, GM_MC_ADDR_H3,
3065 (u16) filter[4] | ((u16) filter[5] << 8));
3066 gma_write16(hw, port, GM_MC_ADDR_H4,
3067 (u16) filter[6] | ((u16) filter[7] << 8));
3068
3069 gma_write16(hw, port, GM_RX_CTRL, reg);
3070 }
3071
3072 /* Can have one global because blinking is controlled by
3073 * ethtool and that is always under RTNL mutex
3074 */
3075 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3076 {
3077 u16 pg;
3078
3079 switch (hw->chip_id) {
3080 case CHIP_ID_YUKON_XL:
3081 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3082 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3083 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3084 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3085 PHY_M_LEDC_INIT_CTRL(7) |
3086 PHY_M_LEDC_STA1_CTRL(7) |
3087 PHY_M_LEDC_STA0_CTRL(7))
3088 : 0);
3089
3090 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3091 break;
3092
3093 default:
3094 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3095 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3096 on ? PHY_M_LED_ALL : 0);
3097 }
3098 }
3099
3100 /* blink LED's for finding board */
3101 static int sky2_phys_id(struct net_device *dev, u32 data)
3102 {
3103 struct sky2_port *sky2 = netdev_priv(dev);
3104 struct sky2_hw *hw = sky2->hw;
3105 unsigned port = sky2->port;
3106 u16 ledctrl, ledover = 0;
3107 long ms;
3108 int interrupted;
3109 int onoff = 1;
3110
3111 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3112 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3113 else
3114 ms = data * 1000;
3115
3116 /* save initial values */
3117 spin_lock_bh(&sky2->phy_lock);
3118 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3119 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3120 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3121 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3122 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3123 } else {
3124 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3125 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3126 }
3127
3128 interrupted = 0;
3129 while (!interrupted && ms > 0) {
3130 sky2_led(hw, port, onoff);
3131 onoff = !onoff;
3132
3133 spin_unlock_bh(&sky2->phy_lock);
3134 interrupted = msleep_interruptible(250);
3135 spin_lock_bh(&sky2->phy_lock);
3136
3137 ms -= 250;
3138 }
3139
3140 /* resume regularly scheduled programming */
3141 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3142 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3143 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3144 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3145 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3146 } else {
3147 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3148 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3149 }
3150 spin_unlock_bh(&sky2->phy_lock);
3151
3152 return 0;
3153 }
3154
3155 static void sky2_get_pauseparam(struct net_device *dev,
3156 struct ethtool_pauseparam *ecmd)
3157 {
3158 struct sky2_port *sky2 = netdev_priv(dev);
3159
3160 switch (sky2->flow_mode) {
3161 case FC_NONE:
3162 ecmd->tx_pause = ecmd->rx_pause = 0;
3163 break;
3164 case FC_TX:
3165 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3166 break;
3167 case FC_RX:
3168 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3169 break;
3170 case FC_BOTH:
3171 ecmd->tx_pause = ecmd->rx_pause = 1;
3172 }
3173
3174 ecmd->autoneg = sky2->autoneg;
3175 }
3176
3177 static int sky2_set_pauseparam(struct net_device *dev,
3178 struct ethtool_pauseparam *ecmd)
3179 {
3180 struct sky2_port *sky2 = netdev_priv(dev);
3181
3182 sky2->autoneg = ecmd->autoneg;
3183 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3184
3185 if (netif_running(dev))
3186 sky2_phy_reinit(sky2);
3187
3188 return 0;
3189 }
3190
3191 static int sky2_get_coalesce(struct net_device *dev,
3192 struct ethtool_coalesce *ecmd)
3193 {
3194 struct sky2_port *sky2 = netdev_priv(dev);
3195 struct sky2_hw *hw = sky2->hw;
3196
3197 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3198 ecmd->tx_coalesce_usecs = 0;
3199 else {
3200 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3201 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3202 }
3203 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3204
3205 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3206 ecmd->rx_coalesce_usecs = 0;
3207 else {
3208 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3209 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3210 }
3211 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3212
3213 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3214 ecmd->rx_coalesce_usecs_irq = 0;
3215 else {
3216 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3217 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3218 }
3219
3220 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3221
3222 return 0;
3223 }
3224
3225 /* Note: this affect both ports */
3226 static int sky2_set_coalesce(struct net_device *dev,
3227 struct ethtool_coalesce *ecmd)
3228 {
3229 struct sky2_port *sky2 = netdev_priv(dev);
3230 struct sky2_hw *hw = sky2->hw;
3231 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3232
3233 if (ecmd->tx_coalesce_usecs > tmax ||
3234 ecmd->rx_coalesce_usecs > tmax ||
3235 ecmd->rx_coalesce_usecs_irq > tmax)
3236 return -EINVAL;
3237
3238 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3239 return -EINVAL;
3240 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3241 return -EINVAL;
3242 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3243 return -EINVAL;
3244
3245 if (ecmd->tx_coalesce_usecs == 0)
3246 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3247 else {
3248 sky2_write32(hw, STAT_TX_TIMER_INI,
3249 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3250 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3251 }
3252 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3253
3254 if (ecmd->rx_coalesce_usecs == 0)
3255 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3256 else {
3257 sky2_write32(hw, STAT_LEV_TIMER_INI,
3258 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3259 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3260 }
3261 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3262
3263 if (ecmd->rx_coalesce_usecs_irq == 0)
3264 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3265 else {
3266 sky2_write32(hw, STAT_ISR_TIMER_INI,
3267 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3268 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3269 }
3270 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3271 return 0;
3272 }
3273
3274 static void sky2_get_ringparam(struct net_device *dev,
3275 struct ethtool_ringparam *ering)
3276 {
3277 struct sky2_port *sky2 = netdev_priv(dev);
3278
3279 ering->rx_max_pending = RX_MAX_PENDING;
3280 ering->rx_mini_max_pending = 0;
3281 ering->rx_jumbo_max_pending = 0;
3282 ering->tx_max_pending = TX_RING_SIZE - 1;
3283
3284 ering->rx_pending = sky2->rx_pending;
3285 ering->rx_mini_pending = 0;
3286 ering->rx_jumbo_pending = 0;
3287 ering->tx_pending = sky2->tx_pending;
3288 }
3289
3290 static int sky2_set_ringparam(struct net_device *dev,
3291 struct ethtool_ringparam *ering)
3292 {
3293 struct sky2_port *sky2 = netdev_priv(dev);
3294 int err = 0;
3295
3296 if (ering->rx_pending > RX_MAX_PENDING ||
3297 ering->rx_pending < 8 ||
3298 ering->tx_pending < MAX_SKB_TX_LE ||
3299 ering->tx_pending > TX_RING_SIZE - 1)
3300 return -EINVAL;
3301
3302 if (netif_running(dev))
3303 sky2_down(dev);
3304
3305 sky2->rx_pending = ering->rx_pending;
3306 sky2->tx_pending = ering->tx_pending;
3307
3308 if (netif_running(dev)) {
3309 err = sky2_up(dev);
3310 if (err)
3311 dev_close(dev);
3312 else
3313 sky2_set_multicast(dev);
3314 }
3315
3316 return err;
3317 }
3318
3319 static int sky2_get_regs_len(struct net_device *dev)
3320 {
3321 return 0x4000;
3322 }
3323
3324 /*
3325 * Returns copy of control register region
3326 * Note: access to the RAM address register set will cause timeouts.
3327 */
3328 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3329 void *p)
3330 {
3331 const struct sky2_port *sky2 = netdev_priv(dev);
3332 const void __iomem *io = sky2->hw->regs;
3333
3334 BUG_ON(regs->len < B3_RI_WTO_R1);
3335 regs->version = 1;
3336 memset(p, 0, regs->len);
3337
3338 memcpy_fromio(p, io, B3_RAM_ADDR);
3339
3340 memcpy_fromio(p + B3_RI_WTO_R1,
3341 io + B3_RI_WTO_R1,
3342 regs->len - B3_RI_WTO_R1);
3343 }
3344
3345 /* In order to do Jumbo packets on these chips, need to turn off the
3346 * transmit store/forward. Therefore checksum offload won't work.
3347 */
3348 static int no_tx_offload(struct net_device *dev)
3349 {
3350 const struct sky2_port *sky2 = netdev_priv(dev);
3351 const struct sky2_hw *hw = sky2->hw;
3352
3353 return dev->mtu > ETH_DATA_LEN &&
3354 (hw->chip_id == CHIP_ID_YUKON_EX
3355 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3356 }
3357
3358 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3359 {
3360 if (data && no_tx_offload(dev))
3361 return -EINVAL;
3362
3363 return ethtool_op_set_tx_csum(dev, data);
3364 }
3365
3366
3367 static int sky2_set_tso(struct net_device *dev, u32 data)
3368 {
3369 if (data && no_tx_offload(dev))
3370 return -EINVAL;
3371
3372 return ethtool_op_set_tso(dev, data);
3373 }
3374
3375 static const struct ethtool_ops sky2_ethtool_ops = {
3376 .get_settings = sky2_get_settings,
3377 .set_settings = sky2_set_settings,
3378 .get_drvinfo = sky2_get_drvinfo,
3379 .get_wol = sky2_get_wol,
3380 .set_wol = sky2_set_wol,
3381 .get_msglevel = sky2_get_msglevel,
3382 .set_msglevel = sky2_set_msglevel,
3383 .nway_reset = sky2_nway_reset,
3384 .get_regs_len = sky2_get_regs_len,
3385 .get_regs = sky2_get_regs,
3386 .get_link = ethtool_op_get_link,
3387 .get_sg = ethtool_op_get_sg,
3388 .set_sg = ethtool_op_set_sg,
3389 .get_tx_csum = ethtool_op_get_tx_csum,
3390 .set_tx_csum = sky2_set_tx_csum,
3391 .get_tso = ethtool_op_get_tso,
3392 .set_tso = sky2_set_tso,
3393 .get_rx_csum = sky2_get_rx_csum,
3394 .set_rx_csum = sky2_set_rx_csum,
3395 .get_strings = sky2_get_strings,
3396 .get_coalesce = sky2_get_coalesce,
3397 .set_coalesce = sky2_set_coalesce,
3398 .get_ringparam = sky2_get_ringparam,
3399 .set_ringparam = sky2_set_ringparam,
3400 .get_pauseparam = sky2_get_pauseparam,
3401 .set_pauseparam = sky2_set_pauseparam,
3402 .phys_id = sky2_phys_id,
3403 .get_stats_count = sky2_get_stats_count,
3404 .get_ethtool_stats = sky2_get_ethtool_stats,
3405 .get_perm_addr = ethtool_op_get_perm_addr,
3406 };
3407
3408 /* Initialize network device */
3409 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3410 unsigned port,
3411 int highmem, int wol)
3412 {
3413 struct sky2_port *sky2;
3414 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3415
3416 if (!dev) {
3417 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3418 return NULL;
3419 }
3420
3421 SET_MODULE_OWNER(dev);
3422 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3423 dev->irq = hw->pdev->irq;
3424 dev->open = sky2_up;
3425 dev->stop = sky2_down;
3426 dev->do_ioctl = sky2_ioctl;
3427 dev->hard_start_xmit = sky2_xmit_frame;
3428 dev->get_stats = sky2_get_stats;
3429 dev->set_multicast_list = sky2_set_multicast;
3430 dev->set_mac_address = sky2_set_mac_address;
3431 dev->change_mtu = sky2_change_mtu;
3432 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3433 dev->tx_timeout = sky2_tx_timeout;
3434 dev->watchdog_timeo = TX_WATCHDOG;
3435 if (port == 0)
3436 dev->poll = sky2_poll;
3437 dev->weight = NAPI_WEIGHT;
3438 #ifdef CONFIG_NET_POLL_CONTROLLER
3439 /* Network console (only works on port 0)
3440 * because netpoll makes assumptions about NAPI
3441 */
3442 if (port == 0)
3443 dev->poll_controller = sky2_netpoll;
3444 #endif
3445
3446 sky2 = netdev_priv(dev);
3447 sky2->netdev = dev;
3448 sky2->hw = hw;
3449 sky2->msg_enable = netif_msg_init(debug, default_msg);
3450
3451 /* Auto speed and flow control */
3452 sky2->autoneg = AUTONEG_ENABLE;
3453 sky2->flow_mode = FC_BOTH;
3454
3455 sky2->duplex = -1;
3456 sky2->speed = -1;
3457 sky2->advertising = sky2_supported_modes(hw);
3458 sky2->rx_csum = 1;
3459 sky2->wol = wol;
3460
3461 spin_lock_init(&sky2->phy_lock);
3462 sky2->tx_pending = TX_DEF_PENDING;
3463 sky2->rx_pending = RX_DEF_PENDING;
3464
3465 hw->dev[port] = dev;
3466
3467 sky2->port = port;
3468
3469 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3470 if (highmem)
3471 dev->features |= NETIF_F_HIGHDMA;
3472
3473 #ifdef SKY2_VLAN_TAG_USED
3474 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3475 dev->vlan_rx_register = sky2_vlan_rx_register;
3476 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3477 #endif
3478
3479 /* read the mac address */
3480 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3481 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3482
3483 /* device is off until link detection */
3484 netif_carrier_off(dev);
3485 netif_stop_queue(dev);
3486
3487 return dev;
3488 }
3489
3490 static void __devinit sky2_show_addr(struct net_device *dev)
3491 {
3492 const struct sky2_port *sky2 = netdev_priv(dev);
3493
3494 if (netif_msg_probe(sky2))
3495 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3496 dev->name,
3497 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3498 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3499 }
3500
3501 /* Handle software interrupt used during MSI test */
3502 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3503 {
3504 struct sky2_hw *hw = dev_id;
3505 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3506
3507 if (status == 0)
3508 return IRQ_NONE;
3509
3510 if (status & Y2_IS_IRQ_SW) {
3511 hw->msi = 1;
3512 wake_up(&hw->msi_wait);
3513 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3514 }
3515 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3516
3517 return IRQ_HANDLED;
3518 }
3519
3520 /* Test interrupt path by forcing a a software IRQ */
3521 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3522 {
3523 struct pci_dev *pdev = hw->pdev;
3524 int err;
3525
3526 init_waitqueue_head (&hw->msi_wait);
3527
3528 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3529
3530 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3531 if (err) {
3532 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3533 return err;
3534 }
3535
3536 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3537 sky2_read8(hw, B0_CTST);
3538
3539 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3540
3541 if (!hw->msi) {
3542 /* MSI test failed, go back to INTx mode */
3543 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3544 "switching to INTx mode.\n");
3545
3546 err = -EOPNOTSUPP;
3547 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3548 }
3549
3550 sky2_write32(hw, B0_IMSK, 0);
3551 sky2_read32(hw, B0_IMSK);
3552
3553 free_irq(pdev->irq, hw);
3554
3555 return err;
3556 }
3557
3558 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3559 {
3560 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3561 u16 value;
3562
3563 if (!pm)
3564 return 0;
3565 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3566 return 0;
3567 return value & PCI_PM_CTRL_PME_ENABLE;
3568 }
3569
3570 static int __devinit sky2_probe(struct pci_dev *pdev,
3571 const struct pci_device_id *ent)
3572 {
3573 struct net_device *dev;
3574 struct sky2_hw *hw;
3575 int err, using_dac = 0, wol_default;
3576
3577 err = pci_enable_device(pdev);
3578 if (err) {
3579 dev_err(&pdev->dev, "cannot enable PCI device\n");
3580 goto err_out;
3581 }
3582
3583 err = pci_request_regions(pdev, DRV_NAME);
3584 if (err) {
3585 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3586 goto err_out;
3587 }
3588
3589 pci_set_master(pdev);
3590
3591 if (sizeof(dma_addr_t) > sizeof(u32) &&
3592 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3593 using_dac = 1;
3594 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3595 if (err < 0) {
3596 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3597 "for consistent allocations\n");
3598 goto err_out_free_regions;
3599 }
3600 } else {
3601 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3602 if (err) {
3603 dev_err(&pdev->dev, "no usable DMA configuration\n");
3604 goto err_out_free_regions;
3605 }
3606 }
3607
3608 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3609
3610 err = -ENOMEM;
3611 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3612 if (!hw) {
3613 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3614 goto err_out_free_regions;
3615 }
3616
3617 hw->pdev = pdev;
3618
3619 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3620 if (!hw->regs) {
3621 dev_err(&pdev->dev, "cannot map device registers\n");
3622 goto err_out_free_hw;
3623 }
3624
3625 #ifdef __BIG_ENDIAN
3626 /* The sk98lin vendor driver uses hardware byte swapping but
3627 * this driver uses software swapping.
3628 */
3629 {
3630 u32 reg;
3631 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3632 reg &= ~PCI_REV_DESC;
3633 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3634 }
3635 #endif
3636
3637 /* ring for status responses */
3638 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3639 &hw->st_dma);
3640 if (!hw->st_le)
3641 goto err_out_iounmap;
3642
3643 err = sky2_init(hw);
3644 if (err)
3645 goto err_out_iounmap;
3646
3647 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3648 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3649 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3650 hw->chip_id, hw->chip_rev);
3651
3652 sky2_reset(hw);
3653
3654 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3655 if (!dev) {
3656 err = -ENOMEM;
3657 goto err_out_free_pci;
3658 }
3659
3660 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3661 err = sky2_test_msi(hw);
3662 if (err == -EOPNOTSUPP)
3663 pci_disable_msi(pdev);
3664 else if (err)
3665 goto err_out_free_netdev;
3666 }
3667
3668 err = register_netdev(dev);
3669 if (err) {
3670 dev_err(&pdev->dev, "cannot register net device\n");
3671 goto err_out_free_netdev;
3672 }
3673
3674 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3675 dev->name, hw);
3676 if (err) {
3677 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3678 goto err_out_unregister;
3679 }
3680 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3681
3682 sky2_show_addr(dev);
3683
3684 if (hw->ports > 1) {
3685 struct net_device *dev1;
3686
3687 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3688 if (!dev1)
3689 dev_warn(&pdev->dev, "allocation for second device failed\n");
3690 else if ((err = register_netdev(dev1))) {
3691 dev_warn(&pdev->dev,
3692 "register of second port failed (%d)\n", err);
3693 hw->dev[1] = NULL;
3694 free_netdev(dev1);
3695 } else
3696 sky2_show_addr(dev1);
3697 }
3698
3699 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3700 INIT_WORK(&hw->restart_work, sky2_restart);
3701
3702 sky2_idle_start(hw);
3703
3704 pci_set_drvdata(pdev, hw);
3705
3706 return 0;
3707
3708 err_out_unregister:
3709 if (hw->msi)
3710 pci_disable_msi(pdev);
3711 unregister_netdev(dev);
3712 err_out_free_netdev:
3713 free_netdev(dev);
3714 err_out_free_pci:
3715 sky2_write8(hw, B0_CTST, CS_RST_SET);
3716 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3717 err_out_iounmap:
3718 iounmap(hw->regs);
3719 err_out_free_hw:
3720 kfree(hw);
3721 err_out_free_regions:
3722 pci_release_regions(pdev);
3723 pci_disable_device(pdev);
3724 err_out:
3725 return err;
3726 }
3727
3728 static void __devexit sky2_remove(struct pci_dev *pdev)
3729 {
3730 struct sky2_hw *hw = pci_get_drvdata(pdev);
3731 struct net_device *dev0, *dev1;
3732
3733 if (!hw)
3734 return;
3735
3736 del_timer_sync(&hw->idle_timer);
3737
3738 flush_scheduled_work();
3739
3740 sky2_write32(hw, B0_IMSK, 0);
3741 synchronize_irq(hw->pdev->irq);
3742
3743 dev0 = hw->dev[0];
3744 dev1 = hw->dev[1];
3745 if (dev1)
3746 unregister_netdev(dev1);
3747 unregister_netdev(dev0);
3748
3749 sky2_power_aux(hw);
3750
3751 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3752 sky2_write8(hw, B0_CTST, CS_RST_SET);
3753 sky2_read8(hw, B0_CTST);
3754
3755 free_irq(pdev->irq, hw);
3756 if (hw->msi)
3757 pci_disable_msi(pdev);
3758 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3759 pci_release_regions(pdev);
3760 pci_disable_device(pdev);
3761
3762 if (dev1)
3763 free_netdev(dev1);
3764 free_netdev(dev0);
3765 iounmap(hw->regs);
3766 kfree(hw);
3767
3768 pci_set_drvdata(pdev, NULL);
3769 }
3770
3771 #ifdef CONFIG_PM
3772 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3773 {
3774 struct sky2_hw *hw = pci_get_drvdata(pdev);
3775 int i, wol = 0;
3776
3777 del_timer_sync(&hw->idle_timer);
3778 netif_poll_disable(hw->dev[0]);
3779
3780 for (i = 0; i < hw->ports; i++) {
3781 struct net_device *dev = hw->dev[i];
3782 struct sky2_port *sky2 = netdev_priv(dev);
3783
3784 if (netif_running(dev))
3785 sky2_down(dev);
3786
3787 if (sky2->wol)
3788 sky2_wol_init(sky2);
3789
3790 wol |= sky2->wol;
3791 }
3792
3793 sky2_write32(hw, B0_IMSK, 0);
3794 sky2_power_aux(hw);
3795
3796 pci_save_state(pdev);
3797 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3798 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3799
3800 return 0;
3801 }
3802
3803 static int sky2_resume(struct pci_dev *pdev)
3804 {
3805 struct sky2_hw *hw = pci_get_drvdata(pdev);
3806 int i, err;
3807
3808 err = pci_set_power_state(pdev, PCI_D0);
3809 if (err)
3810 goto out;
3811
3812 err = pci_restore_state(pdev);
3813 if (err)
3814 goto out;
3815
3816 pci_enable_wake(pdev, PCI_D0, 0);
3817
3818 /* Re-enable all clocks */
3819 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3820 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3821
3822 sky2_reset(hw);
3823
3824 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3825
3826 for (i = 0; i < hw->ports; i++) {
3827 struct net_device *dev = hw->dev[i];
3828 if (netif_running(dev)) {
3829 err = sky2_up(dev);
3830 if (err) {
3831 printk(KERN_ERR PFX "%s: could not up: %d\n",
3832 dev->name, err);
3833 dev_close(dev);
3834 goto out;
3835 }
3836 }
3837 }
3838
3839 netif_poll_enable(hw->dev[0]);
3840 sky2_idle_start(hw);
3841 return 0;
3842 out:
3843 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3844 pci_disable_device(pdev);
3845 return err;
3846 }
3847 #endif
3848
3849 static void sky2_shutdown(struct pci_dev *pdev)
3850 {
3851 struct sky2_hw *hw = pci_get_drvdata(pdev);
3852 int i, wol = 0;
3853
3854 del_timer_sync(&hw->idle_timer);
3855 netif_poll_disable(hw->dev[0]);
3856
3857 for (i = 0; i < hw->ports; i++) {
3858 struct net_device *dev = hw->dev[i];
3859 struct sky2_port *sky2 = netdev_priv(dev);
3860
3861 if (sky2->wol) {
3862 wol = 1;
3863 sky2_wol_init(sky2);
3864 }
3865 }
3866
3867 if (wol)
3868 sky2_power_aux(hw);
3869
3870 pci_enable_wake(pdev, PCI_D3hot, wol);
3871 pci_enable_wake(pdev, PCI_D3cold, wol);
3872
3873 pci_disable_device(pdev);
3874 pci_set_power_state(pdev, PCI_D3hot);
3875
3876 }
3877
3878 static struct pci_driver sky2_driver = {
3879 .name = DRV_NAME,
3880 .id_table = sky2_id_table,
3881 .probe = sky2_probe,
3882 .remove = __devexit_p(sky2_remove),
3883 #ifdef CONFIG_PM
3884 .suspend = sky2_suspend,
3885 .resume = sky2_resume,
3886 #endif
3887 .shutdown = sky2_shutdown,
3888 };
3889
3890 static int __init sky2_init_module(void)
3891 {
3892 return pci_register_driver(&sky2_driver);
3893 }
3894
3895 static void __exit sky2_cleanup_module(void)
3896 {
3897 pci_unregister_driver(&sky2_driver);
3898 }
3899
3900 module_init(sky2_init_module);
3901 module_exit(sky2_cleanup_module);
3902
3903 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3904 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3905 MODULE_LICENSE("GPL");
3906 MODULE_VERSION(DRV_VERSION);
linux kernel for loongson