2 * drivers/ata/sata_fsl.c
4 * Freescale 3.0Gbps SATA device driver
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
26 #include <linux/of_platform.h>
28 /* Controller information */
30 SATA_FSL_QUEUE_DEPTH
= 16,
31 SATA_FSL_MAX_PRD
= 63,
32 SATA_FSL_MAX_PRD_USABLE
= SATA_FSL_MAX_PRD
- 1,
33 SATA_FSL_MAX_PRD_DIRECT
= 16, /* Direct PRDT entries */
35 SATA_FSL_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
36 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
39 SATA_FSL_MAX_CMDS
= SATA_FSL_QUEUE_DEPTH
,
40 SATA_FSL_CMD_HDR_SIZE
= 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE
= (SATA_FSL_MAX_CMDS
* SATA_FSL_CMD_HDR_SIZE
),
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contigious) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
53 SATA_FSL_CMD_DESC_CFIS_SZ
= 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ
= 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ
= 16,
56 SATA_FSL_CMD_DESC_RSRVD
= 16,
58 SATA_FSL_CMD_DESC_SIZE
= (SATA_FSL_CMD_DESC_CFIS_SZ
+
59 SATA_FSL_CMD_DESC_SFIS_SZ
+
60 SATA_FSL_CMD_DESC_ACMD_SZ
+
61 SATA_FSL_CMD_DESC_RSRVD
+
62 SATA_FSL_MAX_PRD
* 16),
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
=
65 (SATA_FSL_CMD_DESC_CFIS_SZ
+
66 SATA_FSL_CMD_DESC_SFIS_SZ
+
67 SATA_FSL_CMD_DESC_ACMD_SZ
+
68 SATA_FSL_CMD_DESC_RSRVD
),
70 SATA_FSL_CMD_DESC_AR_SZ
= (SATA_FSL_CMD_DESC_SIZE
* SATA_FSL_MAX_CMDS
),
71 SATA_FSL_PORT_PRIV_DMA_SZ
= (SATA_FSL_CMD_SLOT_SIZE
+
72 SATA_FSL_CMD_DESC_AR_SZ
),
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
80 SATA_FSL_MAX_PORTS
= 1,
82 SATA_FSL_IRQ_FLAG
= IRQF_SHARED
,
86 * Host Controller command register set - per port
102 * Host Status Register (HStatus) bitdefs
105 GOING_OFFLINE
= (1 << 30),
106 BIST_ERR
= (1 << 29),
108 FATAL_ERR_HC_MASTER_ERR
= (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX
= (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX
= (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN
= (1 << 13),
112 FATAL_ERR_DATA_OVERRUN
= (1 << 12),
113 FATAL_ERR_CRC_ERR_TX
= (1 << 11),
114 FATAL_ERR_CRC_ERR_RX
= (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX
= (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX
= (1 << 8),
118 FATAL_ERROR_DECODE
= FATAL_ERR_HC_MASTER_ERR
|
119 FATAL_ERR_PARITY_ERR_TX
|
120 FATAL_ERR_PARITY_ERR_RX
|
121 FATAL_ERR_DATA_UNDERRUN
|
122 FATAL_ERR_DATA_OVERRUN
|
123 FATAL_ERR_CRC_ERR_TX
|
124 FATAL_ERR_CRC_ERR_RX
|
125 FATAL_ERR_FIFO_OVRFL_TX
| FATAL_ERR_FIFO_OVRFL_RX
,
127 INT_ON_FATAL_ERR
= (1 << 5),
128 INT_ON_PHYRDY_CHG
= (1 << 4),
130 INT_ON_SIGNATURE_UPDATE
= (1 << 3),
131 INT_ON_SNOTIFY_UPDATE
= (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR
= (1 << 1),
133 INT_ON_CMD_COMPLETE
= 1,
135 INT_ON_ERROR
= INT_ON_FATAL_ERR
|
136 INT_ON_PHYRDY_CHG
| INT_ON_SINGL_DEVICE_ERR
,
139 * Host Control Register (HControl) bitdefs
141 HCONTROL_ONLINE_PHY_RST
= (1 << 31),
142 HCONTROL_FORCE_OFFLINE
= (1 << 30),
143 HCONTROL_PARITY_PROT_MOD
= (1 << 14),
144 HCONTROL_DPATH_PARITY
= (1 << 12),
145 HCONTROL_SNOOP_ENABLE
= (1 << 10),
146 HCONTROL_PMP_ATTACHED
= (1 << 9),
147 HCONTROL_COPYOUT_STATFIS
= (1 << 8),
148 IE_ON_FATAL_ERR
= (1 << 5),
149 IE_ON_PHYRDY_CHG
= (1 << 4),
150 IE_ON_SIGNATURE_UPDATE
= (1 << 3),
151 IE_ON_SNOTIFY_UPDATE
= (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR
= (1 << 1),
153 IE_ON_CMD_COMPLETE
= 1,
155 DEFAULT_PORT_IRQ_ENABLE_MASK
= IE_ON_FATAL_ERR
| IE_ON_PHYRDY_CHG
|
156 IE_ON_SIGNATURE_UPDATE
|
157 IE_ON_SINGL_DEVICE_ERR
| IE_ON_CMD_COMPLETE
,
159 EXT_INDIRECT_SEG_PRD_FLAG
= (1 << 31),
160 DATA_SNOOP_ENABLE
= (1 << 22),
164 * SATA Superset Registers
174 * Control Status Register Set
188 /* PHY (link-layer) configuration control */
190 PHY_BIST_ENABLE
= 0x01,
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
197 struct cmdhdr_tbl_entry
{
205 * Description information bitdefs
208 VENDOR_SPECIFIC_BIST
= (1 << 10),
209 CMD_DESC_SNOOP_ENABLE
= (1 << 9),
210 FPDMA_QUEUED_CMD
= (1 << 8),
213 ATAPI_CMD
= (1 << 5),
219 struct command_desc
{
224 u32 prdt
[SATA_FSL_MAX_PRD_DIRECT
* 4];
225 u32 prdt_indirect
[(SATA_FSL_MAX_PRD
- SATA_FSL_MAX_PRD_DIRECT
) * 4];
229 * Physical region table descriptor(PRD)
239 * ata_port private data
240 * This is our per-port instance data.
242 struct sata_fsl_port_priv
{
243 struct cmdhdr_tbl_entry
*cmdslot
;
244 dma_addr_t cmdslot_paddr
;
245 struct command_desc
*cmdentry
;
246 dma_addr_t cmdentry_paddr
;
249 * SATA FSL controller has a Status FIS which should contain the
250 * received D2H FIS & taskfile registers. This SFIS is present in
251 * the command descriptor, and to have a ready reference to it,
252 * we are caching it here, quite similar to what is done in H/W on
253 * AHCI compliant devices by copying taskfile fields to a 32-bit
257 struct ata_taskfile tf
;
261 * ata_port->host_set private data
263 struct sata_fsl_host_priv
{
264 void __iomem
*hcr_base
;
265 void __iomem
*ssr_base
;
266 void __iomem
*csr_base
;
270 static inline unsigned int sata_fsl_tag(unsigned int tag
,
271 void __iomem
*hcr_base
)
273 /* We let libATA core do actual (queue) tag allocation */
275 /* all non NCQ/queued commands should have tag#0 */
276 if (ata_tag_internal(tag
)) {
277 DPRINTK("mapping internal cmds to tag#0\n");
281 if (unlikely(tag
>= SATA_FSL_QUEUE_DEPTH
)) {
282 DPRINTK("tag %d invalid : out of range\n", tag
);
286 if (unlikely((ioread32(hcr_base
+ CQ
)) & (1 << tag
))) {
287 DPRINTK("tag %d invalid : in use!!\n", tag
);
294 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv
*pp
,
295 unsigned int tag
, u32 desc_info
,
296 u32 data_xfer_len
, u8 num_prde
,
299 dma_addr_t cmd_descriptor_address
;
301 cmd_descriptor_address
= pp
->cmdentry_paddr
+
302 tag
* SATA_FSL_CMD_DESC_SIZE
;
304 /* NOTE: both data_xfer_len & fis_len are Dword counts */
306 pp
->cmdslot
[tag
].cda
= cpu_to_le32(cmd_descriptor_address
);
307 pp
->cmdslot
[tag
].prde_fis_len
=
308 cpu_to_le32((num_prde
<< 16) | (fis_len
<< 2));
309 pp
->cmdslot
[tag
].ttl
= cpu_to_le32(data_xfer_len
& ~0x03);
310 pp
->cmdslot
[tag
].desc_info
= cpu_to_le32(desc_info
| (tag
& 0x1F));
312 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
313 pp
->cmdslot
[tag
].cda
,
314 pp
->cmdslot
[tag
].prde_fis_len
,
315 pp
->cmdslot
[tag
].ttl
, pp
->cmdslot
[tag
].desc_info
);
319 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_desc
,
320 u32
*ttl
, dma_addr_t cmd_desc_paddr
)
322 struct scatterlist
*sg
;
323 unsigned int num_prde
= 0;
327 * NOTE : direct & indirect prdt's are contigiously allocated
329 struct prde
*prd
= (struct prde
*)&((struct command_desc
*)
332 struct prde
*prd_ptr_to_indirect_ext
= NULL
;
333 unsigned indirect_ext_segment_sz
= 0;
334 dma_addr_t indirect_ext_segment_paddr
;
337 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc
, prd
);
339 indirect_ext_segment_paddr
= cmd_desc_paddr
+
340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
+ SATA_FSL_MAX_PRD_DIRECT
* 16;
342 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
343 dma_addr_t sg_addr
= sg_dma_address(sg
);
344 u32 sg_len
= sg_dma_len(sg
);
346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
349 /* warn if each s/g element is not dword aligned */
351 ata_port_printk(qc
->ap
, KERN_ERR
,
352 "s/g addr unaligned : 0x%x\n", sg_addr
);
354 ata_port_printk(qc
->ap
, KERN_ERR
,
355 "s/g len unaligned : 0x%x\n", sg_len
);
357 if (num_prde
== (SATA_FSL_MAX_PRD_DIRECT
- 1) &&
358 sg_next(sg
) != NULL
) {
359 VPRINTK("setting indirect prde\n");
360 prd_ptr_to_indirect_ext
= prd
;
361 prd
->dba
= cpu_to_le32(indirect_ext_segment_paddr
);
362 indirect_ext_segment_sz
= 0;
367 ttl_dwords
+= sg_len
;
368 prd
->dba
= cpu_to_le32(sg_addr
);
370 cpu_to_le32(DATA_SNOOP_ENABLE
| (sg_len
& ~0x03));
372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
373 ttl_dwords
, prd
->dba
, prd
->ddc_and_ext
);
377 if (prd_ptr_to_indirect_ext
)
378 indirect_ext_segment_sz
+= sg_len
;
381 if (prd_ptr_to_indirect_ext
) {
382 /* set indirect extension flag along with indirect ext. size */
383 prd_ptr_to_indirect_ext
->ddc_and_ext
=
384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG
|
386 (indirect_ext_segment_sz
& ~0x03)));
393 static void sata_fsl_qc_prep(struct ata_queued_cmd
*qc
)
395 struct ata_port
*ap
= qc
->ap
;
396 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
397 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
398 void __iomem
*hcr_base
= host_priv
->hcr_base
;
399 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
400 struct command_desc
*cd
;
401 u32 desc_info
= CMD_DESC_SNOOP_ENABLE
;
406 cd
= (struct command_desc
*)pp
->cmdentry
+ tag
;
407 cd_paddr
= pp
->cmdentry_paddr
+ tag
* SATA_FSL_CMD_DESC_SIZE
;
409 ata_tf_to_fis(&qc
->tf
, 0, 1, (u8
*) &cd
->cfis
);
411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
412 cd
->cfis
[0], cd
->cfis
[1], cd
->cfis
[2]);
414 if (qc
->tf
.protocol
== ATA_PROT_NCQ
) {
415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
416 cd
->cfis
[3], cd
->cfis
[11]);
419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
420 if (ata_is_atapi(qc
->tf
.protocol
)) {
421 desc_info
|= ATAPI_CMD
;
422 memset((void *)&cd
->acmd
, 0, 32);
423 memcpy((void *)&cd
->acmd
, qc
->cdb
, qc
->dev
->cdb_len
);
426 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
427 num_prde
= sata_fsl_fill_sg(qc
, (void *)cd
,
428 &ttl_dwords
, cd_paddr
);
430 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
431 desc_info
|= FPDMA_QUEUED_CMD
;
433 sata_fsl_setup_cmd_hdr_entry(pp
, tag
, desc_info
, ttl_dwords
,
436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
437 desc_info
, ttl_dwords
, num_prde
);
440 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd
*qc
)
442 struct ata_port
*ap
= qc
->ap
;
443 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
444 void __iomem
*hcr_base
= host_priv
->hcr_base
;
445 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
448 ioread32(CQ
+ hcr_base
),
449 ioread32(CA
+ hcr_base
),
450 ioread32(CE
+ hcr_base
), ioread32(CC
+ hcr_base
));
452 /* Simply queue command to the controller/device */
453 iowrite32(1 << tag
, CQ
+ hcr_base
);
455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
456 tag
, ioread32(CQ
+ hcr_base
), ioread32(CA
+ hcr_base
));
458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
459 ioread32(CE
+ hcr_base
),
460 ioread32(DE
+ hcr_base
),
461 ioread32(CC
+ hcr_base
),
462 ioread32(COMMANDSTAT
+ host_priv
->csr_base
));
467 static int sata_fsl_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
,
470 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
471 void __iomem
*ssr_base
= host_priv
->ssr_base
;
485 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg
);
487 iowrite32(val
, ssr_base
+ (sc_reg
* 4));
491 static int sata_fsl_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
,
494 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
495 void __iomem
*ssr_base
= host_priv
->ssr_base
;
509 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg
);
511 *val
= ioread32(ssr_base
+ (sc_reg
* 4));
515 static void sata_fsl_freeze(struct ata_port
*ap
)
517 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
518 void __iomem
*hcr_base
= host_priv
->hcr_base
;
521 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
522 ioread32(CQ
+ hcr_base
),
523 ioread32(CA
+ hcr_base
),
524 ioread32(CE
+ hcr_base
), ioread32(DE
+ hcr_base
));
525 VPRINTK("CmdStat = 0x%x\n",
526 ioread32(host_priv
->csr_base
+ COMMANDSTAT
));
528 /* disable interrupts on the controller/port */
529 temp
= ioread32(hcr_base
+ HCONTROL
);
530 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
532 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
533 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
536 static void sata_fsl_thaw(struct ata_port
*ap
)
538 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
539 void __iomem
*hcr_base
= host_priv
->hcr_base
;
542 /* ack. any pending IRQs for this controller/port */
543 temp
= ioread32(hcr_base
+ HSTATUS
);
545 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp
& 0x3F));
548 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
550 /* enable interrupts on the controller/port */
551 temp
= ioread32(hcr_base
+ HCONTROL
);
552 iowrite32((temp
| DEFAULT_PORT_IRQ_ENABLE_MASK
), hcr_base
+ HCONTROL
);
554 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
555 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
559 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
561 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
565 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
566 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
567 void __iomem
*hcr_base
= host_priv
->hcr_base
;
568 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
569 struct command_desc
*cd
;
571 cd
= pp
->cmdentry
+ tag
;
573 ata_tf_from_fis(cd
->sfis
, &pp
->tf
);
576 static u8
sata_fsl_check_status(struct ata_port
*ap
)
578 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
580 return pp
->tf
.command
;
583 static void sata_fsl_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
585 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
590 static int sata_fsl_port_start(struct ata_port
*ap
)
592 struct device
*dev
= ap
->host
->dev
;
593 struct sata_fsl_port_priv
*pp
;
597 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
598 void __iomem
*hcr_base
= host_priv
->hcr_base
;
601 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
605 mem
= dma_alloc_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
, &mem_dma
,
611 memset(mem
, 0, SATA_FSL_PORT_PRIV_DMA_SZ
);
614 pp
->cmdslot_paddr
= mem_dma
;
616 mem
+= SATA_FSL_CMD_SLOT_SIZE
;
617 mem_dma
+= SATA_FSL_CMD_SLOT_SIZE
;
620 pp
->cmdentry_paddr
= mem_dma
;
622 ap
->private_data
= pp
;
624 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
625 pp
->cmdslot_paddr
, pp
->cmdentry_paddr
);
627 /* Now, update the CHBA register in host controller cmd register set */
628 iowrite32(pp
->cmdslot_paddr
& 0xffffffff, hcr_base
+ CHBA
);
631 * Now, we can bring the controller on-line & also initiate
632 * the COMINIT sequence, we simply return here and the boot-probing
633 * & device discovery process is re-initiated by libATA using a
634 * Softreset EH (dummy) session. Hence, boot probing and device
635 * discovey will be part of sata_fsl_softreset() callback.
638 temp
= ioread32(hcr_base
+ HCONTROL
);
639 iowrite32((temp
| HCONTROL_ONLINE_PHY_RST
), hcr_base
+ HCONTROL
);
641 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
642 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
643 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base
+ CHBA
));
645 #ifdef CONFIG_MPC8315_DS
647 * Workaround for 8315DS board 3gbps link-up issue,
648 * currently limit SATA port to GEN1 speed
650 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
653 sata_fsl_scr_write(ap
, SCR_CONTROL
, temp
);
655 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
656 dev_printk(KERN_WARNING
, dev
, "scr_control, speed limited to %x\n",
663 static void sata_fsl_port_stop(struct ata_port
*ap
)
665 struct device
*dev
= ap
->host
->dev
;
666 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
667 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
668 void __iomem
*hcr_base
= host_priv
->hcr_base
;
672 * Force host controller to go off-line, aborting current operations
674 temp
= ioread32(hcr_base
+ HCONTROL
);
675 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
676 temp
|= HCONTROL_FORCE_OFFLINE
;
677 iowrite32(temp
, hcr_base
+ HCONTROL
);
679 /* Poll for controller to go offline - should happen immediately */
680 ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 1);
682 ap
->private_data
= NULL
;
683 dma_free_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
,
684 pp
->cmdslot
, pp
->cmdslot_paddr
);
689 static unsigned int sata_fsl_dev_classify(struct ata_port
*ap
)
691 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
692 void __iomem
*hcr_base
= host_priv
->hcr_base
;
693 struct ata_taskfile tf
;
696 temp
= ioread32(hcr_base
+ SIGNATURE
);
698 VPRINTK("raw sig = 0x%x\n", temp
);
699 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
700 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
702 tf
.lbah
= (temp
>> 24) & 0xff;
703 tf
.lbam
= (temp
>> 16) & 0xff;
704 tf
.lbal
= (temp
>> 8) & 0xff;
705 tf
.nsect
= temp
& 0xff;
707 return ata_dev_classify(&tf
);
710 static int sata_fsl_softreset(struct ata_link
*link
, unsigned int *class,
711 unsigned long deadline
)
713 struct ata_port
*ap
= link
->ap
;
714 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
715 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
716 void __iomem
*hcr_base
= host_priv
->hcr_base
;
718 struct ata_taskfile tf
;
722 unsigned long start_jiffies
;
724 DPRINTK("in xx_softreset\n");
728 * Force host controller to go off-line, aborting current operations
730 temp
= ioread32(hcr_base
+ HCONTROL
);
731 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
732 iowrite32(temp
, hcr_base
+ HCONTROL
);
734 /* Poll for controller to go offline */
735 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 500);
738 ata_port_printk(ap
, KERN_ERR
,
739 "Softreset failed, not off-lined %d\n", i
);
742 * Try to offline controller atleast twice
748 goto try_offline_again
;
751 DPRINTK("softreset, controller off-lined\n");
752 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
753 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
756 * PHY reset should remain asserted for atleast 1ms
761 * Now, bring the host controller online again, this can take time
762 * as PHY reset and communication establishment, 1st D2H FIS and
763 * device signature update is done, on safe side assume 500ms
764 * NOTE : Host online status may be indicated immediately!!
767 temp
= ioread32(hcr_base
+ HCONTROL
);
768 temp
|= (HCONTROL_ONLINE_PHY_RST
| HCONTROL_SNOOP_ENABLE
);
769 iowrite32(temp
, hcr_base
+ HCONTROL
);
771 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, 0, 1, 500);
773 if (!(temp
& ONLINE
)) {
774 ata_port_printk(ap
, KERN_ERR
,
775 "Softreset failed, not on-lined\n");
779 DPRINTK("softreset, controller off-lined & on-lined\n");
780 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
781 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
784 * First, wait for the PHYRDY change to occur before waiting for
785 * the signature, and also verify if SStatus indicates device
789 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0, 1, 500);
790 if ((!(temp
& 0x10)) || ata_link_offline(link
)) {
791 ata_port_printk(ap
, KERN_WARNING
,
792 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
793 ioread32(hcr_base
+ HSTATUS
));
798 * Wait for the first D2H from device,i.e,signature update notification
800 start_jiffies
= jiffies
;
801 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0x10,
802 500, jiffies_to_msecs(deadline
- start_jiffies
));
804 if ((temp
& 0xFF) != 0x18) {
805 ata_port_printk(ap
, KERN_WARNING
, "No Signature Update\n");
808 ata_port_printk(ap
, KERN_INFO
,
809 "Signature Update detected @ %d msecs\n",
810 jiffies_to_msecs(jiffies
- start_jiffies
));
814 * Send a device reset (SRST) explicitly on command slot #0
815 * Check : will the command queue (reg) be cleared during offlining ??
816 * Also we will be online only if Phy commn. has been established
817 * and device presence has been detected, therefore if we have
818 * reached here, we can send a command to the target device
821 DPRINTK("Sending SRST/device reset\n");
823 ata_tf_init(link
->device
, &tf
);
824 cfis
= (u8
*) &pp
->cmdentry
->cfis
;
826 /* device reset/SRST is a control register update FIS, uses tag0 */
827 sata_fsl_setup_cmd_hdr_entry(pp
, 0,
828 SRST_CMD
| CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
830 tf
.ctl
|= ATA_SRST
; /* setup SRST bit in taskfile control reg */
831 ata_tf_to_fis(&tf
, 0, 0, cfis
);
833 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
834 cfis
[0], cfis
[1], cfis
[2], cfis
[3]);
837 * Queue SRST command to the controller/device, ensure that no
838 * other commands are active on the controller/device
841 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
842 ioread32(CQ
+ hcr_base
),
843 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
845 iowrite32(0xFFFF, CC
+ hcr_base
);
846 iowrite32(1, CQ
+ hcr_base
);
848 temp
= ata_wait_register(CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
850 ata_port_printk(ap
, KERN_WARNING
, "ATA_SRST issue failed\n");
852 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
853 ioread32(CQ
+ hcr_base
),
854 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
856 sata_fsl_scr_read(ap
, SCR_ERROR
, &Serror
);
858 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
859 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
860 DPRINTK("Serror = 0x%x\n", Serror
);
867 * SATA device enters reset state after receving a Control register
868 * FIS with SRST bit asserted and it awaits another H2D Control reg.
869 * FIS with SRST bit cleared, then the device does internal diags &
870 * initialization, followed by indicating it's initialization status
871 * using ATA signature D2H register FIS to the host controller.
874 sata_fsl_setup_cmd_hdr_entry(pp
, 0, CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
876 tf
.ctl
&= ~ATA_SRST
; /* 2nd H2D Ctl. register FIS */
877 ata_tf_to_fis(&tf
, 0, 0, cfis
);
879 iowrite32(1, CQ
+ hcr_base
);
880 msleep(150); /* ?? */
883 * The above command would have signalled an interrupt on command
884 * complete, which needs special handling, by clearing the Nth
885 * command bit of the CCreg
887 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
889 DPRINTK("SATA FSL : Now checking device signature\n");
891 *class = ATA_DEV_NONE
;
893 /* Verify if SStatus indicates device presence */
894 if (ata_link_online(link
)) {
896 * if we are here, device presence has been detected,
897 * 1st D2H FIS would have been received, but sfis in
898 * command desc. is not updated, but signature register
899 * would have been updated
902 *class = sata_fsl_dev_classify(ap
);
904 DPRINTK("class = %d\n", *class);
905 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base
+ CC
));
906 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base
+ CE
));
915 static void sata_fsl_error_handler(struct ata_port
*ap
)
918 DPRINTK("in xx_error_handler\n");
920 /* perform recovery */
921 ata_do_eh(ap
, ata_std_prereset
, sata_fsl_softreset
, sata_std_hardreset
,
925 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd
*qc
)
927 if (qc
->flags
& ATA_QCFLAG_FAILED
)
928 qc
->err_mask
|= AC_ERR_OTHER
;
931 /* make DMA engine forget about the failed command */
936 static void sata_fsl_error_intr(struct ata_port
*ap
)
938 struct ata_link
*link
= &ap
->link
;
939 struct ata_eh_info
*ehi
= &link
->eh_info
;
940 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
941 void __iomem
*hcr_base
= host_priv
->hcr_base
;
942 u32 hstatus
, dereg
, cereg
= 0, SError
= 0;
943 unsigned int err_mask
= 0, action
= 0;
944 struct ata_queued_cmd
*qc
;
947 hstatus
= ioread32(hcr_base
+ HSTATUS
);
948 cereg
= ioread32(hcr_base
+ CE
);
950 ata_ehi_clear_desc(ehi
);
953 * Handle & Clear SError
956 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
957 if (unlikely(SError
& 0xFFFF0000)) {
958 sata_fsl_scr_write(ap
, SCR_ERROR
, SError
);
959 err_mask
|= AC_ERR_ATA_BUS
;
962 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
963 hstatus
, cereg
, ioread32(hcr_base
+ DE
), SError
);
965 /* handle single device errors */
968 * clear the command error, also clears queue to the device
969 * in error, and we can (re)issue commands to this device.
970 * When a device is in error all commands queued into the
971 * host controller and at the device are considered aborted
972 * and the queue for that device is stopped. Now, after
973 * clearing the device error, we can issue commands to the
974 * device to interrogate it to find the source of the error.
976 dereg
= ioread32(hcr_base
+ DE
);
977 iowrite32(dereg
, hcr_base
+ DE
);
978 iowrite32(cereg
, hcr_base
+ CE
);
980 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
981 ioread32(hcr_base
+ CE
), ioread32(hcr_base
+ DE
));
983 * We should consider this as non fatal error, and TF must
984 * be updated as done below.
987 err_mask
|= AC_ERR_DEV
;
990 /* handle fatal errors */
991 if (hstatus
& FATAL_ERROR_DECODE
) {
992 err_mask
|= AC_ERR_ATA_BUS
;
993 action
|= ATA_EH_RESET
;
994 /* how will fatal error interrupts be completed ?? */
998 /* Handle PHYRDY change notification */
999 if (hstatus
& INT_ON_PHYRDY_CHG
) {
1000 DPRINTK("SATA FSL: PHYRDY change indication\n");
1002 /* Setup a soft-reset EH action */
1003 ata_ehi_hotplugged(ehi
);
1007 /* record error info */
1008 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1011 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1012 qc
->err_mask
|= err_mask
;
1014 ehi
->err_mask
|= err_mask
;
1016 ehi
->action
|= action
;
1017 ehi
->serror
|= SError
;
1019 /* freeze or abort */
1021 ata_port_freeze(ap
);
1026 static void sata_fsl_qc_complete(struct ata_queued_cmd
*qc
)
1028 if (qc
->flags
& ATA_QCFLAG_RESULT_TF
) {
1029 DPRINTK("xx_qc_complete called\n");
1030 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1034 static void sata_fsl_host_intr(struct ata_port
*ap
)
1036 struct ata_link
*link
= &ap
->link
;
1037 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1038 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1039 u32 hstatus
, qc_active
= 0;
1040 struct ata_queued_cmd
*qc
;
1043 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1045 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
1047 if (unlikely(SError
& 0xFFFF0000)) {
1048 DPRINTK("serror @host_intr : 0x%x\n", SError
);
1049 sata_fsl_error_intr(ap
);
1053 if (unlikely(hstatus
& INT_ON_ERROR
)) {
1054 DPRINTK("error interrupt!!\n");
1055 sata_fsl_error_intr(ap
);
1059 if (link
->sactive
) { /* only true for NCQ commands */
1061 /* Read command completed register */
1062 qc_active
= ioread32(hcr_base
+ CC
);
1063 /* clear CC bit, this will also complete the interrupt */
1064 iowrite32(qc_active
, hcr_base
+ CC
);
1066 DPRINTK("Status of all queues :\n");
1067 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1068 qc_active
, ioread32(hcr_base
+ CA
),
1069 ioread32(hcr_base
+ CE
));
1071 for (i
= 0; i
< SATA_FSL_QUEUE_DEPTH
; i
++) {
1072 if (qc_active
& (1 << i
)) {
1073 qc
= ata_qc_from_tag(ap
, i
);
1075 sata_fsl_qc_complete(qc
);
1076 ata_qc_complete(qc
);
1079 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1080 i
, ioread32(hcr_base
+ CC
),
1081 ioread32(hcr_base
+ CA
));
1086 } else if (ap
->qc_active
) {
1087 iowrite32(1, hcr_base
+ CC
);
1088 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1090 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1091 link
->active_tag
, ioread32(hcr_base
+ CC
));
1094 sata_fsl_qc_complete(qc
);
1095 ata_qc_complete(qc
);
1098 /* Spurious Interrupt!! */
1099 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1100 ioread32(hcr_base
+ CC
));
1105 static irqreturn_t
sata_fsl_interrupt(int irq
, void *dev_instance
)
1107 struct ata_host
*host
= dev_instance
;
1108 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1109 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1110 u32 interrupt_enables
;
1111 unsigned handled
= 0;
1112 struct ata_port
*ap
;
1114 /* ack. any pending IRQs for this controller/port */
1115 interrupt_enables
= ioread32(hcr_base
+ HSTATUS
);
1116 interrupt_enables
&= 0x3F;
1118 DPRINTK("interrupt status 0x%x\n", interrupt_enables
);
1120 if (!interrupt_enables
)
1123 spin_lock(&host
->lock
);
1125 /* Assuming one port per host controller */
1127 ap
= host
->ports
[0];
1129 sata_fsl_host_intr(ap
);
1131 dev_printk(KERN_WARNING
, host
->dev
,
1132 "interrupt on disabled port 0\n");
1135 iowrite32(interrupt_enables
, hcr_base
+ HSTATUS
);
1138 spin_unlock(&host
->lock
);
1140 return IRQ_RETVAL(handled
);
1144 * Multiple ports are represented by multiple SATA controllers with
1145 * one port per controller
1147 static int sata_fsl_init_controller(struct ata_host
*host
)
1149 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1150 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1154 * NOTE : We cannot bring the controller online before setting
1155 * the CHBA, hence main controller initialization is done as
1156 * part of the port_start() callback
1159 /* ack. any pending IRQs for this controller/port */
1160 temp
= ioread32(hcr_base
+ HSTATUS
);
1162 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
1164 /* Keep interrupts disabled on the controller */
1165 temp
= ioread32(hcr_base
+ HCONTROL
);
1166 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
1168 /* Disable interrupt coalescing control(icc), for the moment */
1169 DPRINTK("icc = 0x%x\n", ioread32(hcr_base
+ ICC
));
1170 iowrite32(0x01000000, hcr_base
+ ICC
);
1172 /* clear error registers, SError is cleared by libATA */
1173 iowrite32(0x00000FFFF, hcr_base
+ CE
);
1174 iowrite32(0x00000FFFF, hcr_base
+ DE
);
1176 /* initially assuming no Port multiplier, set CQPMP to 0 */
1177 iowrite32(0x0, hcr_base
+ CQPMP
);
1180 * host controller will be brought on-line, during xx_port_start()
1181 * callback, that should also initiate the OOB, COMINIT sequence
1184 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
1185 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
1191 * scsi mid-layer and libata interface structures
1193 static struct scsi_host_template sata_fsl_sht
= {
1194 .module
= THIS_MODULE
,
1196 .ioctl
= ata_scsi_ioctl
,
1197 .queuecommand
= ata_scsi_queuecmd
,
1198 .change_queue_depth
= ata_scsi_change_queue_depth
,
1199 .can_queue
= SATA_FSL_QUEUE_DEPTH
,
1200 .this_id
= ATA_SHT_THIS_ID
,
1201 .sg_tablesize
= SATA_FSL_MAX_PRD_USABLE
,
1202 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
1203 .emulated
= ATA_SHT_EMULATED
,
1204 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
1205 .proc_name
= "sata_fsl",
1206 .dma_boundary
= ATA_DMA_BOUNDARY
,
1207 .slave_configure
= ata_scsi_slave_config
,
1208 .slave_destroy
= ata_scsi_slave_destroy
,
1209 .bios_param
= ata_std_bios_param
,
1212 static const struct ata_port_operations sata_fsl_ops
= {
1213 .check_status
= sata_fsl_check_status
,
1214 .check_altstatus
= sata_fsl_check_status
,
1215 .dev_select
= ata_noop_dev_select
,
1217 .tf_read
= sata_fsl_tf_read
,
1219 .qc_prep
= sata_fsl_qc_prep
,
1220 .qc_issue
= sata_fsl_qc_issue
,
1221 .irq_clear
= ata_noop_irq_clear
,
1223 .scr_read
= sata_fsl_scr_read
,
1224 .scr_write
= sata_fsl_scr_write
,
1226 .freeze
= sata_fsl_freeze
,
1227 .thaw
= sata_fsl_thaw
,
1228 .error_handler
= sata_fsl_error_handler
,
1229 .post_internal_cmd
= sata_fsl_post_internal_cmd
,
1231 .port_start
= sata_fsl_port_start
,
1232 .port_stop
= sata_fsl_port_stop
,
1235 static const struct ata_port_info sata_fsl_port_info
[] = {
1237 .flags
= SATA_FSL_HOST_FLAGS
,
1238 .pio_mask
= 0x1f, /* pio 0-4 */
1239 .udma_mask
= 0x7f, /* udma 0-6 */
1240 .port_ops
= &sata_fsl_ops
,
1244 static int sata_fsl_probe(struct of_device
*ofdev
,
1245 const struct of_device_id
*match
)
1248 void __iomem
*hcr_base
= NULL
;
1249 void __iomem
*ssr_base
= NULL
;
1250 void __iomem
*csr_base
= NULL
;
1251 struct sata_fsl_host_priv
*host_priv
= NULL
;
1253 struct ata_host
*host
;
1255 struct ata_port_info pi
= sata_fsl_port_info
[0];
1256 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1258 dev_printk(KERN_INFO
, &ofdev
->dev
,
1259 "Sata FSL Platform/CSB Driver init\n");
1261 hcr_base
= of_iomap(ofdev
->node
, 0);
1263 goto error_exit_with_cleanup
;
1265 ssr_base
= hcr_base
+ 0x100;
1266 csr_base
= hcr_base
+ 0x140;
1268 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base
+ TRANSCFG
));
1269 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc
));
1270 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE
);
1272 host_priv
= kzalloc(sizeof(struct sata_fsl_host_priv
), GFP_KERNEL
);
1274 goto error_exit_with_cleanup
;
1276 host_priv
->hcr_base
= hcr_base
;
1277 host_priv
->ssr_base
= ssr_base
;
1278 host_priv
->csr_base
= csr_base
;
1280 irq
= irq_of_parse_and_map(ofdev
->node
, 0);
1282 dev_printk(KERN_ERR
, &ofdev
->dev
, "invalid irq from platform\n");
1283 goto error_exit_with_cleanup
;
1285 host_priv
->irq
= irq
;
1287 /* allocate host structure */
1288 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_FSL_MAX_PORTS
);
1290 /* host->iomap is not used currently */
1291 host
->private_data
= host_priv
;
1295 host
->ports
[0]->ioaddr
.cmd_addr
= host_priv
->hcr_base
;
1296 host
->ports
[0]->ioaddr
.scr_addr
= host_priv
->ssr_base
;
1298 /* initialize host controller */
1299 sata_fsl_init_controller(host
);
1302 * Now, register with libATA core, this will also initiate the
1303 * device discovery process, invoking our port_start() handler &
1304 * error_handler() to execute a dummy Softreset EH session
1306 ata_host_activate(host
, irq
, sata_fsl_interrupt
, SATA_FSL_IRQ_FLAG
,
1309 dev_set_drvdata(&ofdev
->dev
, host
);
1313 error_exit_with_cleanup
:
1323 static int sata_fsl_remove(struct of_device
*ofdev
)
1325 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
1326 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1328 ata_host_detach(host
);
1330 dev_set_drvdata(&ofdev
->dev
, NULL
);
1332 irq_dispose_mapping(host_priv
->irq
);
1333 iounmap(host_priv
->hcr_base
);
1339 static struct of_device_id fsl_sata_match
[] = {
1341 .compatible
= "fsl,pq-sata",
1346 MODULE_DEVICE_TABLE(of
, fsl_sata_match
);
1348 static struct of_platform_driver fsl_sata_driver
= {
1350 .match_table
= fsl_sata_match
,
1351 .probe
= sata_fsl_probe
,
1352 .remove
= sata_fsl_remove
,
1355 static int __init
sata_fsl_init(void)
1357 of_register_platform_driver(&fsl_sata_driver
);
1361 static void __exit
sata_fsl_exit(void)
1363 of_unregister_platform_driver(&fsl_sata_driver
);
1366 MODULE_LICENSE("GPL");
1367 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1368 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1369 MODULE_VERSION("1.10");
1371 module_init(sata_fsl_init
);
1372 module_exit(sata_fsl_exit
);