arch/x86/mach-visws/setup_visws.c

   1 /*
   2  *  Unmaintained SGI Visual Workstation support.
   3  *  Split out from setup.c by davej@suse.de
   4  */
   5
   6 #include <linux/interrupt.h>
   7 #include <linux/module.h>
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/arch_hooks.h>
  12 #include <asm/fixmap.h>
  13 #include <asm/reboot.h>
  14 #include <asm/setup.h>
  15 #include <asm/e820.h>
  16 #include <asm/io.h>
  17
  18 #include <mach_ipi.h>
  19
  20 #include "cobalt.h"
  21 #include "piix4.h"
  22
  23 char visws_board_type   = -1;
  24 char visws_board_rev    = -1;
  25
  26 static int __init visws_time_init_quirk(void)
  27 {
  28         printk(KERN_INFO "Starting Cobalt Timer system clock\n");
  29
  30         /* Set the countdown value */
  31         co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
  32
  33         /* Start the timer */
  34         co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
  35
  36         /* Enable (unmask) the timer interrupt */
  37         co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
  38
  39         /*
  40          * Zero return means the generic timer setup code will set up
  41          * the standard vector:
  42          */
  43         return 0;
  44 }
  45
  46 static int __init visws_pre_intr_init_quirk(void)
  47 {
  48         init_VISWS_APIC_irqs();
  49
  50         /*
  51          * We dont want ISA irqs to be set up by the generic code:
  52          */
  53         return 1;
  54 }
  55
  56 /* Quirk for machine specific memory setup. */
  57
  58 #define MB (1024 * 1024)
  59
  60 unsigned long sgivwfb_mem_phys;
  61 unsigned long sgivwfb_mem_size;
  62 EXPORT_SYMBOL(sgivwfb_mem_phys);
  63 EXPORT_SYMBOL(sgivwfb_mem_size);
  64
  65 long long mem_size __initdata = 0;
  66
  67 static char * __init visws_memory_setup_quirk(void)
  68 {
  69         long long gfx_mem_size = 8 * MB;
  70
  71         mem_size = boot_params.alt_mem_k;
  72
  73         if (!mem_size) {
  74                 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
  75                 mem_size = 128 * MB;
  76         }
  77
  78         /*
  79          * this hardcodes the graphics memory to 8 MB
  80          * it really should be sized dynamically (or at least
  81          * set as a boot param)
  82          */
  83         if (!sgivwfb_mem_size) {
  84                 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
  85                 sgivwfb_mem_size = 8 * MB;
  86         }
  87
  88         /*
  89          * Trim to nearest MB
  90          */
  91         sgivwfb_mem_size &= ~((1 << 20) - 1);
  92         sgivwfb_mem_phys = mem_size - gfx_mem_size;
  93
  94         e820_add_region(0, LOWMEMSIZE(), E820_RAM);
  95         e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
  96         e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
  97
  98         return "PROM";
  99 }
 100
 101 static void visws_machine_emergency_restart(void)
 102 {
 103         /*
 104          * Visual Workstations restart after this
 105          * register is poked on the PIIX4
 106          */
 107         outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
 108 }
 109
 110 static void visws_machine_power_off(void)
 111 {
 112         unsigned short pm_status;
 113 /*      extern unsigned int pci_bus0; */
 114
 115         while ((pm_status = inw(PMSTS_PORT)) & 0x100)
 116                 outw(pm_status, PMSTS_PORT);
 117
 118         outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
 119
 120         mdelay(10);
 121
 122 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
 123         (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
 124
 125 /*      outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
 126         outl(PIIX_SPECIAL_STOP, 0xCFC);
 127 }
 128
 129 extern int visws_trap_init_quirk(void);
 130
 131 void __init visws_early_detect(void)
 132 {
 133         int raw;
 134
 135         visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
 136                                                          >> PIIX_GPI_BD_SHIFT;
 137
 138         if (visws_board_type < 0)
 139                 return;
 140
 141         /*
 142          * Install special quirks for timer, interrupt and memory setup:
 143          */
 144         arch_time_init_quirk = visws_time_init_quirk;
 145         arch_pre_intr_init_quirk = visws_pre_intr_init_quirk;
 146         arch_memory_setup_quirk = visws_memory_setup_quirk;
 147
 148         /*
 149          * Fall back to generic behavior for traps:
 150          */
 151         arch_intr_init_quirk = NULL;
 152         arch_trap_init_quirk = visws_trap_init_quirk;
 153
 154         /*
 155          * Install reboot quirks:
 156          */
 157         pm_power_off = visws_machine_power_off;
 158         machine_ops.emergency_restart = visws_machine_emergency_restart;
 159
 160         /*
 161          * Do not use broadcast IPIs:
 162          */
 163         no_broadcast = 0;
 164
 165         /*
 166          * Get Board rev.
 167          * First, we have to initialize the 307 part to allow us access
 168          * to the GPIO registers.  Let's map them at 0x0fc0 which is right
 169          * after the PIIX4 PM section.
 170          */
 171         outb_p(SIO_DEV_SEL, SIO_INDEX);
 172         outb_p(SIO_GP_DEV, SIO_DATA);   /* Talk to GPIO regs. */
 173
 174         outb_p(SIO_DEV_MSB, SIO_INDEX);
 175         outb_p(SIO_GP_MSB, SIO_DATA);   /* MSB of GPIO base address */
 176
 177         outb_p(SIO_DEV_LSB, SIO_INDEX);
 178         outb_p(SIO_GP_LSB, SIO_DATA);   /* LSB of GPIO base address */
 179
 180         outb_p(SIO_DEV_ENB, SIO_INDEX);
 181         outb_p(1, SIO_DATA);            /* Enable GPIO registers. */
 182
 183         /*
 184          * Now, we have to map the power management section to write
 185          * a bit which enables access to the GPIO registers.
 186          * What lunatic came up with this shit?
 187          */
 188         outb_p(SIO_DEV_SEL, SIO_INDEX);
 189         outb_p(SIO_PM_DEV, SIO_DATA);   /* Talk to GPIO regs. */
 190
 191         outb_p(SIO_DEV_MSB, SIO_INDEX);
 192         outb_p(SIO_PM_MSB, SIO_DATA);   /* MSB of PM base address */
 193
 194         outb_p(SIO_DEV_LSB, SIO_INDEX);
 195         outb_p(SIO_PM_LSB, SIO_DATA);   /* LSB of PM base address */
 196
 197         outb_p(SIO_DEV_ENB, SIO_INDEX);
 198         outb_p(1, SIO_DATA);            /* Enable PM registers. */
 199
 200         /*
 201          * Now, write the PM register which enables the GPIO registers.
 202          */
 203         outb_p(SIO_PM_FER2, SIO_PM_INDEX);
 204         outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
 205
 206         /*
 207          * Now, initialize the GPIO registers.
 208          * We want them all to be inputs which is the
 209          * power on default, so let's leave them alone.
 210          * So, let's just read the board rev!
 211          */
 212         raw = inb_p(SIO_GP_DATA1);
 213         raw &= 0x7f;    /* 7 bits of valid board revision ID. */
 214
 215         if (visws_board_type == VISWS_320) {
 216                 if (raw < 0x6) {
 217                         visws_board_rev = 4;
 218                 } else if (raw < 0xc) {
 219                         visws_board_rev = 5;
 220                 } else {
 221                         visws_board_rev = 6;
 222                 }
 223         } else if (visws_board_type == VISWS_540) {
 224                         visws_board_rev = 2;
 225                 } else {
 226                         visws_board_rev = raw;
 227                 }
 228
 229         printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
 230                (visws_board_type == VISWS_320 ? "320" :
 231                (visws_board_type == VISWS_540 ? "540" :
 232                 "unknown")), visws_board_rev);
 233 }