2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.7"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) },
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) },
135 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
137 /* Avoid conditionals by using array */
138 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
139 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
140 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
142 /* This driver supports yukon2 chipset only */
143 static const char *yukon2_name
[] = {
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
151 /* Access to external PHY */
152 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
156 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
157 gma_write16(hw
, port
, GM_SMI_CTRL
,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
160 for (i
= 0; i
< PHY_RETRIES
; i
++) {
161 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
166 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
170 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
174 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
175 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
177 for (i
= 0; i
< PHY_RETRIES
; i
++) {
178 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
179 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
189 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
193 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
194 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
198 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
203 pr_debug("sky2_set_power_state %d\n", state
);
204 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
206 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
207 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
208 (power_control
& PCI_PM_CAP_PME_D3cold
);
210 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
212 power_control
|= PCI_PM_CTRL_PME_STATUS
;
213 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw
, B0_POWER_CTRL
,
219 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
221 /* disable Core Clock Division, */
222 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
224 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
225 /* enable bits are inverted */
226 sky2_write8(hw
, B2_Y2_CLK_GATE
,
227 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
228 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
229 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
231 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
233 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
236 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
237 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
238 reg1
&= P_ASPM_CONTROL_MSK
;
239 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
240 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
247 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
248 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
250 /* enable bits are inverted */
251 sky2_write8(hw
, B2_Y2_CLK_GATE
,
252 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
253 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
254 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
256 /* switch power to VAUX */
257 if (vaux
&& state
!= PCI_D3cold
)
258 sky2_write8(hw
, B0_POWER_CTRL
,
259 (PC_VAUX_ENA
| PC_VCC_ENA
|
260 PC_VAUX_ON
| PC_VCC_OFF
));
263 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
266 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
267 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
270 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
279 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
280 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
281 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
282 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
284 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
285 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
286 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
289 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
291 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
292 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
294 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
295 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
296 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
298 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
300 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
302 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
303 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
305 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
307 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
310 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
311 if (sky2_is_copper(hw
)) {
312 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
313 /* enable automatic crossover */
314 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
316 /* disable energy detect */
317 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
319 /* enable automatic crossover */
320 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
322 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
323 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
324 ctrl
&= ~PHY_M_PC_DSC_MSK
;
325 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
329 /* workaround for deviation #4.88 (CRC errors) */
330 /* disable Automatic Crossover */
332 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
335 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
337 /* special setup for PHY 88E1112 Fiber */
338 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
339 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
343 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
344 ctrl
&= ~PHY_M_MAC_MD_MSK
;
345 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
346 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
348 if (hw
->pmd_type
== 'P') {
349 /* select page 1 to access Fiber registers */
350 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
352 /* for SFP-module set SIGDET polarity to low */
353 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
354 ctrl
|= PHY_M_FIB_SIGD_POL
;
355 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
358 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
361 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
362 if (sky2
->autoneg
== AUTONEG_DISABLE
)
367 ctrl
|= PHY_CT_RESET
;
368 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
375 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
376 if (sky2_is_copper(hw
)) {
377 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
378 ct1000
|= PHY_M_1000C_AFD
;
379 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
380 ct1000
|= PHY_M_1000C_AHD
;
381 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
382 adv
|= PHY_M_AN_100_FD
;
383 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
384 adv
|= PHY_M_AN_100_HD
;
385 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
386 adv
|= PHY_M_AN_10_FD
;
387 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
388 adv
|= PHY_M_AN_10_HD
;
389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
391 adv
|= PHY_M_AN_1000X_AFD
;
392 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
393 adv
|= PHY_M_AN_1000X_AHD
;
396 /* Set Flow-control capabilities */
397 if (sky2
->tx_pause
&& sky2
->rx_pause
)
398 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
399 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
400 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
401 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
402 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
404 /* Restart Auto-negotiation */
405 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
407 /* forced speed/duplex settings */
408 ct1000
= PHY_M_1000C_MSE
;
410 /* Disable auto update for duplex flow control and speed */
411 reg
|= GM_GPCR_AU_ALL_DIS
;
413 switch (sky2
->speed
) {
415 ctrl
|= PHY_CT_SP1000
;
416 reg
|= GM_GPCR_SPEED_1000
;
419 ctrl
|= PHY_CT_SP100
;
420 reg
|= GM_GPCR_SPEED_100
;
424 if (sky2
->duplex
== DUPLEX_FULL
) {
425 reg
|= GM_GPCR_DUP_FULL
;
426 ctrl
|= PHY_CT_DUP_MD
;
427 } else if (sky2
->speed
!= SPEED_1000
&& hw
->chip_id
!= CHIP_ID_YUKON_EC_U
) {
428 /* Turn off flow control for 10/100mbps */
434 reg
|= GM_GPCR_FC_RX_DIS
;
437 reg
|= GM_GPCR_FC_TX_DIS
;
439 /* Forward pause packets to GMAC? */
440 if (sky2
->tx_pause
|| sky2
->rx_pause
)
441 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
443 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
445 ctrl
|= PHY_CT_RESET
;
448 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
450 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
451 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
453 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
454 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
456 /* Setup Phy LED's */
457 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
460 switch (hw
->chip_id
) {
461 case CHIP_ID_YUKON_FE
:
462 /* on 88E3082 these bits are at 11..9 (shifted left) */
463 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
465 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
467 /* delete ACT LED control bits */
468 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
469 /* change ACT LED control to blink mode */
470 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
471 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
474 case CHIP_ID_YUKON_XL
:
475 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
477 /* select page 3 to access LED control register */
478 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
480 /* set LED Function Control register */
481 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
482 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
483 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
484 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
485 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
487 /* set Polarity Control register */
488 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
489 (PHY_M_POLC_LS1_P_MIX(4) |
490 PHY_M_POLC_IS0_P_MIX(4) |
491 PHY_M_POLC_LOS_CTRL(2) |
492 PHY_M_POLC_INIT_CTRL(2) |
493 PHY_M_POLC_STA1_CTRL(2) |
494 PHY_M_POLC_STA0_CTRL(2)));
496 /* restore page register */
497 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
499 case CHIP_ID_YUKON_EC_U
:
500 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
502 /* select page 3 to access LED control register */
503 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
505 /* set LED Function Control register */
506 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
507 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
508 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
509 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
510 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512 /* set Blink Rate in LED Timer Control Register */
513 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
514 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
515 /* restore page register */
516 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
520 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
521 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
522 /* turn off the Rx LED (LED_RX) */
523 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
526 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
527 /* apply fixes in PHY AFE */
528 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
529 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
531 /* increase differential signal amplitude in 10BASE-T */
532 gm_phy_write(hw
, port
, 0x18, 0xaa99);
533 gm_phy_write(hw
, port
, 0x17, 0x2011);
535 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
536 gm_phy_write(hw
, port
, 0x18, 0xa204);
537 gm_phy_write(hw
, port
, 0x17, 0x2002);
539 /* set page register to 0 */
540 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
542 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
544 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
545 /* turn on 100 Mbps LED (LED_LINK100) */
546 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
550 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
554 /* Enable phy interrupt on auto-negotiation complete (or link up) */
555 if (sky2
->autoneg
== AUTONEG_ENABLE
)
556 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
558 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
561 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
564 static const u32 phy_power
[]
565 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
567 /* looks like this XL is back asswards .. */
568 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
571 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
574 /* Turn off phy power saving */
575 reg1
&= ~phy_power
[port
];
577 reg1
|= phy_power
[port
];
579 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
580 sky2_pci_read32(hw
, PCI_DEV_REG1
);
584 /* Force a renegotiation */
585 static void sky2_phy_reinit(struct sky2_port
*sky2
)
587 spin_lock_bh(&sky2
->phy_lock
);
588 sky2_phy_init(sky2
->hw
, sky2
->port
);
589 spin_unlock_bh(&sky2
->phy_lock
);
592 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
594 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
597 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
599 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
600 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
602 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
604 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
605 /* WA DEV_472 -- looks like crossed wires on port 2 */
606 /* clear GMAC 1 Control reset */
607 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
609 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
610 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
611 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
612 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
613 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
616 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
618 /* Enable Transmit FIFO Underrun */
619 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
621 spin_lock_bh(&sky2
->phy_lock
);
622 sky2_phy_init(hw
, port
);
623 spin_unlock_bh(&sky2
->phy_lock
);
626 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
627 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
629 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
630 gma_read16(hw
, port
, i
);
631 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
633 /* transmit control */
634 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
636 /* receive control reg: unicast + multicast + no FCS */
637 gma_write16(hw
, port
, GM_RX_CTRL
,
638 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
640 /* transmit flow control */
641 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
643 /* transmit parameter */
644 gma_write16(hw
, port
, GM_TX_PARAM
,
645 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
646 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
647 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
648 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
650 /* serial mode register */
651 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
652 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
654 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
655 reg
|= GM_SMOD_JUMBO_ENA
;
657 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
659 /* virtual address for data */
660 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
662 /* physical address: used for pause frames */
663 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
665 /* ignore counter overflows */
666 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
667 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
668 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
670 /* Configure Rx MAC FIFO */
671 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
672 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
673 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
675 /* Flush Rx MAC FIFO on any flow control or error */
676 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
678 /* Set threshold to 0xa (64 bytes)
679 * ASF disabled so no need to do WA dev #4.30
681 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
685 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
687 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
688 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
689 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
690 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
700 /* Assign Ram Buffer allocation.
701 * start and end are in units of 4k bytes
702 * ram registers are in units of 64bit words
704 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
708 start
= startk
* 4096/8;
709 end
= (endk
* 4096/8) - 1;
711 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
712 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
713 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
714 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
715 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
717 if (q
== Q_R1
|| q
== Q_R2
) {
718 u32 space
= (endk
- startk
) * 4096/8;
719 u32 tp
= space
- space
/4;
721 /* On receive queue's set the thresholds
722 * give receiver priority when > 3/4 full
723 * send pause when down to 2K
725 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
726 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
729 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
730 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
732 /* Enable store & forward on Tx queue's because
733 * Tx FIFO is only 1K on Yukon
735 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
738 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
739 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
742 /* Setup Bus Memory Interface */
743 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
745 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
746 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
747 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
748 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
751 /* Setup prefetch unit registers. This is the interface between
752 * hardware and driver list elements
754 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
757 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
758 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
759 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
760 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
761 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
762 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
764 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
767 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
769 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
771 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
776 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
777 struct sky2_tx_le
*le
)
779 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
782 /* Update chip's next pointer */
783 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
785 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
787 sky2_write16(hw
, q
, idx
);
792 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
794 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
795 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
800 /* Return high part of DMA address (could be 32 or 64 bit) */
801 static inline u32
high32(dma_addr_t a
)
803 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
806 /* Build description to hardware about buffer */
807 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
809 struct sky2_rx_le
*le
;
810 u32 hi
= high32(map
);
811 u16 len
= sky2
->rx_bufsize
;
813 if (sky2
->rx_addr64
!= hi
) {
814 le
= sky2_next_rx(sky2
);
815 le
->addr
= cpu_to_le32(hi
);
816 le
->opcode
= OP_ADDR64
| HW_OWNER
;
817 sky2
->rx_addr64
= high32(map
+ len
);
820 le
= sky2_next_rx(sky2
);
821 le
->addr
= cpu_to_le32((u32
) map
);
822 le
->length
= cpu_to_le16(len
);
823 le
->opcode
= OP_PACKET
| HW_OWNER
;
827 /* Tell chip where to start receive checksum.
828 * Actually has two checksums, but set both same to avoid possible byte
831 static void rx_set_checksum(struct sky2_port
*sky2
)
833 struct sky2_rx_le
*le
;
835 le
= sky2_next_rx(sky2
);
836 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
838 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
840 sky2_write32(sky2
->hw
,
841 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
842 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
847 * The RX Stop command will not work for Yukon-2 if the BMU does not
848 * reach the end of packet and since we can't make sure that we have
849 * incoming data, we must reset the BMU while it is not doing a DMA
850 * transfer. Since it is possible that the RX path is still active,
851 * the RX RAM buffer will be stopped first, so any possible incoming
852 * data will not trigger a DMA. After the RAM buffer is stopped, the
853 * BMU is polled until any DMA in progress is ended and only then it
856 static void sky2_rx_stop(struct sky2_port
*sky2
)
858 struct sky2_hw
*hw
= sky2
->hw
;
859 unsigned rxq
= rxqaddr
[sky2
->port
];
862 /* disable the RAM Buffer receive queue */
863 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
865 for (i
= 0; i
< 0xffff; i
++)
866 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
867 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
870 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
873 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
875 /* reset the Rx prefetch unit */
876 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
879 /* Clean out receive buffer area, assumes receiver hardware stopped */
880 static void sky2_rx_clean(struct sky2_port
*sky2
)
884 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
885 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
886 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
889 pci_unmap_single(sky2
->hw
->pdev
,
890 re
->mapaddr
, sky2
->rx_bufsize
,
898 /* Basic MII support */
899 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
901 struct mii_ioctl_data
*data
= if_mii(ifr
);
902 struct sky2_port
*sky2
= netdev_priv(dev
);
903 struct sky2_hw
*hw
= sky2
->hw
;
904 int err
= -EOPNOTSUPP
;
906 if (!netif_running(dev
))
907 return -ENODEV
; /* Phy still in reset */
911 data
->phy_id
= PHY_ADDR_MARV
;
917 spin_lock_bh(&sky2
->phy_lock
);
918 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
919 spin_unlock_bh(&sky2
->phy_lock
);
926 if (!capable(CAP_NET_ADMIN
))
929 spin_lock_bh(&sky2
->phy_lock
);
930 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
932 spin_unlock_bh(&sky2
->phy_lock
);
938 #ifdef SKY2_VLAN_TAG_USED
939 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
941 struct sky2_port
*sky2
= netdev_priv(dev
);
942 struct sky2_hw
*hw
= sky2
->hw
;
943 u16 port
= sky2
->port
;
945 netif_tx_lock_bh(dev
);
947 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
948 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
951 netif_tx_unlock_bh(dev
);
954 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
956 struct sky2_port
*sky2
= netdev_priv(dev
);
957 struct sky2_hw
*hw
= sky2
->hw
;
958 u16 port
= sky2
->port
;
960 netif_tx_lock_bh(dev
);
962 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
963 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
965 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
967 netif_tx_unlock_bh(dev
);
972 * It appears the hardware has a bug in the FIFO logic that
973 * cause it to hang if the FIFO gets overrun and the receive buffer
974 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
975 * aligned except if slab debugging is enabled.
977 static inline struct sk_buff
*sky2_alloc_skb(struct net_device
*dev
,
983 skb
= __netdev_alloc_skb(dev
, length
+ RX_SKB_ALIGN
, gfp_mask
);
985 unsigned long p
= (unsigned long) skb
->data
;
986 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
993 * Allocate and setup receiver buffer pool.
994 * In case of 64 bit dma, there are 2X as many list elements
995 * available as ring entries
996 * and need to reserve one list element so we don't wrap around.
998 static int sky2_rx_start(struct sky2_port
*sky2
)
1000 struct sky2_hw
*hw
= sky2
->hw
;
1001 unsigned rxq
= rxqaddr
[sky2
->port
];
1005 sky2
->rx_put
= sky2
->rx_next
= 0;
1008 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
1009 /* MAC Rx RAM Read is controlled by hardware */
1010 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1013 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1015 rx_set_checksum(sky2
);
1016 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1017 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1019 re
->skb
= sky2_alloc_skb(sky2
->netdev
, sky2
->rx_bufsize
,
1024 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1025 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1026 sky2_rx_add(sky2
, re
->mapaddr
);
1031 * The receiver hangs if it receives frames larger than the
1032 * packet buffer. As a workaround, truncate oversize frames, but
1033 * the register is limited to 9 bits, so if you do frames > 2052
1034 * you better get the MTU right!
1036 thresh
= (sky2
->rx_bufsize
- 8) / sizeof(u32
);
1038 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1040 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1041 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1045 /* Tell chip about available buffers */
1046 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1049 sky2_rx_clean(sky2
);
1053 /* Bring up network interface. */
1054 static int sky2_up(struct net_device
*dev
)
1056 struct sky2_port
*sky2
= netdev_priv(dev
);
1057 struct sky2_hw
*hw
= sky2
->hw
;
1058 unsigned port
= sky2
->port
;
1059 u32 ramsize
, rxspace
, imask
;
1060 int cap
, err
= -ENOMEM
;
1061 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1064 * On dual port PCI-X card, there is an problem where status
1065 * can be received out of order due to split transactions
1067 if (otherdev
&& netif_running(otherdev
) &&
1068 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1069 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1072 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1073 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1074 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1080 if (netif_msg_ifup(sky2
))
1081 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1083 /* must be power of 2 */
1084 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1086 sizeof(struct sky2_tx_le
),
1091 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1095 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1097 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1101 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1103 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1108 sky2_phy_power(hw
, port
, 1);
1110 sky2_mac_init(hw
, port
);
1112 /* Determine available ram buffer space (in 4K blocks).
1113 * Note: not sure about the FE setting below yet
1115 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1118 ramsize
= sky2_read8(hw
, B2_E_0
);
1120 /* Give transmitter one third (rounded up) */
1121 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1123 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1124 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1126 /* Make sure SyncQ is disabled */
1127 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1130 sky2_qset(hw
, txqaddr
[port
]);
1132 /* Set almost empty threshold */
1133 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1134 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1135 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1137 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1140 err
= sky2_rx_start(sky2
);
1144 /* Enable interrupts from phy/mac for port */
1145 imask
= sky2_read32(hw
, B0_IMSK
);
1146 imask
|= portirq_msk
[port
];
1147 sky2_write32(hw
, B0_IMSK
, imask
);
1153 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1154 sky2
->rx_le
, sky2
->rx_le_map
);
1158 pci_free_consistent(hw
->pdev
,
1159 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1160 sky2
->tx_le
, sky2
->tx_le_map
);
1163 kfree(sky2
->tx_ring
);
1164 kfree(sky2
->rx_ring
);
1166 sky2
->tx_ring
= NULL
;
1167 sky2
->rx_ring
= NULL
;
1171 /* Modular subtraction in ring */
1172 static inline int tx_dist(unsigned tail
, unsigned head
)
1174 return (head
- tail
) & (TX_RING_SIZE
- 1);
1177 /* Number of list elements available for next tx */
1178 static inline int tx_avail(const struct sky2_port
*sky2
)
1180 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1183 /* Estimate of number of transmit list elements required */
1184 static unsigned tx_le_req(const struct sk_buff
*skb
)
1188 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1189 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1191 if (skb_is_gso(skb
))
1194 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1201 * Put one packet in ring for transmit.
1202 * A single packet can generate multiple list elements, and
1203 * the number of ring elements will probably be less than the number
1204 * of list elements used.
1206 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1208 struct sky2_port
*sky2
= netdev_priv(dev
);
1209 struct sky2_hw
*hw
= sky2
->hw
;
1210 struct sky2_tx_le
*le
= NULL
;
1211 struct tx_ring_info
*re
;
1218 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1219 return NETDEV_TX_BUSY
;
1221 if (unlikely(netif_msg_tx_queued(sky2
)))
1222 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1223 dev
->name
, sky2
->tx_prod
, skb
->len
);
1225 len
= skb_headlen(skb
);
1226 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1227 addr64
= high32(mapping
);
1229 /* Send high bits if changed or crosses boundary */
1230 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1231 le
= get_tx_le(sky2
);
1232 le
->addr
= cpu_to_le32(addr64
);
1233 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1234 sky2
->tx_addr64
= high32(mapping
+ len
);
1237 /* Check for TCP Segmentation Offload */
1238 mss
= skb_shinfo(skb
)->gso_size
;
1240 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1241 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1244 if (mss
!= sky2
->tx_last_mss
) {
1245 le
= get_tx_le(sky2
);
1246 le
->addr
= cpu_to_le32(mss
);
1247 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1248 sky2
->tx_last_mss
= mss
;
1253 #ifdef SKY2_VLAN_TAG_USED
1254 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1255 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1257 le
= get_tx_le(sky2
);
1259 le
->opcode
= OP_VLAN
|HW_OWNER
;
1261 le
->opcode
|= OP_VLAN
;
1262 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1267 /* Handle TCP checksum offload */
1268 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1269 unsigned offset
= skb
->h
.raw
- skb
->data
;
1272 tcpsum
= offset
<< 16; /* sum start */
1273 tcpsum
|= offset
+ skb
->csum
; /* sum write */
1275 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1276 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1279 if (tcpsum
!= sky2
->tx_tcpsum
) {
1280 sky2
->tx_tcpsum
= tcpsum
;
1282 le
= get_tx_le(sky2
);
1283 le
->addr
= cpu_to_le32(tcpsum
);
1284 le
->length
= 0; /* initial checksum value */
1285 le
->ctrl
= 1; /* one packet */
1286 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1290 le
= get_tx_le(sky2
);
1291 le
->addr
= cpu_to_le32((u32
) mapping
);
1292 le
->length
= cpu_to_le16(len
);
1294 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1296 re
= tx_le_re(sky2
, le
);
1298 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1299 pci_unmap_len_set(re
, maplen
, len
);
1301 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1302 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1304 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1305 frag
->size
, PCI_DMA_TODEVICE
);
1306 addr64
= high32(mapping
);
1307 if (addr64
!= sky2
->tx_addr64
) {
1308 le
= get_tx_le(sky2
);
1309 le
->addr
= cpu_to_le32(addr64
);
1311 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1312 sky2
->tx_addr64
= addr64
;
1315 le
= get_tx_le(sky2
);
1316 le
->addr
= cpu_to_le32((u32
) mapping
);
1317 le
->length
= cpu_to_le16(frag
->size
);
1319 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1321 re
= tx_le_re(sky2
, le
);
1323 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1324 pci_unmap_len_set(re
, maplen
, frag
->size
);
1329 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1330 netif_stop_queue(dev
);
1332 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1334 dev
->trans_start
= jiffies
;
1335 return NETDEV_TX_OK
;
1339 * Free ring elements from starting at tx_cons until "done"
1341 * NB: the hardware will tell us about partial completion of multi-part
1342 * buffers so make sure not to free skb to early.
1344 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1346 struct net_device
*dev
= sky2
->netdev
;
1347 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1350 BUG_ON(done
>= TX_RING_SIZE
);
1352 for (idx
= sky2
->tx_cons
; idx
!= done
;
1353 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1354 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1355 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1357 switch(le
->opcode
& ~HW_OWNER
) {
1360 pci_unmap_single(pdev
,
1361 pci_unmap_addr(re
, mapaddr
),
1362 pci_unmap_len(re
, maplen
),
1366 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1367 pci_unmap_len(re
, maplen
),
1372 if (le
->ctrl
& EOP
) {
1373 if (unlikely(netif_msg_tx_done(sky2
)))
1374 printk(KERN_DEBUG
"%s: tx done %u\n",
1376 dev_kfree_skb(re
->skb
);
1379 le
->opcode
= 0; /* paranoia */
1382 sky2
->tx_cons
= idx
;
1383 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1384 netif_wake_queue(dev
);
1387 /* Cleanup all untransmitted buffers, assume transmitter not running */
1388 static void sky2_tx_clean(struct net_device
*dev
)
1390 struct sky2_port
*sky2
= netdev_priv(dev
);
1392 netif_tx_lock_bh(dev
);
1393 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1394 netif_tx_unlock_bh(dev
);
1397 /* Network shutdown */
1398 static int sky2_down(struct net_device
*dev
)
1400 struct sky2_port
*sky2
= netdev_priv(dev
);
1401 struct sky2_hw
*hw
= sky2
->hw
;
1402 unsigned port
= sky2
->port
;
1406 /* Never really got started! */
1410 if (netif_msg_ifdown(sky2
))
1411 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1413 /* Stop more packets from being queued */
1414 netif_stop_queue(dev
);
1416 sky2_gmac_reset(hw
, port
);
1418 /* Stop transmitter */
1419 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1420 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1422 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1423 RB_RST_SET
| RB_DIS_OP_MD
);
1425 /* WA for dev. #4.209 */
1426 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1427 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
)
1428 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1429 sky2
->speed
!= SPEED_1000
?
1430 TX_STFW_ENA
: TX_STFW_DIS
);
1432 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1433 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1434 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1436 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1438 /* Workaround shared GMAC reset */
1439 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1440 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1441 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1443 /* Disable Force Sync bit and Enable Alloc bit */
1444 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1445 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1447 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1448 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1449 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1451 /* Reset the PCI FIFO of the async Tx queue */
1452 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1453 BMU_RST_SET
| BMU_FIFO_RST
);
1455 /* Reset the Tx prefetch units */
1456 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1459 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1463 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1464 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1466 /* Disable port IRQ */
1467 imask
= sky2_read32(hw
, B0_IMSK
);
1468 imask
&= ~portirq_msk
[port
];
1469 sky2_write32(hw
, B0_IMSK
, imask
);
1471 sky2_phy_power(hw
, port
, 0);
1473 /* turn off LED's */
1474 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1476 synchronize_irq(hw
->pdev
->irq
);
1479 sky2_rx_clean(sky2
);
1481 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1482 sky2
->rx_le
, sky2
->rx_le_map
);
1483 kfree(sky2
->rx_ring
);
1485 pci_free_consistent(hw
->pdev
,
1486 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1487 sky2
->tx_le
, sky2
->tx_le_map
);
1488 kfree(sky2
->tx_ring
);
1493 sky2
->rx_ring
= NULL
;
1494 sky2
->tx_ring
= NULL
;
1499 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1501 if (!sky2_is_copper(hw
))
1504 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1505 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1507 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1508 case PHY_M_PS_SPEED_1000
:
1510 case PHY_M_PS_SPEED_100
:
1517 static void sky2_link_up(struct sky2_port
*sky2
)
1519 struct sky2_hw
*hw
= sky2
->hw
;
1520 unsigned port
= sky2
->port
;
1524 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1525 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1526 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1528 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1530 netif_carrier_on(sky2
->netdev
);
1531 netif_wake_queue(sky2
->netdev
);
1533 /* Turn on link LED */
1534 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1535 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1537 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1538 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1539 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1541 switch(sky2
->speed
) {
1543 led
|= PHY_M_LEDC_INIT_CTRL(7);
1547 led
|= PHY_M_LEDC_STA1_CTRL(7);
1551 led
|= PHY_M_LEDC_STA0_CTRL(7);
1555 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1556 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1557 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1560 if (netif_msg_link(sky2
))
1561 printk(KERN_INFO PFX
1562 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1563 sky2
->netdev
->name
, sky2
->speed
,
1564 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1565 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1566 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1569 static void sky2_link_down(struct sky2_port
*sky2
)
1571 struct sky2_hw
*hw
= sky2
->hw
;
1572 unsigned port
= sky2
->port
;
1575 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1577 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1578 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1579 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1581 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1582 /* restore Asymmetric Pause bit */
1583 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1584 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1588 netif_carrier_off(sky2
->netdev
);
1589 netif_stop_queue(sky2
->netdev
);
1591 /* Turn on link LED */
1592 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1594 if (netif_msg_link(sky2
))
1595 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1597 sky2_phy_init(hw
, port
);
1600 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1602 struct sky2_hw
*hw
= sky2
->hw
;
1603 unsigned port
= sky2
->port
;
1606 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1608 if (lpa
& PHY_M_AN_RF
) {
1609 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1613 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1614 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1615 sky2
->netdev
->name
);
1619 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1620 if (sky2
->speed
== SPEED_1000
) {
1621 u16 ctl2
= gm_phy_read(hw
, port
, PHY_MARV_1000T_CTRL
);
1622 u16 lpa2
= gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
);
1623 if (lpa2
& PHY_B_1000S_MSF
) {
1624 printk(KERN_ERR PFX
"%s: master/slave fault",
1625 sky2
->netdev
->name
);
1629 if ((ctl2
& PHY_M_1000C_AFD
) && (lpa2
& PHY_B_1000S_LP_FD
))
1630 sky2
->duplex
= DUPLEX_FULL
;
1632 sky2
->duplex
= DUPLEX_HALF
;
1634 u16 adv
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1635 if ((aux
& adv
) & PHY_AN_FULL
)
1636 sky2
->duplex
= DUPLEX_FULL
;
1638 sky2
->duplex
= DUPLEX_HALF
;
1641 /* Pause bits are offset (9..8) */
1642 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1645 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1646 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1648 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
!= SPEED_1000
1649 && hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
1650 sky2
->rx_pause
= sky2
->tx_pause
= 0;
1652 if (sky2
->rx_pause
|| sky2
->tx_pause
)
1653 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1655 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1660 /* Interrupt from PHY */
1661 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1663 struct net_device
*dev
= hw
->dev
[port
];
1664 struct sky2_port
*sky2
= netdev_priv(dev
);
1665 u16 istatus
, phystat
;
1667 spin_lock(&sky2
->phy_lock
);
1668 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1669 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1671 if (!netif_running(dev
))
1674 if (netif_msg_intr(sky2
))
1675 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1676 sky2
->netdev
->name
, istatus
, phystat
);
1678 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1679 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1684 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1685 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1687 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1689 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1691 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1692 if (phystat
& PHY_M_PS_LINK_UP
)
1695 sky2_link_down(sky2
);
1698 spin_unlock(&sky2
->phy_lock
);
1702 /* Transmit timeout is only called if we are running, carries is up
1703 * and tx queue is full (stopped).
1705 static void sky2_tx_timeout(struct net_device
*dev
)
1707 struct sky2_port
*sky2
= netdev_priv(dev
);
1708 struct sky2_hw
*hw
= sky2
->hw
;
1709 unsigned txq
= txqaddr
[sky2
->port
];
1712 if (netif_msg_timer(sky2
))
1713 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1715 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1716 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1718 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1720 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1722 if (report
!= done
) {
1723 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1725 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1726 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1727 } else if (report
!= sky2
->tx_cons
) {
1728 printk(KERN_INFO PFX
"status report lost?\n");
1730 netif_tx_lock_bh(dev
);
1731 sky2_tx_complete(sky2
, report
);
1732 netif_tx_unlock_bh(dev
);
1734 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1736 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1737 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1742 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1747 /* Want receive buffer size to be multiple of 64 bits
1748 * and incl room for vlan and truncation
1750 static inline unsigned sky2_buf_size(int mtu
)
1752 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1755 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1757 struct sky2_port
*sky2
= netdev_priv(dev
);
1758 struct sky2_hw
*hw
= sky2
->hw
;
1763 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1766 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1769 if (!netif_running(dev
)) {
1774 imask
= sky2_read32(hw
, B0_IMSK
);
1775 sky2_write32(hw
, B0_IMSK
, 0);
1777 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1778 netif_stop_queue(dev
);
1779 netif_poll_disable(hw
->dev
[0]);
1781 synchronize_irq(hw
->pdev
->irq
);
1783 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1784 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1786 sky2_rx_clean(sky2
);
1789 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1790 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1791 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1793 if (dev
->mtu
> ETH_DATA_LEN
)
1794 mode
|= GM_SMOD_JUMBO_ENA
;
1796 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1798 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1800 err
= sky2_rx_start(sky2
);
1801 sky2_write32(hw
, B0_IMSK
, imask
);
1806 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1808 netif_poll_enable(hw
->dev
[0]);
1809 netif_wake_queue(dev
);
1816 * Receive one packet.
1817 * For small packets or errors, just reuse existing skb.
1818 * For larger packets, get new buffer.
1820 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
1821 u16 length
, u32 status
)
1823 struct sky2_port
*sky2
= netdev_priv(dev
);
1824 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1825 struct sk_buff
*skb
= NULL
;
1827 if (unlikely(netif_msg_rx_status(sky2
)))
1828 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1829 dev
->name
, sky2
->rx_next
, status
, length
);
1831 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1832 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1834 if (status
& GMR_FS_ANY_ERR
)
1837 if (!(status
& GMR_FS_RX_OK
))
1840 if (length
> dev
->mtu
+ ETH_HLEN
)
1843 if (length
< copybreak
) {
1844 skb
= netdev_alloc_skb(dev
, length
+ 2);
1848 skb_reserve(skb
, 2);
1849 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1850 length
, PCI_DMA_FROMDEVICE
);
1851 memcpy(skb
->data
, re
->skb
->data
, length
);
1852 skb
->ip_summed
= re
->skb
->ip_summed
;
1853 skb
->csum
= re
->skb
->csum
;
1854 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1855 length
, PCI_DMA_FROMDEVICE
);
1857 struct sk_buff
*nskb
;
1859 nskb
= sky2_alloc_skb(dev
, sky2
->rx_bufsize
, GFP_ATOMIC
);
1865 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1866 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1867 prefetch(skb
->data
);
1869 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1870 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1873 skb_put(skb
, length
);
1875 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1876 sky2_rx_add(sky2
, re
->mapaddr
);
1881 ++sky2
->net_stats
.rx_over_errors
;
1885 ++sky2
->net_stats
.rx_errors
;
1887 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1888 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1889 dev
->name
, status
, length
);
1891 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1892 sky2
->net_stats
.rx_length_errors
++;
1893 if (status
& GMR_FS_FRAGMENT
)
1894 sky2
->net_stats
.rx_frame_errors
++;
1895 if (status
& GMR_FS_CRC_ERR
)
1896 sky2
->net_stats
.rx_crc_errors
++;
1897 if (status
& GMR_FS_RX_FF_OV
)
1898 sky2
->net_stats
.rx_fifo_errors
++;
1903 /* Transmit complete */
1904 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1906 struct sky2_port
*sky2
= netdev_priv(dev
);
1908 if (netif_running(dev
)) {
1910 sky2_tx_complete(sky2
, last
);
1911 netif_tx_unlock(dev
);
1915 /* Process status response ring */
1916 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1918 struct sky2_port
*sky2
;
1920 unsigned buf_write
[2] = { 0, 0 };
1921 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1925 while (hw
->st_idx
!= hwidx
) {
1926 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1927 struct net_device
*dev
;
1928 struct sk_buff
*skb
;
1932 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1934 BUG_ON(le
->link
>= 2);
1935 dev
= hw
->dev
[le
->link
];
1937 sky2
= netdev_priv(dev
);
1938 length
= le16_to_cpu(le
->length
);
1939 status
= le32_to_cpu(le
->status
);
1941 switch (le
->opcode
& ~HW_OWNER
) {
1943 skb
= sky2_receive(dev
, length
, status
);
1947 skb
->protocol
= eth_type_trans(skb
, dev
);
1948 dev
->last_rx
= jiffies
;
1950 #ifdef SKY2_VLAN_TAG_USED
1951 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1952 vlan_hwaccel_receive_skb(skb
,
1954 be16_to_cpu(sky2
->rx_tag
));
1957 netif_receive_skb(skb
);
1959 /* Update receiver after 16 frames */
1960 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
1961 sky2_put_idx(hw
, rxqaddr
[le
->link
],
1963 buf_write
[le
->link
] = 0;
1966 /* Stop after net poll weight */
1967 if (++work_done
>= to_do
)
1971 #ifdef SKY2_VLAN_TAG_USED
1973 sky2
->rx_tag
= length
;
1977 sky2
->rx_tag
= length
;
1981 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1982 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1983 skb
->csum
= status
& 0xffff;
1987 /* TX index reports status for both ports */
1988 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
1989 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
1991 sky2_tx_done(hw
->dev
[1],
1992 ((status
>> 24) & 0xff)
1993 | (u16
)(length
& 0xf) << 8);
1997 if (net_ratelimit())
1998 printk(KERN_WARNING PFX
1999 "unknown status opcode 0x%x\n", le
->opcode
);
2004 /* Fully processed status ring so clear irq */
2005 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2009 sky2
= netdev_priv(hw
->dev
[0]);
2010 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2014 sky2
= netdev_priv(hw
->dev
[1]);
2015 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2021 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2023 struct net_device
*dev
= hw
->dev
[port
];
2025 if (net_ratelimit())
2026 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2029 if (status
& Y2_IS_PAR_RD1
) {
2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2034 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2037 if (status
& Y2_IS_PAR_WR1
) {
2038 if (net_ratelimit())
2039 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2042 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2045 if (status
& Y2_IS_PAR_MAC1
) {
2046 if (net_ratelimit())
2047 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2048 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2051 if (status
& Y2_IS_PAR_RX1
) {
2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2054 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2057 if (status
& Y2_IS_TCP_TXA1
) {
2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2061 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2065 static void sky2_hw_intr(struct sky2_hw
*hw
)
2067 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2069 if (status
& Y2_IS_TIST_OV
)
2070 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2072 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2075 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2078 pci_name(hw
->pdev
), pci_err
);
2080 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2081 sky2_pci_write16(hw
, PCI_STATUS
,
2082 pci_err
| PCI_STATUS_ERROR_BITS
);
2083 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2086 if (status
& Y2_IS_PCI_EXP
) {
2087 /* PCI-Express uncorrectable Error occurred */
2090 pex_err
= sky2_pci_read32(hw
,
2091 hw
->err_cap
+ PCI_ERR_UNCOR_STATUS
);
2093 if (net_ratelimit())
2094 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2095 pci_name(hw
->pdev
), pex_err
);
2097 /* clear the interrupt */
2098 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2099 sky2_pci_write32(hw
,
2100 hw
->err_cap
+ PCI_ERR_UNCOR_STATUS
,
2102 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2105 /* In case of fatal error mask off to keep from getting stuck */
2106 if (pex_err
& (PCI_ERR_UNC_POISON_TLP
| PCI_ERR_UNC_FCP
2107 | PCI_ERR_UNC_DLP
)) {
2108 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2109 hwmsk
&= ~Y2_IS_PCI_EXP
;
2110 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2115 if (status
& Y2_HWE_L1_MASK
)
2116 sky2_hw_error(hw
, 0, status
);
2118 if (status
& Y2_HWE_L1_MASK
)
2119 sky2_hw_error(hw
, 1, status
);
2122 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2124 struct net_device
*dev
= hw
->dev
[port
];
2125 struct sky2_port
*sky2
= netdev_priv(dev
);
2126 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2128 if (netif_msg_intr(sky2
))
2129 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2132 if (status
& GM_IS_RX_FF_OR
) {
2133 ++sky2
->net_stats
.rx_fifo_errors
;
2134 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2137 if (status
& GM_IS_TX_FF_UR
) {
2138 ++sky2
->net_stats
.tx_fifo_errors
;
2139 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2143 /* This should never happen it is a fatal situation */
2144 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2145 const char *rxtx
, u32 mask
)
2147 struct net_device
*dev
= hw
->dev
[port
];
2148 struct sky2_port
*sky2
= netdev_priv(dev
);
2151 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2152 dev
? dev
->name
: "<not registered>", rxtx
);
2154 imask
= sky2_read32(hw
, B0_IMSK
);
2156 sky2_write32(hw
, B0_IMSK
, imask
);
2159 spin_lock(&sky2
->phy_lock
);
2160 sky2_link_down(sky2
);
2161 spin_unlock(&sky2
->phy_lock
);
2165 /* If idle then force a fake soft NAPI poll once a second
2166 * to work around cases where sharing an edge triggered interrupt.
2168 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2170 if (idle_timeout
> 0)
2171 mod_timer(&hw
->idle_timer
,
2172 jiffies
+ msecs_to_jiffies(idle_timeout
));
2175 static void sky2_idle(unsigned long arg
)
2177 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2178 struct net_device
*dev
= hw
->dev
[0];
2180 if (__netif_rx_schedule_prep(dev
))
2181 __netif_rx_schedule(dev
);
2183 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2187 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2189 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2190 int work_limit
= min(dev0
->quota
, *budget
);
2192 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2194 if (status
& Y2_IS_HW_ERR
)
2197 if (status
& Y2_IS_IRQ_PHY1
)
2198 sky2_phy_intr(hw
, 0);
2200 if (status
& Y2_IS_IRQ_PHY2
)
2201 sky2_phy_intr(hw
, 1);
2203 if (status
& Y2_IS_IRQ_MAC1
)
2204 sky2_mac_intr(hw
, 0);
2206 if (status
& Y2_IS_IRQ_MAC2
)
2207 sky2_mac_intr(hw
, 1);
2209 if (status
& Y2_IS_CHK_RX1
)
2210 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2212 if (status
& Y2_IS_CHK_RX2
)
2213 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2215 if (status
& Y2_IS_CHK_TXA1
)
2216 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2218 if (status
& Y2_IS_CHK_TXA2
)
2219 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2221 work_done
= sky2_status_intr(hw
, work_limit
);
2222 if (work_done
< work_limit
) {
2223 netif_rx_complete(dev0
);
2225 sky2_read32(hw
, B0_Y2_SP_LISR
);
2228 *budget
-= work_done
;
2229 dev0
->quota
-= work_done
;
2234 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2236 struct sky2_hw
*hw
= dev_id
;
2237 struct net_device
*dev0
= hw
->dev
[0];
2240 /* Reading this mask interrupts as side effect */
2241 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2242 if (status
== 0 || status
== ~0)
2245 prefetch(&hw
->st_le
[hw
->st_idx
]);
2246 if (likely(__netif_rx_schedule_prep(dev0
)))
2247 __netif_rx_schedule(dev0
);
2252 #ifdef CONFIG_NET_POLL_CONTROLLER
2253 static void sky2_netpoll(struct net_device
*dev
)
2255 struct sky2_port
*sky2
= netdev_priv(dev
);
2256 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2258 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2259 __netif_rx_schedule(dev0
);
2263 /* Chip internal frequency for clock calculations */
2264 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2266 switch (hw
->chip_id
) {
2267 case CHIP_ID_YUKON_EC
:
2268 case CHIP_ID_YUKON_EC_U
:
2269 return 125; /* 125 Mhz */
2270 case CHIP_ID_YUKON_FE
:
2271 return 100; /* 100 Mhz */
2272 default: /* YUKON_XL */
2273 return 156; /* 156 Mhz */
2277 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2279 return sky2_mhz(hw
) * us
;
2282 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2284 return clk
/ sky2_mhz(hw
);
2288 static int sky2_reset(struct sky2_hw
*hw
)
2295 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2297 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2298 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2299 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2300 pci_name(hw
->pdev
), hw
->chip_id
);
2304 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2306 /* This rev is really old, and requires untested workarounds */
2307 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2308 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2309 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2310 hw
->chip_id
, hw
->chip_rev
);
2315 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2316 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2317 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2321 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2322 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2324 /* clear PCI errors, if any */
2325 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2327 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2328 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2331 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2333 /* clear any PEX errors */
2334 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
)) {
2335 hw
->err_cap
= pci_find_ext_capability(hw
->pdev
, PCI_EXT_CAP_ID_ERR
);
2337 sky2_pci_write32(hw
,
2338 hw
->err_cap
+ PCI_ERR_UNCOR_STATUS
,
2342 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2344 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2345 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2346 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2350 sky2_set_power_state(hw
, PCI_D0
);
2352 for (i
= 0; i
< hw
->ports
; i
++) {
2353 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2354 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2357 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2359 /* Clear I2C IRQ noise */
2360 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2362 /* turn off hardware timer (unused) */
2363 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2364 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2366 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2368 /* Turn off descriptor polling */
2369 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2371 /* Turn off receive timestamp */
2372 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2373 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2375 /* enable the Tx Arbiters */
2376 for (i
= 0; i
< hw
->ports
; i
++)
2377 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2379 /* Initialize ram interface */
2380 for (i
= 0; i
< hw
->ports
; i
++) {
2381 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2383 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2384 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2385 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2386 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2387 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2388 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2389 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2390 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2391 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2392 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2393 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2394 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2397 msk
= Y2_HWE_ALL_MASK
;
2399 msk
&= ~Y2_IS_PCI_EXP
;
2400 sky2_write32(hw
, B0_HWE_IMSK
, msk
);
2402 for (i
= 0; i
< hw
->ports
; i
++)
2403 sky2_gmac_reset(hw
, i
);
2405 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2408 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2409 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2411 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2412 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2414 /* Set the list last index */
2415 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2417 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2418 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2420 /* set Status-FIFO ISR watermark */
2421 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2422 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2424 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2426 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2427 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2428 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2430 /* enable status unit */
2431 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2433 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2434 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2435 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2440 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2442 if (sky2_is_copper(hw
)) {
2443 u32 modes
= SUPPORTED_10baseT_Half
2444 | SUPPORTED_10baseT_Full
2445 | SUPPORTED_100baseT_Half
2446 | SUPPORTED_100baseT_Full
2447 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2449 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2450 modes
|= SUPPORTED_1000baseT_Half
2451 | SUPPORTED_1000baseT_Full
;
2454 return SUPPORTED_1000baseT_Half
2455 | SUPPORTED_1000baseT_Full
2460 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2462 struct sky2_port
*sky2
= netdev_priv(dev
);
2463 struct sky2_hw
*hw
= sky2
->hw
;
2465 ecmd
->transceiver
= XCVR_INTERNAL
;
2466 ecmd
->supported
= sky2_supported_modes(hw
);
2467 ecmd
->phy_address
= PHY_ADDR_MARV
;
2468 if (sky2_is_copper(hw
)) {
2469 ecmd
->supported
= SUPPORTED_10baseT_Half
2470 | SUPPORTED_10baseT_Full
2471 | SUPPORTED_100baseT_Half
2472 | SUPPORTED_100baseT_Full
2473 | SUPPORTED_1000baseT_Half
2474 | SUPPORTED_1000baseT_Full
2475 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2476 ecmd
->port
= PORT_TP
;
2477 ecmd
->speed
= sky2
->speed
;
2479 ecmd
->speed
= SPEED_1000
;
2480 ecmd
->port
= PORT_FIBRE
;
2483 ecmd
->advertising
= sky2
->advertising
;
2484 ecmd
->autoneg
= sky2
->autoneg
;
2485 ecmd
->duplex
= sky2
->duplex
;
2489 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2491 struct sky2_port
*sky2
= netdev_priv(dev
);
2492 const struct sky2_hw
*hw
= sky2
->hw
;
2493 u32 supported
= sky2_supported_modes(hw
);
2495 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2496 ecmd
->advertising
= supported
;
2502 switch (ecmd
->speed
) {
2504 if (ecmd
->duplex
== DUPLEX_FULL
)
2505 setting
= SUPPORTED_1000baseT_Full
;
2506 else if (ecmd
->duplex
== DUPLEX_HALF
)
2507 setting
= SUPPORTED_1000baseT_Half
;
2512 if (ecmd
->duplex
== DUPLEX_FULL
)
2513 setting
= SUPPORTED_100baseT_Full
;
2514 else if (ecmd
->duplex
== DUPLEX_HALF
)
2515 setting
= SUPPORTED_100baseT_Half
;
2521 if (ecmd
->duplex
== DUPLEX_FULL
)
2522 setting
= SUPPORTED_10baseT_Full
;
2523 else if (ecmd
->duplex
== DUPLEX_HALF
)
2524 setting
= SUPPORTED_10baseT_Half
;
2532 if ((setting
& supported
) == 0)
2535 sky2
->speed
= ecmd
->speed
;
2536 sky2
->duplex
= ecmd
->duplex
;
2539 sky2
->autoneg
= ecmd
->autoneg
;
2540 sky2
->advertising
= ecmd
->advertising
;
2542 if (netif_running(dev
))
2543 sky2_phy_reinit(sky2
);
2548 static void sky2_get_drvinfo(struct net_device
*dev
,
2549 struct ethtool_drvinfo
*info
)
2551 struct sky2_port
*sky2
= netdev_priv(dev
);
2553 strcpy(info
->driver
, DRV_NAME
);
2554 strcpy(info
->version
, DRV_VERSION
);
2555 strcpy(info
->fw_version
, "N/A");
2556 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2559 static const struct sky2_stat
{
2560 char name
[ETH_GSTRING_LEN
];
2563 { "tx_bytes", GM_TXO_OK_HI
},
2564 { "rx_bytes", GM_RXO_OK_HI
},
2565 { "tx_broadcast", GM_TXF_BC_OK
},
2566 { "rx_broadcast", GM_RXF_BC_OK
},
2567 { "tx_multicast", GM_TXF_MC_OK
},
2568 { "rx_multicast", GM_RXF_MC_OK
},
2569 { "tx_unicast", GM_TXF_UC_OK
},
2570 { "rx_unicast", GM_RXF_UC_OK
},
2571 { "tx_mac_pause", GM_TXF_MPAUSE
},
2572 { "rx_mac_pause", GM_RXF_MPAUSE
},
2573 { "collisions", GM_TXF_COL
},
2574 { "late_collision",GM_TXF_LAT_COL
},
2575 { "aborted", GM_TXF_ABO_COL
},
2576 { "single_collisions", GM_TXF_SNG_COL
},
2577 { "multi_collisions", GM_TXF_MUL_COL
},
2579 { "rx_short", GM_RXF_SHT
},
2580 { "rx_runt", GM_RXE_FRAG
},
2581 { "rx_64_byte_packets", GM_RXF_64B
},
2582 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2583 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2584 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2585 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2586 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2587 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2588 { "rx_too_long", GM_RXF_LNG_ERR
},
2589 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2590 { "rx_jabber", GM_RXF_JAB_PKT
},
2591 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2593 { "tx_64_byte_packets", GM_TXF_64B
},
2594 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2595 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2596 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2597 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2598 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2599 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2600 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2603 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2605 struct sky2_port
*sky2
= netdev_priv(dev
);
2607 return sky2
->rx_csum
;
2610 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2612 struct sky2_port
*sky2
= netdev_priv(dev
);
2614 sky2
->rx_csum
= data
;
2616 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2617 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2622 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2624 struct sky2_port
*sky2
= netdev_priv(netdev
);
2625 return sky2
->msg_enable
;
2628 static int sky2_nway_reset(struct net_device
*dev
)
2630 struct sky2_port
*sky2
= netdev_priv(dev
);
2632 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2635 sky2_phy_reinit(sky2
);
2640 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2642 struct sky2_hw
*hw
= sky2
->hw
;
2643 unsigned port
= sky2
->port
;
2646 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2647 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2648 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2649 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2651 for (i
= 2; i
< count
; i
++)
2652 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2655 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2657 struct sky2_port
*sky2
= netdev_priv(netdev
);
2658 sky2
->msg_enable
= value
;
2661 static int sky2_get_stats_count(struct net_device
*dev
)
2663 return ARRAY_SIZE(sky2_stats
);
2666 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2667 struct ethtool_stats
*stats
, u64
* data
)
2669 struct sky2_port
*sky2
= netdev_priv(dev
);
2671 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2674 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2678 switch (stringset
) {
2680 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2681 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2682 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2687 /* Use hardware MIB variables for critical path statistics and
2688 * transmit feedback not reported at interrupt.
2689 * Other errors are accounted for in interrupt handler.
2691 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2693 struct sky2_port
*sky2
= netdev_priv(dev
);
2696 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2698 sky2
->net_stats
.tx_bytes
= data
[0];
2699 sky2
->net_stats
.rx_bytes
= data
[1];
2700 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2701 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2702 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2703 sky2
->net_stats
.collisions
= data
[10];
2704 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2706 return &sky2
->net_stats
;
2709 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2711 struct sky2_port
*sky2
= netdev_priv(dev
);
2712 struct sky2_hw
*hw
= sky2
->hw
;
2713 unsigned port
= sky2
->port
;
2714 const struct sockaddr
*addr
= p
;
2716 if (!is_valid_ether_addr(addr
->sa_data
))
2717 return -EADDRNOTAVAIL
;
2719 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2720 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2721 dev
->dev_addr
, ETH_ALEN
);
2722 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2723 dev
->dev_addr
, ETH_ALEN
);
2725 /* virtual address for data */
2726 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2728 /* physical address: used for pause frames */
2729 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2734 static void sky2_set_multicast(struct net_device
*dev
)
2736 struct sky2_port
*sky2
= netdev_priv(dev
);
2737 struct sky2_hw
*hw
= sky2
->hw
;
2738 unsigned port
= sky2
->port
;
2739 struct dev_mc_list
*list
= dev
->mc_list
;
2743 memset(filter
, 0, sizeof(filter
));
2745 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2746 reg
|= GM_RXCR_UCF_ENA
;
2748 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2749 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2750 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2751 memset(filter
, 0xff, sizeof(filter
));
2752 else if (dev
->mc_count
== 0) /* no multicast */
2753 reg
&= ~GM_RXCR_MCF_ENA
;
2756 reg
|= GM_RXCR_MCF_ENA
;
2758 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2759 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2760 filter
[bit
/ 8] |= 1 << (bit
% 8);
2764 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2765 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2766 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2767 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2768 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2769 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2770 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2771 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2773 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2776 /* Can have one global because blinking is controlled by
2777 * ethtool and that is always under RTNL mutex
2779 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2783 switch (hw
->chip_id
) {
2784 case CHIP_ID_YUKON_XL
:
2785 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2786 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2787 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2788 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2789 PHY_M_LEDC_INIT_CTRL(7) |
2790 PHY_M_LEDC_STA1_CTRL(7) |
2791 PHY_M_LEDC_STA0_CTRL(7))
2794 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2798 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2799 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2800 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2801 PHY_M_LED_MO_10(MO_LED_ON
) |
2802 PHY_M_LED_MO_100(MO_LED_ON
) |
2803 PHY_M_LED_MO_1000(MO_LED_ON
) |
2804 PHY_M_LED_MO_RX(MO_LED_ON
)
2805 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2806 PHY_M_LED_MO_10(MO_LED_OFF
) |
2807 PHY_M_LED_MO_100(MO_LED_OFF
) |
2808 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2809 PHY_M_LED_MO_RX(MO_LED_OFF
));
2814 /* blink LED's for finding board */
2815 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2817 struct sky2_port
*sky2
= netdev_priv(dev
);
2818 struct sky2_hw
*hw
= sky2
->hw
;
2819 unsigned port
= sky2
->port
;
2820 u16 ledctrl
, ledover
= 0;
2825 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2826 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2830 /* save initial values */
2831 spin_lock_bh(&sky2
->phy_lock
);
2832 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2833 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2834 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2835 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2836 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2838 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2839 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2843 while (!interrupted
&& ms
> 0) {
2844 sky2_led(hw
, port
, onoff
);
2847 spin_unlock_bh(&sky2
->phy_lock
);
2848 interrupted
= msleep_interruptible(250);
2849 spin_lock_bh(&sky2
->phy_lock
);
2854 /* resume regularly scheduled programming */
2855 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2856 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2857 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2858 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2859 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2861 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2862 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2864 spin_unlock_bh(&sky2
->phy_lock
);
2869 static void sky2_get_pauseparam(struct net_device
*dev
,
2870 struct ethtool_pauseparam
*ecmd
)
2872 struct sky2_port
*sky2
= netdev_priv(dev
);
2874 ecmd
->tx_pause
= sky2
->tx_pause
;
2875 ecmd
->rx_pause
= sky2
->rx_pause
;
2876 ecmd
->autoneg
= sky2
->autoneg
;
2879 static int sky2_set_pauseparam(struct net_device
*dev
,
2880 struct ethtool_pauseparam
*ecmd
)
2882 struct sky2_port
*sky2
= netdev_priv(dev
);
2884 sky2
->autoneg
= ecmd
->autoneg
;
2885 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2886 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2888 sky2_phy_reinit(sky2
);
2893 static int sky2_get_coalesce(struct net_device
*dev
,
2894 struct ethtool_coalesce
*ecmd
)
2896 struct sky2_port
*sky2
= netdev_priv(dev
);
2897 struct sky2_hw
*hw
= sky2
->hw
;
2899 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2900 ecmd
->tx_coalesce_usecs
= 0;
2902 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2903 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2905 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2907 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2908 ecmd
->rx_coalesce_usecs
= 0;
2910 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2911 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2913 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2915 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2916 ecmd
->rx_coalesce_usecs_irq
= 0;
2918 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2919 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2922 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2927 /* Note: this affect both ports */
2928 static int sky2_set_coalesce(struct net_device
*dev
,
2929 struct ethtool_coalesce
*ecmd
)
2931 struct sky2_port
*sky2
= netdev_priv(dev
);
2932 struct sky2_hw
*hw
= sky2
->hw
;
2933 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2935 if (ecmd
->tx_coalesce_usecs
> tmax
||
2936 ecmd
->rx_coalesce_usecs
> tmax
||
2937 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2940 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2942 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2944 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2947 if (ecmd
->tx_coalesce_usecs
== 0)
2948 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2950 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2951 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2952 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2954 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2956 if (ecmd
->rx_coalesce_usecs
== 0)
2957 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2959 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2960 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2961 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2963 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2965 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2966 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2968 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2969 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2970 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2972 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2976 static void sky2_get_ringparam(struct net_device
*dev
,
2977 struct ethtool_ringparam
*ering
)
2979 struct sky2_port
*sky2
= netdev_priv(dev
);
2981 ering
->rx_max_pending
= RX_MAX_PENDING
;
2982 ering
->rx_mini_max_pending
= 0;
2983 ering
->rx_jumbo_max_pending
= 0;
2984 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2986 ering
->rx_pending
= sky2
->rx_pending
;
2987 ering
->rx_mini_pending
= 0;
2988 ering
->rx_jumbo_pending
= 0;
2989 ering
->tx_pending
= sky2
->tx_pending
;
2992 static int sky2_set_ringparam(struct net_device
*dev
,
2993 struct ethtool_ringparam
*ering
)
2995 struct sky2_port
*sky2
= netdev_priv(dev
);
2998 if (ering
->rx_pending
> RX_MAX_PENDING
||
2999 ering
->rx_pending
< 8 ||
3000 ering
->tx_pending
< MAX_SKB_TX_LE
||
3001 ering
->tx_pending
> TX_RING_SIZE
- 1)
3004 if (netif_running(dev
))
3007 sky2
->rx_pending
= ering
->rx_pending
;
3008 sky2
->tx_pending
= ering
->tx_pending
;
3010 if (netif_running(dev
)) {
3015 sky2_set_multicast(dev
);
3021 static int sky2_get_regs_len(struct net_device
*dev
)
3027 * Returns copy of control register region
3028 * Note: access to the RAM address register set will cause timeouts.
3030 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3033 const struct sky2_port
*sky2
= netdev_priv(dev
);
3034 const void __iomem
*io
= sky2
->hw
->regs
;
3036 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3038 memset(p
, 0, regs
->len
);
3040 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3042 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3044 regs
->len
- B3_RI_WTO_R1
);
3047 static const struct ethtool_ops sky2_ethtool_ops
= {
3048 .get_settings
= sky2_get_settings
,
3049 .set_settings
= sky2_set_settings
,
3050 .get_drvinfo
= sky2_get_drvinfo
,
3051 .get_msglevel
= sky2_get_msglevel
,
3052 .set_msglevel
= sky2_set_msglevel
,
3053 .nway_reset
= sky2_nway_reset
,
3054 .get_regs_len
= sky2_get_regs_len
,
3055 .get_regs
= sky2_get_regs
,
3056 .get_link
= ethtool_op_get_link
,
3057 .get_sg
= ethtool_op_get_sg
,
3058 .set_sg
= ethtool_op_set_sg
,
3059 .get_tx_csum
= ethtool_op_get_tx_csum
,
3060 .set_tx_csum
= ethtool_op_set_tx_csum
,
3061 .get_tso
= ethtool_op_get_tso
,
3062 .set_tso
= ethtool_op_set_tso
,
3063 .get_rx_csum
= sky2_get_rx_csum
,
3064 .set_rx_csum
= sky2_set_rx_csum
,
3065 .get_strings
= sky2_get_strings
,
3066 .get_coalesce
= sky2_get_coalesce
,
3067 .set_coalesce
= sky2_set_coalesce
,
3068 .get_ringparam
= sky2_get_ringparam
,
3069 .set_ringparam
= sky2_set_ringparam
,
3070 .get_pauseparam
= sky2_get_pauseparam
,
3071 .set_pauseparam
= sky2_set_pauseparam
,
3072 .phys_id
= sky2_phys_id
,
3073 .get_stats_count
= sky2_get_stats_count
,
3074 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3075 .get_perm_addr
= ethtool_op_get_perm_addr
,
3078 /* Initialize network device */
3079 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3080 unsigned port
, int highmem
)
3082 struct sky2_port
*sky2
;
3083 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3086 printk(KERN_ERR
"sky2 etherdev alloc failed");
3090 SET_MODULE_OWNER(dev
);
3091 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3092 dev
->irq
= hw
->pdev
->irq
;
3093 dev
->open
= sky2_up
;
3094 dev
->stop
= sky2_down
;
3095 dev
->do_ioctl
= sky2_ioctl
;
3096 dev
->hard_start_xmit
= sky2_xmit_frame
;
3097 dev
->get_stats
= sky2_get_stats
;
3098 dev
->set_multicast_list
= sky2_set_multicast
;
3099 dev
->set_mac_address
= sky2_set_mac_address
;
3100 dev
->change_mtu
= sky2_change_mtu
;
3101 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3102 dev
->tx_timeout
= sky2_tx_timeout
;
3103 dev
->watchdog_timeo
= TX_WATCHDOG
;
3105 dev
->poll
= sky2_poll
;
3106 dev
->weight
= NAPI_WEIGHT
;
3107 #ifdef CONFIG_NET_POLL_CONTROLLER
3108 dev
->poll_controller
= sky2_netpoll
;
3111 sky2
= netdev_priv(dev
);
3114 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3116 /* Auto speed and flow control */
3117 sky2
->autoneg
= AUTONEG_ENABLE
;
3122 sky2
->advertising
= sky2_supported_modes(hw
);
3125 spin_lock_init(&sky2
->phy_lock
);
3126 sky2
->tx_pending
= TX_DEF_PENDING
;
3127 sky2
->rx_pending
= RX_DEF_PENDING
;
3128 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3130 hw
->dev
[port
] = dev
;
3134 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3135 dev
->features
|= NETIF_F_TSO
;
3137 dev
->features
|= NETIF_F_HIGHDMA
;
3138 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3140 #ifdef SKY2_VLAN_TAG_USED
3141 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3142 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3143 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3146 /* read the mac address */
3147 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3148 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3150 /* device is off until link detection */
3151 netif_carrier_off(dev
);
3152 netif_stop_queue(dev
);
3157 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3159 const struct sky2_port
*sky2
= netdev_priv(dev
);
3161 if (netif_msg_probe(sky2
))
3162 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3164 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3165 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3168 /* Handle software interrupt used during MSI test */
3169 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3170 struct pt_regs
*regs
)
3172 struct sky2_hw
*hw
= dev_id
;
3173 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3178 if (status
& Y2_IS_IRQ_SW
) {
3179 hw
->msi_detected
= 1;
3180 wake_up(&hw
->msi_wait
);
3181 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3183 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3188 /* Test interrupt path by forcing a a software IRQ */
3189 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3191 struct pci_dev
*pdev
= hw
->pdev
;
3194 init_waitqueue_head (&hw
->msi_wait
);
3196 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3198 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3200 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3201 pci_name(pdev
), pdev
->irq
);
3205 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3206 sky2_read8(hw
, B0_CTST
);
3208 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3210 if (!hw
->msi_detected
) {
3211 /* MSI test failed, go back to INTx mode */
3212 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3213 "switching to INTx mode. Please report this failure to "
3214 "the PCI maintainer and include system chipset information.\n",
3218 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3221 sky2_write32(hw
, B0_IMSK
, 0);
3223 free_irq(pdev
->irq
, hw
);
3228 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3229 const struct pci_device_id
*ent
)
3231 struct net_device
*dev
, *dev1
= NULL
;
3233 int err
, pm_cap
, using_dac
= 0;
3235 err
= pci_enable_device(pdev
);
3237 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3242 err
= pci_request_regions(pdev
, DRV_NAME
);
3244 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3249 pci_set_master(pdev
);
3251 /* Find power-management capability. */
3252 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3254 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3257 goto err_out_free_regions
;
3260 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3261 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3263 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3265 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3266 "for consistent allocations\n", pci_name(pdev
));
3267 goto err_out_free_regions
;
3271 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3273 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3275 goto err_out_free_regions
;
3280 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3282 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3284 goto err_out_free_regions
;
3289 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3291 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3293 goto err_out_free_hw
;
3295 hw
->pm_cap
= pm_cap
;
3298 /* The sk98lin vendor driver uses hardware byte swapping but
3299 * this driver uses software swapping.
3303 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3304 reg
&= ~PCI_REV_DESC
;
3305 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3309 /* ring for status responses */
3310 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3313 goto err_out_iounmap
;
3315 err
= sky2_reset(hw
);
3317 goto err_out_iounmap
;
3319 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3320 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3321 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3322 hw
->chip_id
, hw
->chip_rev
);
3324 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3326 goto err_out_free_pci
;
3328 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3329 err
= sky2_test_msi(hw
);
3330 if (err
== -EOPNOTSUPP
)
3331 pci_disable_msi(pdev
);
3333 goto err_out_free_netdev
;
3336 err
= register_netdev(dev
);
3338 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3340 goto err_out_free_netdev
;
3343 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, dev
->name
, hw
);
3345 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3346 pci_name(pdev
), pdev
->irq
);
3347 goto err_out_unregister
;
3349 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3351 sky2_show_addr(dev
);
3353 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3354 if (register_netdev(dev1
) == 0)
3355 sky2_show_addr(dev1
);
3357 /* Failure to register second port need not be fatal */
3358 printk(KERN_WARNING PFX
3359 "register of second port failed\n");
3365 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3366 sky2_idle_start(hw
);
3368 pci_set_drvdata(pdev
, hw
);
3373 pci_disable_msi(pdev
);
3374 unregister_netdev(dev
);
3375 err_out_free_netdev
:
3378 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3379 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3384 err_out_free_regions
:
3385 pci_release_regions(pdev
);
3386 pci_disable_device(pdev
);
3391 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3393 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3394 struct net_device
*dev0
, *dev1
;
3399 del_timer_sync(&hw
->idle_timer
);
3401 sky2_write32(hw
, B0_IMSK
, 0);
3402 synchronize_irq(hw
->pdev
->irq
);
3407 unregister_netdev(dev1
);
3408 unregister_netdev(dev0
);
3410 sky2_set_power_state(hw
, PCI_D3hot
);
3411 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3412 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3413 sky2_read8(hw
, B0_CTST
);
3415 free_irq(pdev
->irq
, hw
);
3416 pci_disable_msi(pdev
);
3417 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3418 pci_release_regions(pdev
);
3419 pci_disable_device(pdev
);
3427 pci_set_drvdata(pdev
, NULL
);
3431 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3433 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3435 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3437 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3440 del_timer_sync(&hw
->idle_timer
);
3441 netif_poll_disable(hw
->dev
[0]);
3443 for (i
= 0; i
< hw
->ports
; i
++) {
3444 struct net_device
*dev
= hw
->dev
[i
];
3446 if (netif_running(dev
)) {
3448 netif_device_detach(dev
);
3452 sky2_write32(hw
, B0_IMSK
, 0);
3453 pci_save_state(pdev
);
3454 sky2_set_power_state(hw
, pstate
);
3458 static int sky2_resume(struct pci_dev
*pdev
)
3460 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3463 pci_restore_state(pdev
);
3464 pci_enable_wake(pdev
, PCI_D0
, 0);
3465 sky2_set_power_state(hw
, PCI_D0
);
3467 err
= sky2_reset(hw
);
3471 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3473 for (i
= 0; i
< hw
->ports
; i
++) {
3474 struct net_device
*dev
= hw
->dev
[i
];
3475 if (netif_running(dev
)) {
3476 netif_device_attach(dev
);
3480 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3488 netif_poll_enable(hw
->dev
[0]);
3489 sky2_idle_start(hw
);
3495 static struct pci_driver sky2_driver
= {
3497 .id_table
= sky2_id_table
,
3498 .probe
= sky2_probe
,
3499 .remove
= __devexit_p(sky2_remove
),
3501 .suspend
= sky2_suspend
,
3502 .resume
= sky2_resume
,
3506 static int __init
sky2_init_module(void)
3508 return pci_register_driver(&sky2_driver
);
3511 static void __exit
sky2_cleanup_module(void)
3513 pci_unregister_driver(&sky2_driver
);
3516 module_init(sky2_init_module
);
3517 module_exit(sky2_cleanup_module
);
3519 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3520 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3521 MODULE_LICENSE("GPL");
3522 MODULE_VERSION(DRV_VERSION
);