2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
29 struct cplb_entry icplb_tbl
[MAX_CPLBS
];
30 struct cplb_entry dcplb_tbl
[MAX_CPLBS
];
32 int first_switched_icplb
, first_switched_dcplb
;
35 void __init
generate_cpl_tables(void)
39 unsigned long d_data
, i_data
;
40 unsigned long d_cache
= 0, i_cache
= 0;
42 #ifdef CONFIG_BFIN_ICACHE
43 i_cache
= CPLB_L1_CHBL
| ANOMALY_05000158_WORKAROUND
;
46 #ifdef CONFIG_BFIN_DCACHE
47 d_cache
= CPLB_L1_CHBL
;
48 #ifdef CONFIG_BLKFIN_WT
49 d_cache
|= CPLB_L1_AOW
| CPLB_WT
;
54 /* Set up the zero page. */
55 dcplb_tbl
[i_d
].addr
= 0;
56 dcplb_tbl
[i_d
++].data
= SDRAM_OOPS
| PAGE_SIZE_1KB
;
59 icplb_tbl
[i_i
].addr
= 0;
60 icplb_tbl
[i_i
++].data
= i_cache
| CPLB_USER_RD
| PAGE_SIZE_4KB
;
63 /* Cover kernel memory with 4M pages. */
65 d_data
= d_cache
| CPLB_SUPV_WR
| CPLB_VALID
| PAGE_SIZE_4MB
| CPLB_DIRTY
;
66 i_data
= i_cache
| CPLB_VALID
| CPLB_PORTPRIO
| PAGE_SIZE_4MB
;
68 for (; addr
< memory_start
; addr
+= 4 * 1024 * 1024) {
69 dcplb_tbl
[i_d
].addr
= addr
;
70 dcplb_tbl
[i_d
++].data
= d_data
;
71 icplb_tbl
[i_i
].addr
= addr
;
72 icplb_tbl
[i_i
++].data
= i_data
| (addr
== 0 ? CPLB_USER_RD
: 0);
75 /* Cover L1 memory. One 4M area for code and data each is enough. */
76 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
77 dcplb_tbl
[i_d
].addr
= L1_DATA_A_START
;
78 dcplb_tbl
[i_d
++].data
= L1_DMEMORY
| PAGE_SIZE_4MB
;
80 icplb_tbl
[i_i
].addr
= L1_CODE_START
;
81 icplb_tbl
[i_i
++].data
= L1_IMEMORY
| PAGE_SIZE_4MB
;
83 first_mask_dcplb
= i_d
;
84 first_switched_dcplb
= i_d
+ (1 << page_mask_order
);
85 first_switched_icplb
= i_i
;
87 while (i_d
< MAX_CPLBS
)
88 dcplb_tbl
[i_d
++].data
= 0;
89 while (i_i
< MAX_CPLBS
)
90 icplb_tbl
[i_i
++].data
= 0;