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ahci: clean up PORT_IRQ_BAD_PMP enabling
[linux-2.6/linux-loongson.git] / drivers / ata / ahci.c
blob6633c7422fc48d1389bba3f04048d15e7b545113
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "3.0"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82 board_ahci_sb600 = 3,
83 board_ahci_mv = 4,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
146 PORT_IRQ_PHYRDY |
147 PORT_IRQ_UNK_FIS |
148 PORT_IRQ_BAD_PMP,
149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
150 PORT_IRQ_TF_ERR |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
155
156 /* PORT_CMD bits */
157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
162 PORT_CMD_CLO = (1 << 3), /* Command list override */
163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
166
167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
171
172 /* hpriv->flags bits */
173 AHCI_HFLAG_NO_NCQ = (1 << 0),
174 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
175 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
176 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
177 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
178 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
179 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
180
181 /* ap->flags bits */
182 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
183
184 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
185 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
186 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
187 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
188 };
189
190 struct ahci_cmd_hdr {
191 u32 opts;
192 u32 status;
193 u32 tbl_addr;
194 u32 tbl_addr_hi;
195 u32 reserved[4];
196 };
197
198 struct ahci_sg {
199 u32 addr;
200 u32 addr_hi;
201 u32 reserved;
202 u32 flags_size;
203 };
204
205 struct ahci_host_priv {
206 unsigned int flags; /* AHCI_HFLAG_* */
207 u32 cap; /* cap to use */
208 u32 port_map; /* port map to use */
209 u32 saved_cap; /* saved initial cap */
210 u32 saved_port_map; /* saved initial port_map */
211 };
212
213 struct ahci_port_priv {
214 struct ata_link *active_link;
215 struct ahci_cmd_hdr *cmd_slot;
216 dma_addr_t cmd_slot_dma;
217 void *cmd_tbl;
218 dma_addr_t cmd_tbl_dma;
219 void *rx_fis;
220 dma_addr_t rx_fis_dma;
221 /* for NCQ spurious interrupt analysis */
222 unsigned int ncq_saw_d2h:1;
223 unsigned int ncq_saw_dmas:1;
224 unsigned int ncq_saw_sdb:1;
225 u32 intr_mask; /* interrupts to enable */
226 };
227
228 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
229 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
230 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
231 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
232 static void ahci_irq_clear(struct ata_port *ap);
233 static int ahci_port_start(struct ata_port *ap);
234 static void ahci_port_stop(struct ata_port *ap);
235 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
236 static void ahci_qc_prep(struct ata_queued_cmd *qc);
237 static u8 ahci_check_status(struct ata_port *ap);
238 static void ahci_freeze(struct ata_port *ap);
239 static void ahci_thaw(struct ata_port *ap);
240 static void ahci_pmp_attach(struct ata_port *ap);
241 static void ahci_pmp_detach(struct ata_port *ap);
242 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
243 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
244 static void ahci_error_handler(struct ata_port *ap);
245 static void ahci_vt8251_error_handler(struct ata_port *ap);
246 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
247 static int ahci_port_resume(struct ata_port *ap);
248 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
249 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
250 u32 opts);
251 #ifdef CONFIG_PM
252 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
253 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
254 static int ahci_pci_device_resume(struct pci_dev *pdev);
255 #endif
256
257 static struct scsi_host_template ahci_sht = {
258 .module = THIS_MODULE,
259 .name = DRV_NAME,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
262 .change_queue_depth = ata_scsi_change_queue_depth,
263 .can_queue = AHCI_MAX_CMDS - 1,
264 .this_id = ATA_SHT_THIS_ID,
265 .sg_tablesize = AHCI_MAX_SG,
266 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
267 .emulated = ATA_SHT_EMULATED,
268 .use_clustering = AHCI_USE_CLUSTERING,
269 .proc_name = DRV_NAME,
270 .dma_boundary = AHCI_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config,
272 .slave_destroy = ata_scsi_slave_destroy,
273 .bios_param = ata_std_bios_param,
274 };
275
276 static const struct ata_port_operations ahci_ops = {
277 .check_status = ahci_check_status,
278 .check_altstatus = ahci_check_status,
279 .dev_select = ata_noop_dev_select,
280
281 .tf_read = ahci_tf_read,
282
283 .qc_defer = sata_pmp_qc_defer_cmd_switch,
284 .qc_prep = ahci_qc_prep,
285 .qc_issue = ahci_qc_issue,
286
287 .irq_clear = ahci_irq_clear,
288
289 .scr_read = ahci_scr_read,
290 .scr_write = ahci_scr_write,
291
292 .freeze = ahci_freeze,
293 .thaw = ahci_thaw,
294
295 .error_handler = ahci_error_handler,
296 .post_internal_cmd = ahci_post_internal_cmd,
297
298 .pmp_attach = ahci_pmp_attach,
299 .pmp_detach = ahci_pmp_detach,
300 .pmp_read = ahci_pmp_read,
301 .pmp_write = ahci_pmp_write,
302
303 #ifdef CONFIG_PM
304 .port_suspend = ahci_port_suspend,
305 .port_resume = ahci_port_resume,
306 #endif
307
308 .port_start = ahci_port_start,
309 .port_stop = ahci_port_stop,
310 };
311
312 static const struct ata_port_operations ahci_vt8251_ops = {
313 .check_status = ahci_check_status,
314 .check_altstatus = ahci_check_status,
315 .dev_select = ata_noop_dev_select,
316
317 .tf_read = ahci_tf_read,
318
319 .qc_defer = sata_pmp_qc_defer_cmd_switch,
320 .qc_prep = ahci_qc_prep,
321 .qc_issue = ahci_qc_issue,
322
323 .irq_clear = ahci_irq_clear,
324
325 .scr_read = ahci_scr_read,
326 .scr_write = ahci_scr_write,
327
328 .freeze = ahci_freeze,
329 .thaw = ahci_thaw,
330
331 .error_handler = ahci_vt8251_error_handler,
332 .post_internal_cmd = ahci_post_internal_cmd,
333
334 .pmp_attach = ahci_pmp_attach,
335 .pmp_detach = ahci_pmp_detach,
336 .pmp_read = ahci_pmp_read,
337 .pmp_write = ahci_pmp_write,
338
339 #ifdef CONFIG_PM
340 .port_suspend = ahci_port_suspend,
341 .port_resume = ahci_port_resume,
342 #endif
343
344 .port_start = ahci_port_start,
345 .port_stop = ahci_port_stop,
346 };
347
348 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
349
350 static const struct ata_port_info ahci_port_info[] = {
351 /* board_ahci */
352 {
353 .flags = AHCI_FLAG_COMMON,
354 .link_flags = AHCI_LFLAG_COMMON,
355 .pio_mask = 0x1f, /* pio0-4 */
356 .udma_mask = ATA_UDMA6,
357 .port_ops = &ahci_ops,
358 },
359 /* board_ahci_vt8251 */
360 {
361 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
362 .flags = AHCI_FLAG_COMMON,
363 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
364 .pio_mask = 0x1f, /* pio0-4 */
365 .udma_mask = ATA_UDMA6,
366 .port_ops = &ahci_vt8251_ops,
367 },
368 /* board_ahci_ign_iferr */
369 {
370 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
371 .flags = AHCI_FLAG_COMMON,
372 .link_flags = AHCI_LFLAG_COMMON,
373 .pio_mask = 0x1f, /* pio0-4 */
374 .udma_mask = ATA_UDMA6,
375 .port_ops = &ahci_ops,
376 },
377 /* board_ahci_sb600 */
378 {
379 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
380 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
381 .flags = AHCI_FLAG_COMMON,
382 .link_flags = AHCI_LFLAG_COMMON,
383 .pio_mask = 0x1f, /* pio0-4 */
384 .udma_mask = ATA_UDMA6,
385 .port_ops = &ahci_ops,
386 },
387 /* board_ahci_mv */
388 {
389 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
390 AHCI_HFLAG_MV_PATA),
391 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
392 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
393 .link_flags = AHCI_LFLAG_COMMON,
394 .pio_mask = 0x1f, /* pio0-4 */
395 .udma_mask = ATA_UDMA6,
396 .port_ops = &ahci_ops,
397 },
398 };
399
400 static const struct pci_device_id ahci_pci_tbl[] = {
401 /* Intel */
402 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
403 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
404 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
405 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
406 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
407 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
408 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
409 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
410 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
411 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
412 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
413 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
414 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
415 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
416 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
417 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
418 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
420 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
422 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
423 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
425 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
426 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
427 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
428 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
429 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
430 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
431
432 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
433 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
434 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
435
436 /* ATI */
437 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
438 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
441 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
443 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
444
445 /* VIA */
446 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
447 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
448
449 /* NVIDIA */
450 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
502
503 /* SiS */
504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
507
508 /* Marvell */
509 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
510
511 /* Generic, PCI class code for AHCI */
512 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
513 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
514
515 { } /* terminate list */
516 };
517
518
519 static struct pci_driver ahci_pci_driver = {
520 .name = DRV_NAME,
521 .id_table = ahci_pci_tbl,
522 .probe = ahci_init_one,
523 .remove = ata_pci_remove_one,
524 #ifdef CONFIG_PM
525 .suspend = ahci_pci_device_suspend,
526 .resume = ahci_pci_device_resume,
527 #endif
528 };
529
530
531 static inline int ahci_nr_ports(u32 cap)
532 {
533 return (cap & 0x1f) + 1;
534 }
535
536 static inline void __iomem *__ahci_port_base(struct ata_host *host,
537 unsigned int port_no)
538 {
539 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
540
541 return mmio + 0x100 + (port_no * 0x80);
542 }
543
544 static inline void __iomem *ahci_port_base(struct ata_port *ap)
545 {
546 return __ahci_port_base(ap->host, ap->port_no);
547 }
548
549 /**
550 * ahci_save_initial_config - Save and fixup initial config values
551 * @pdev: target PCI device
552 * @hpriv: host private area to store config values
553 *
554 * Some registers containing configuration info might be setup by
555 * BIOS and might be cleared on reset. This function saves the
556 * initial values of those registers into @hpriv such that they
557 * can be restored after controller reset.
558 *
559 * If inconsistent, config values are fixed up by this function.
560 *
561 * LOCKING:
562 * None.
563 */
564 static void ahci_save_initial_config(struct pci_dev *pdev,
565 struct ahci_host_priv *hpriv)
566 {
567 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
568 u32 cap, port_map;
569 int i;
570
571 /* Values prefixed with saved_ are written back to host after
572 * reset. Values without are used for driver operation.
573 */
574 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
575 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
576
577 /* some chips have errata preventing 64bit use */
578 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
579 dev_printk(KERN_INFO, &pdev->dev,
580 "controller can't do 64bit DMA, forcing 32bit\n");
581 cap &= ~HOST_CAP_64;
582 }
583
584 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
585 dev_printk(KERN_INFO, &pdev->dev,
586 "controller can't do NCQ, turning off CAP_NCQ\n");
587 cap &= ~HOST_CAP_NCQ;
588 }
589
590 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
591 dev_printk(KERN_INFO, &pdev->dev,
592 "controller can't do PMP, turning off CAP_PMP\n");
593 cap &= ~HOST_CAP_PMP;
594 }
595
596 /*
597 * Temporary Marvell 6145 hack: PATA port presence
598 * is asserted through the standard AHCI port
599 * presence register, as bit 4 (counting from 0)
600 */
601 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
602 dev_printk(KERN_ERR, &pdev->dev,
603 "MV_AHCI HACK: port_map %x -> %x\n",
604 hpriv->port_map,
605 hpriv->port_map & 0xf);
606
607 port_map &= 0xf;
608 }
609
610 /* cross check port_map and cap.n_ports */
611 if (port_map) {
612 u32 tmp_port_map = port_map;
613 int n_ports = ahci_nr_ports(cap);
614
615 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
616 if (tmp_port_map & (1 << i)) {
617 n_ports--;
618 tmp_port_map &= ~(1 << i);
619 }
620 }
621
622 /* If n_ports and port_map are inconsistent, whine and
623 * clear port_map and let it be generated from n_ports.
624 */
625 if (n_ports || tmp_port_map) {
626 dev_printk(KERN_WARNING, &pdev->dev,
627 "nr_ports (%u) and implemented port map "
628 "(0x%x) don't match, using nr_ports\n",
629 ahci_nr_ports(cap), port_map);
630 port_map = 0;
631 }
632 }
633
634 /* fabricate port_map from cap.nr_ports */
635 if (!port_map) {
636 port_map = (1 << ahci_nr_ports(cap)) - 1;
637 dev_printk(KERN_WARNING, &pdev->dev,
638 "forcing PORTS_IMPL to 0x%x\n", port_map);
639
640 /* write the fixed up value to the PI register */
641 hpriv->saved_port_map = port_map;
642 }
643
644 /* record values to use during operation */
645 hpriv->cap = cap;
646 hpriv->port_map = port_map;
647 }
648
649 /**
650 * ahci_restore_initial_config - Restore initial config
651 * @host: target ATA host
652 *
653 * Restore initial config stored by ahci_save_initial_config().
654 *
655 * LOCKING:
656 * None.
657 */
658 static void ahci_restore_initial_config(struct ata_host *host)
659 {
660 struct ahci_host_priv *hpriv = host->private_data;
661 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
662
663 writel(hpriv->saved_cap, mmio + HOST_CAP);
664 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
665 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
666 }
667
668 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
669 {
670 static const int offset[] = {
671 [SCR_STATUS] = PORT_SCR_STAT,
672 [SCR_CONTROL] = PORT_SCR_CTL,
673 [SCR_ERROR] = PORT_SCR_ERR,
674 [SCR_ACTIVE] = PORT_SCR_ACT,
675 [SCR_NOTIFICATION] = PORT_SCR_NTF,
676 };
677 struct ahci_host_priv *hpriv = ap->host->private_data;
678
679 if (sc_reg < ARRAY_SIZE(offset) &&
680 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
681 return offset[sc_reg];
682 return 0;
683 }
684
685 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
686 {
687 void __iomem *port_mmio = ahci_port_base(ap);
688 int offset = ahci_scr_offset(ap, sc_reg);
689
690 if (offset) {
691 *val = readl(port_mmio + offset);
692 return 0;
693 }
694 return -EINVAL;
695 }
696
697 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
698 {
699 void __iomem *port_mmio = ahci_port_base(ap);
700 int offset = ahci_scr_offset(ap, sc_reg);
701
702 if (offset) {
703 writel(val, port_mmio + offset);
704 return 0;
705 }
706 return -EINVAL;
707 }
708
709 static void ahci_start_engine(struct ata_port *ap)
710 {
711 void __iomem *port_mmio = ahci_port_base(ap);
712 u32 tmp;
713
714 /* start DMA */
715 tmp = readl(port_mmio + PORT_CMD);
716 tmp |= PORT_CMD_START;
717 writel(tmp, port_mmio + PORT_CMD);
718 readl(port_mmio + PORT_CMD); /* flush */
719 }
720
721 static int ahci_stop_engine(struct ata_port *ap)
722 {
723 void __iomem *port_mmio = ahci_port_base(ap);
724 u32 tmp;
725
726 tmp = readl(port_mmio + PORT_CMD);
727
728 /* check if the HBA is idle */
729 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
730 return 0;
731
732 /* setting HBA to idle */
733 tmp &= ~PORT_CMD_START;
734 writel(tmp, port_mmio + PORT_CMD);
735
736 /* wait for engine to stop. This could be as long as 500 msec */
737 tmp = ata_wait_register(port_mmio + PORT_CMD,
738 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
739 if (tmp & PORT_CMD_LIST_ON)
740 return -EIO;
741
742 return 0;
743 }
744
745 static void ahci_start_fis_rx(struct ata_port *ap)
746 {
747 void __iomem *port_mmio = ahci_port_base(ap);
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 struct ahci_port_priv *pp = ap->private_data;
750 u32 tmp;
751
752 /* set FIS registers */
753 if (hpriv->cap & HOST_CAP_64)
754 writel((pp->cmd_slot_dma >> 16) >> 16,
755 port_mmio + PORT_LST_ADDR_HI);
756 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
757
758 if (hpriv->cap & HOST_CAP_64)
759 writel((pp->rx_fis_dma >> 16) >> 16,
760 port_mmio + PORT_FIS_ADDR_HI);
761 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
762
763 /* enable FIS reception */
764 tmp = readl(port_mmio + PORT_CMD);
765 tmp |= PORT_CMD_FIS_RX;
766 writel(tmp, port_mmio + PORT_CMD);
767
768 /* flush */
769 readl(port_mmio + PORT_CMD);
770 }
771
772 static int ahci_stop_fis_rx(struct ata_port *ap)
773 {
774 void __iomem *port_mmio = ahci_port_base(ap);
775 u32 tmp;
776
777 /* disable FIS reception */
778 tmp = readl(port_mmio + PORT_CMD);
779 tmp &= ~PORT_CMD_FIS_RX;
780 writel(tmp, port_mmio + PORT_CMD);
781
782 /* wait for completion, spec says 500ms, give it 1000 */
783 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
784 PORT_CMD_FIS_ON, 10, 1000);
785 if (tmp & PORT_CMD_FIS_ON)
786 return -EBUSY;
787
788 return 0;
789 }
790
791 static void ahci_power_up(struct ata_port *ap)
792 {
793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 void __iomem *port_mmio = ahci_port_base(ap);
795 u32 cmd;
796
797 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
798
799 /* spin up device */
800 if (hpriv->cap & HOST_CAP_SSS) {
801 cmd |= PORT_CMD_SPIN_UP;
802 writel(cmd, port_mmio + PORT_CMD);
803 }
804
805 /* wake up link */
806 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
807 }
808
809 #ifdef CONFIG_PM
810 static void ahci_power_down(struct ata_port *ap)
811 {
812 struct ahci_host_priv *hpriv = ap->host->private_data;
813 void __iomem *port_mmio = ahci_port_base(ap);
814 u32 cmd, scontrol;
815
816 if (!(hpriv->cap & HOST_CAP_SSS))
817 return;
818
819 /* put device into listen mode, first set PxSCTL.DET to 0 */
820 scontrol = readl(port_mmio + PORT_SCR_CTL);
821 scontrol &= ~0xf;
822 writel(scontrol, port_mmio + PORT_SCR_CTL);
823
824 /* then set PxCMD.SUD to 0 */
825 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
826 cmd &= ~PORT_CMD_SPIN_UP;
827 writel(cmd, port_mmio + PORT_CMD);
828 }
829 #endif
830
831 static void ahci_start_port(struct ata_port *ap)
832 {
833 /* enable FIS reception */
834 ahci_start_fis_rx(ap);
835
836 /* enable DMA */
837 ahci_start_engine(ap);
838 }
839
840 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
841 {
842 int rc;
843
844 /* disable DMA */
845 rc = ahci_stop_engine(ap);
846 if (rc) {
847 *emsg = "failed to stop engine";
848 return rc;
849 }
850
851 /* disable FIS reception */
852 rc = ahci_stop_fis_rx(ap);
853 if (rc) {
854 *emsg = "failed stop FIS RX";
855 return rc;
856 }
857
858 return 0;
859 }
860
861 static int ahci_reset_controller(struct ata_host *host)
862 {
863 struct pci_dev *pdev = to_pci_dev(host->dev);
864 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
865 u32 tmp;
866
867 /* we must be in AHCI mode, before using anything
868 * AHCI-specific, such as HOST_RESET.
869 */
870 tmp = readl(mmio + HOST_CTL);
871 if (!(tmp & HOST_AHCI_EN))
872 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
873
874 /* global controller reset */
875 if ((tmp & HOST_RESET) == 0) {
876 writel(tmp | HOST_RESET, mmio + HOST_CTL);
877 readl(mmio + HOST_CTL); /* flush */
878 }
879
880 /* reset must complete within 1 second, or
881 * the hardware should be considered fried.
882 */
883 ssleep(1);
884
885 tmp = readl(mmio + HOST_CTL);
886 if (tmp & HOST_RESET) {
887 dev_printk(KERN_ERR, host->dev,
888 "controller reset failed (0x%x)\n", tmp);
889 return -EIO;
890 }
891
892 /* turn on AHCI mode */
893 writel(HOST_AHCI_EN, mmio + HOST_CTL);
894 (void) readl(mmio + HOST_CTL); /* flush */
895
896 /* some registers might be cleared on reset. restore initial values */
897 ahci_restore_initial_config(host);
898
899 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
900 u16 tmp16;
901
902 /* configure PCS */
903 pci_read_config_word(pdev, 0x92, &tmp16);
904 tmp16 |= 0xf;
905 pci_write_config_word(pdev, 0x92, tmp16);
906 }
907
908 return 0;
909 }
910
911 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
912 int port_no, void __iomem *mmio,
913 void __iomem *port_mmio)
914 {
915 const char *emsg = NULL;
916 int rc;
917 u32 tmp;
918
919 /* make sure port is not active */
920 rc = ahci_deinit_port(ap, &emsg);
921 if (rc)
922 dev_printk(KERN_WARNING, &pdev->dev,
923 "%s (%d)\n", emsg, rc);
924
925 /* clear SError */
926 tmp = readl(port_mmio + PORT_SCR_ERR);
927 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
928 writel(tmp, port_mmio + PORT_SCR_ERR);
929
930 /* clear port IRQ */
931 tmp = readl(port_mmio + PORT_IRQ_STAT);
932 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
933 if (tmp)
934 writel(tmp, port_mmio + PORT_IRQ_STAT);
935
936 writel(1 << port_no, mmio + HOST_IRQ_STAT);
937 }
938
939 static void ahci_init_controller(struct ata_host *host)
940 {
941 struct ahci_host_priv *hpriv = host->private_data;
942 struct pci_dev *pdev = to_pci_dev(host->dev);
943 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
944 int i;
945 void __iomem *port_mmio;
946 u32 tmp;
947
948 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
949 port_mmio = __ahci_port_base(host, 4);
950
951 writel(0, port_mmio + PORT_IRQ_MASK);
952
953 /* clear port IRQ */
954 tmp = readl(port_mmio + PORT_IRQ_STAT);
955 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
956 if (tmp)
957 writel(tmp, port_mmio + PORT_IRQ_STAT);
958 }
959
960 for (i = 0; i < host->n_ports; i++) {
961 struct ata_port *ap = host->ports[i];
962
963 port_mmio = ahci_port_base(ap);
964 if (ata_port_is_dummy(ap))
965 continue;
966
967 ahci_port_init(pdev, ap, i, mmio, port_mmio);
968 }
969
970 tmp = readl(mmio + HOST_CTL);
971 VPRINTK("HOST_CTL 0x%x\n", tmp);
972 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
973 tmp = readl(mmio + HOST_CTL);
974 VPRINTK("HOST_CTL 0x%x\n", tmp);
975 }
976
977 static unsigned int ahci_dev_classify(struct ata_port *ap)
978 {
979 void __iomem *port_mmio = ahci_port_base(ap);
980 struct ata_taskfile tf;
981 u32 tmp;
982
983 tmp = readl(port_mmio + PORT_SIG);
984 tf.lbah = (tmp >> 24) & 0xff;
985 tf.lbam = (tmp >> 16) & 0xff;
986 tf.lbal = (tmp >> 8) & 0xff;
987 tf.nsect = (tmp) & 0xff;
988
989 return ata_dev_classify(&tf);
990 }
991
992 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
993 u32 opts)
994 {
995 dma_addr_t cmd_tbl_dma;
996
997 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
998
999 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1000 pp->cmd_slot[tag].status = 0;
1001 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1002 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1003 }
1004
1005 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1006 {
1007 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1008 struct ahci_host_priv *hpriv = ap->host->private_data;
1009 u32 tmp;
1010 int busy, rc;
1011
1012 /* do we need to kick the port? */
1013 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1014 if (!busy && !force_restart)
1015 return 0;
1016
1017 /* stop engine */
1018 rc = ahci_stop_engine(ap);
1019 if (rc)
1020 goto out_restart;
1021
1022 /* need to do CLO? */
1023 if (!busy) {
1024 rc = 0;
1025 goto out_restart;
1026 }
1027
1028 if (!(hpriv->cap & HOST_CAP_CLO)) {
1029 rc = -EOPNOTSUPP;
1030 goto out_restart;
1031 }
1032
1033 /* perform CLO */
1034 tmp = readl(port_mmio + PORT_CMD);
1035 tmp |= PORT_CMD_CLO;
1036 writel(tmp, port_mmio + PORT_CMD);
1037
1038 rc = 0;
1039 tmp = ata_wait_register(port_mmio + PORT_CMD,
1040 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1041 if (tmp & PORT_CMD_CLO)
1042 rc = -EIO;
1043
1044 /* restart engine */
1045 out_restart:
1046 ahci_start_engine(ap);
1047 return rc;
1048 }
1049
1050 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1051 struct ata_taskfile *tf, int is_cmd, u16 flags,
1052 unsigned long timeout_msec)
1053 {
1054 const u32 cmd_fis_len = 5; /* five dwords */
1055 struct ahci_port_priv *pp = ap->private_data;
1056 void __iomem *port_mmio = ahci_port_base(ap);
1057 u8 *fis = pp->cmd_tbl;
1058 u32 tmp;
1059
1060 /* prep the command */
1061 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1062 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1063
1064 /* issue & wait */
1065 writel(1, port_mmio + PORT_CMD_ISSUE);
1066
1067 if (timeout_msec) {
1068 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1069 1, timeout_msec);
1070 if (tmp & 0x1) {
1071 ahci_kick_engine(ap, 1);
1072 return -EBUSY;
1073 }
1074 } else
1075 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1076
1077 return 0;
1078 }
1079
1080 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1081 int pmp, unsigned long deadline)
1082 {
1083 struct ata_port *ap = link->ap;
1084 const char *reason = NULL;
1085 unsigned long now, msecs;
1086 struct ata_taskfile tf;
1087 int rc;
1088
1089 DPRINTK("ENTER\n");
1090
1091 if (ata_link_offline(link)) {
1092 DPRINTK("PHY reports no device\n");
1093 *class = ATA_DEV_NONE;
1094 return 0;
1095 }
1096
1097 /* prepare for SRST (AHCI-1.1 10.4.1) */
1098 rc = ahci_kick_engine(ap, 1);
1099 if (rc)
1100 ata_link_printk(link, KERN_WARNING,
1101 "failed to reset engine (errno=%d)", rc);
1102
1103 ata_tf_init(link->device, &tf);
1104
1105 /* issue the first D2H Register FIS */
1106 msecs = 0;
1107 now = jiffies;
1108 if (time_after(now, deadline))
1109 msecs = jiffies_to_msecs(deadline - now);
1110
1111 tf.ctl |= ATA_SRST;
1112 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1113 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1114 rc = -EIO;
1115 reason = "1st FIS failed";
1116 goto fail;
1117 }
1118
1119 /* spec says at least 5us, but be generous and sleep for 1ms */
1120 msleep(1);
1121
1122 /* issue the second D2H Register FIS */
1123 tf.ctl &= ~ATA_SRST;
1124 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1125
1126 /* spec mandates ">= 2ms" before checking status.
1127 * We wait 150ms, because that was the magic delay used for
1128 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1129 * between when the ATA command register is written, and then
1130 * status is checked. Because waiting for "a while" before
1131 * checking status is fine, post SRST, we perform this magic
1132 * delay here as well.
1133 */
1134 msleep(150);
1135
1136 rc = ata_wait_ready(ap, deadline);
1137 /* link occupied, -ENODEV too is an error */
1138 if (rc) {
1139 reason = "device not ready";
1140 goto fail;
1141 }
1142 *class = ahci_dev_classify(ap);
1143
1144 DPRINTK("EXIT, class=%u\n", *class);
1145 return 0;
1146
1147 fail:
1148 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1149 return rc;
1150 }
1151
1152 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1153 unsigned long deadline)
1154 {
1155 int pmp = 0;
1156
1157 if (link->ap->flags & ATA_FLAG_PMP)
1158 pmp = SATA_PMP_CTRL_PORT;
1159
1160 return ahci_do_softreset(link, class, pmp, deadline);
1161 }
1162
1163 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1164 unsigned long deadline)
1165 {
1166 struct ata_port *ap = link->ap;
1167 struct ahci_port_priv *pp = ap->private_data;
1168 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1169 struct ata_taskfile tf;
1170 int rc;
1171
1172 DPRINTK("ENTER\n");
1173
1174 ahci_stop_engine(ap);
1175
1176 /* clear D2H reception area to properly wait for D2H FIS */
1177 ata_tf_init(link->device, &tf);
1178 tf.command = 0x80;
1179 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1180
1181 rc = sata_std_hardreset(link, class, deadline);
1182
1183 ahci_start_engine(ap);
1184
1185 if (rc == 0 && ata_link_online(link))
1186 *class = ahci_dev_classify(ap);
1187 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1188 *class = ATA_DEV_NONE;
1189
1190 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1191 return rc;
1192 }
1193
1194 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1195 unsigned long deadline)
1196 {
1197 struct ata_port *ap = link->ap;
1198 u32 serror;
1199 int rc;
1200
1201 DPRINTK("ENTER\n");
1202
1203 ahci_stop_engine(ap);
1204
1205 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1206 deadline);
1207
1208 /* vt8251 needs SError cleared for the port to operate */
1209 ahci_scr_read(ap, SCR_ERROR, &serror);
1210 ahci_scr_write(ap, SCR_ERROR, serror);
1211
1212 ahci_start_engine(ap);
1213
1214 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1215
1216 /* vt8251 doesn't clear BSY on signature FIS reception,
1217 * request follow-up softreset.
1218 */
1219 return rc ?: -EAGAIN;
1220 }
1221
1222 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1223 {
1224 struct ata_port *ap = link->ap;
1225 void __iomem *port_mmio = ahci_port_base(ap);
1226 u32 new_tmp, tmp;
1227
1228 ata_std_postreset(link, class);
1229
1230 /* Make sure port's ATAPI bit is set appropriately */
1231 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1232 if (*class == ATA_DEV_ATAPI)
1233 new_tmp |= PORT_CMD_ATAPI;
1234 else
1235 new_tmp &= ~PORT_CMD_ATAPI;
1236 if (new_tmp != tmp) {
1237 writel(new_tmp, port_mmio + PORT_CMD);
1238 readl(port_mmio + PORT_CMD); /* flush */
1239 }
1240 }
1241
1242 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1243 unsigned long deadline)
1244 {
1245 return ahci_do_softreset(link, class, link->pmp, deadline);
1246 }
1247
1248 static u8 ahci_check_status(struct ata_port *ap)
1249 {
1250 void __iomem *mmio = ap->ioaddr.cmd_addr;
1251
1252 return readl(mmio + PORT_TFDATA) & 0xFF;
1253 }
1254
1255 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1256 {
1257 struct ahci_port_priv *pp = ap->private_data;
1258 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1259
1260 ata_tf_from_fis(d2h_fis, tf);
1261 }
1262
1263 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1264 {
1265 struct scatterlist *sg;
1266 struct ahci_sg *ahci_sg;
1267 unsigned int n_sg = 0;
1268
1269 VPRINTK("ENTER\n");
1270
1271 /*
1272 * Next, the S/G list.
1273 */
1274 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1275 ata_for_each_sg(sg, qc) {
1276 dma_addr_t addr = sg_dma_address(sg);
1277 u32 sg_len = sg_dma_len(sg);
1278
1279 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1280 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1281 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1282
1283 ahci_sg++;
1284 n_sg++;
1285 }
1286
1287 return n_sg;
1288 }
1289
1290 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1291 {
1292 struct ata_port *ap = qc->ap;
1293 struct ahci_port_priv *pp = ap->private_data;
1294 int is_atapi = is_atapi_taskfile(&qc->tf);
1295 void *cmd_tbl;
1296 u32 opts;
1297 const u32 cmd_fis_len = 5; /* five dwords */
1298 unsigned int n_elem;
1299
1300 /*
1301 * Fill in command table information. First, the header,
1302 * a SATA Register - Host to Device command FIS.
1303 */
1304 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1305
1306 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1307 if (is_atapi) {
1308 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1309 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1310 }
1311
1312 n_elem = 0;
1313 if (qc->flags & ATA_QCFLAG_DMAMAP)
1314 n_elem = ahci_fill_sg(qc, cmd_tbl);
1315
1316 /*
1317 * Fill in command slot information.
1318 */
1319 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1320 if (qc->tf.flags & ATA_TFLAG_WRITE)
1321 opts |= AHCI_CMD_WRITE;
1322 if (is_atapi)
1323 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1324
1325 ahci_fill_cmd_slot(pp, qc->tag, opts);
1326 }
1327
1328 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1329 {
1330 struct ahci_host_priv *hpriv = ap->host->private_data;
1331 struct ahci_port_priv *pp = ap->private_data;
1332 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1333 struct ata_link *link = NULL;
1334 struct ata_queued_cmd *active_qc;
1335 struct ata_eh_info *active_ehi;
1336 u32 serror;
1337
1338 /* determine active link */
1339 ata_port_for_each_link(link, ap)
1340 if (ata_link_active(link))
1341 break;
1342 if (!link)
1343 link = &ap->link;
1344
1345 active_qc = ata_qc_from_tag(ap, link->active_tag);
1346 active_ehi = &link->eh_info;
1347
1348 /* record irq stat */
1349 ata_ehi_clear_desc(host_ehi);
1350 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1351
1352 /* AHCI needs SError cleared; otherwise, it might lock up */
1353 ahci_scr_read(ap, SCR_ERROR, &serror);
1354 ahci_scr_write(ap, SCR_ERROR, serror);
1355 host_ehi->serror |= serror;
1356
1357 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1358 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1359 irq_stat &= ~PORT_IRQ_IF_ERR;
1360
1361 if (irq_stat & PORT_IRQ_TF_ERR) {
1362 /* If qc is active, charge it; otherwise, the active
1363 * link. There's no active qc on NCQ errors. It will
1364 * be determined by EH by reading log page 10h.
1365 */
1366 if (active_qc)
1367 active_qc->err_mask |= AC_ERR_DEV;
1368 else
1369 active_ehi->err_mask |= AC_ERR_DEV;
1370
1371 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1372 host_ehi->serror &= ~SERR_INTERNAL;
1373 }
1374
1375 if (irq_stat & PORT_IRQ_UNK_FIS) {
1376 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1377
1378 active_ehi->err_mask |= AC_ERR_HSM;
1379 active_ehi->action |= ATA_EH_SOFTRESET;
1380 ata_ehi_push_desc(active_ehi,
1381 "unknown FIS %08x %08x %08x %08x" ,
1382 unk[0], unk[1], unk[2], unk[3]);
1383 }
1384
1385 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1386 active_ehi->err_mask |= AC_ERR_HSM;
1387 active_ehi->action |= ATA_EH_SOFTRESET;
1388 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1389 }
1390
1391 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1392 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1393 host_ehi->action |= ATA_EH_SOFTRESET;
1394 ata_ehi_push_desc(host_ehi, "host bus error");
1395 }
1396
1397 if (irq_stat & PORT_IRQ_IF_ERR) {
1398 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1399 host_ehi->action |= ATA_EH_SOFTRESET;
1400 ata_ehi_push_desc(host_ehi, "interface fatal error");
1401 }
1402
1403 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1404 ata_ehi_hotplugged(host_ehi);
1405 ata_ehi_push_desc(host_ehi, "%s",
1406 irq_stat & PORT_IRQ_CONNECT ?
1407 "connection status changed" : "PHY RDY changed");
1408 }
1409
1410 /* okay, let's hand over to EH */
1411
1412 if (irq_stat & PORT_IRQ_FREEZE)
1413 ata_port_freeze(ap);
1414 else
1415 ata_port_abort(ap);
1416 }
1417
1418 static void ahci_port_intr(struct ata_port *ap)
1419 {
1420 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1421 struct ata_eh_info *ehi = &ap->link.eh_info;
1422 struct ahci_port_priv *pp = ap->private_data;
1423 u32 status, qc_active;
1424 int rc, known_irq = 0;
1425
1426 status = readl(port_mmio + PORT_IRQ_STAT);
1427 writel(status, port_mmio + PORT_IRQ_STAT);
1428
1429 if (unlikely(status & PORT_IRQ_ERROR)) {
1430 ahci_error_intr(ap, status);
1431 return;
1432 }
1433
1434 if (status & PORT_IRQ_SDB_FIS) {
1435 /* If the 'N' bit in word 0 of the FIS is set, we just
1436 * received asynchronous notification. Tell libata
1437 * about it. Note that as the SDB FIS itself is
1438 * accessible, SNotification can be emulated by the
1439 * driver but don't bother for the time being.
1440 */
1441 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1442 u32 f0 = le32_to_cpu(f[0]);
1443
1444 if (f0 & (1 << 15))
1445 sata_async_notification(ap);
1446 }
1447
1448 /* pp->active_link is valid iff any command is in flight */
1449 if (ap->qc_active && pp->active_link->sactive)
1450 qc_active = readl(port_mmio + PORT_SCR_ACT);
1451 else
1452 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1453
1454 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1455 if (rc > 0)
1456 return;
1457 if (rc < 0) {
1458 ehi->err_mask |= AC_ERR_HSM;
1459 ehi->action |= ATA_EH_SOFTRESET;
1460 ata_port_freeze(ap);
1461 return;
1462 }
1463
1464 /* hmmm... a spurious interupt */
1465
1466 /* if !NCQ, ignore. No modern ATA device has broken HSM
1467 * implementation for non-NCQ commands.
1468 */
1469 if (!ap->link.sactive)
1470 return;
1471
1472 if (status & PORT_IRQ_D2H_REG_FIS) {
1473 if (!pp->ncq_saw_d2h)
1474 ata_port_printk(ap, KERN_INFO,
1475 "D2H reg with I during NCQ, "
1476 "this message won't be printed again\n");
1477 pp->ncq_saw_d2h = 1;
1478 known_irq = 1;
1479 }
1480
1481 if (status & PORT_IRQ_DMAS_FIS) {
1482 if (!pp->ncq_saw_dmas)
1483 ata_port_printk(ap, KERN_INFO,
1484 "DMAS FIS during NCQ, "
1485 "this message won't be printed again\n");
1486 pp->ncq_saw_dmas = 1;
1487 known_irq = 1;
1488 }
1489
1490 if (status & PORT_IRQ_SDB_FIS) {
1491 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1492
1493 if (le32_to_cpu(f[1])) {
1494 /* SDB FIS containing spurious completions
1495 * might be dangerous, whine and fail commands
1496 * with HSM violation. EH will turn off NCQ
1497 * after several such failures.
1498 */
1499 ata_ehi_push_desc(ehi,
1500 "spurious completions during NCQ "
1501 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1502 readl(port_mmio + PORT_CMD_ISSUE),
1503 readl(port_mmio + PORT_SCR_ACT),
1504 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1505 ehi->err_mask |= AC_ERR_HSM;
1506 ehi->action |= ATA_EH_SOFTRESET;
1507 ata_port_freeze(ap);
1508 } else {
1509 if (!pp->ncq_saw_sdb)
1510 ata_port_printk(ap, KERN_INFO,
1511 "spurious SDB FIS %08x:%08x during NCQ, "
1512 "this message won't be printed again\n",
1513 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1514 pp->ncq_saw_sdb = 1;
1515 }
1516 known_irq = 1;
1517 }
1518
1519 if (!known_irq)
1520 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1521 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1522 status, ap->link.active_tag, ap->link.sactive);
1523 }
1524
1525 static void ahci_irq_clear(struct ata_port *ap)
1526 {
1527 /* TODO */
1528 }
1529
1530 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1531 {
1532 struct ata_host *host = dev_instance;
1533 struct ahci_host_priv *hpriv;
1534 unsigned int i, handled = 0;
1535 void __iomem *mmio;
1536 u32 irq_stat, irq_ack = 0;
1537
1538 VPRINTK("ENTER\n");
1539
1540 hpriv = host->private_data;
1541 mmio = host->iomap[AHCI_PCI_BAR];
1542
1543 /* sigh. 0xffffffff is a valid return from h/w */
1544 irq_stat = readl(mmio + HOST_IRQ_STAT);
1545 irq_stat &= hpriv->port_map;
1546 if (!irq_stat)
1547 return IRQ_NONE;
1548
1549 spin_lock(&host->lock);
1550
1551 for (i = 0; i < host->n_ports; i++) {
1552 struct ata_port *ap;
1553
1554 if (!(irq_stat & (1 << i)))
1555 continue;
1556
1557 ap = host->ports[i];
1558 if (ap) {
1559 ahci_port_intr(ap);
1560 VPRINTK("port %u\n", i);
1561 } else {
1562 VPRINTK("port %u (no irq)\n", i);
1563 if (ata_ratelimit())
1564 dev_printk(KERN_WARNING, host->dev,
1565 "interrupt on disabled port %u\n", i);
1566 }
1567
1568 irq_ack |= (1 << i);
1569 }
1570
1571 if (irq_ack) {
1572 writel(irq_ack, mmio + HOST_IRQ_STAT);
1573 handled = 1;
1574 }
1575
1576 spin_unlock(&host->lock);
1577
1578 VPRINTK("EXIT\n");
1579
1580 return IRQ_RETVAL(handled);
1581 }
1582
1583 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1584 {
1585 struct ata_port *ap = qc->ap;
1586 void __iomem *port_mmio = ahci_port_base(ap);
1587 struct ahci_port_priv *pp = ap->private_data;
1588
1589 /* Keep track of the currently active link. It will be used
1590 * in completion path to determine whether NCQ phase is in
1591 * progress.
1592 */
1593 pp->active_link = qc->dev->link;
1594
1595 if (qc->tf.protocol == ATA_PROT_NCQ)
1596 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1597 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1598 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1599
1600 return 0;
1601 }
1602
1603 static void ahci_freeze(struct ata_port *ap)
1604 {
1605 void __iomem *port_mmio = ahci_port_base(ap);
1606
1607 /* turn IRQ off */
1608 writel(0, port_mmio + PORT_IRQ_MASK);
1609 }
1610
1611 static void ahci_thaw(struct ata_port *ap)
1612 {
1613 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1614 void __iomem *port_mmio = ahci_port_base(ap);
1615 u32 tmp;
1616 struct ahci_port_priv *pp = ap->private_data;
1617
1618 /* clear IRQ */
1619 tmp = readl(port_mmio + PORT_IRQ_STAT);
1620 writel(tmp, port_mmio + PORT_IRQ_STAT);
1621 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1622
1623 /* turn IRQ back on */
1624 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1625 }
1626
1627 static void ahci_error_handler(struct ata_port *ap)
1628 {
1629 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1630 /* restart engine */
1631 ahci_stop_engine(ap);
1632 ahci_start_engine(ap);
1633 }
1634
1635 /* perform recovery */
1636 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1637 ahci_hardreset, ahci_postreset,
1638 sata_pmp_std_prereset, ahci_pmp_softreset,
1639 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1640 }
1641
1642 static void ahci_vt8251_error_handler(struct ata_port *ap)
1643 {
1644 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1645 /* restart engine */
1646 ahci_stop_engine(ap);
1647 ahci_start_engine(ap);
1648 }
1649
1650 /* perform recovery */
1651 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1652 ahci_postreset);
1653 }
1654
1655 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1656 {
1657 struct ata_port *ap = qc->ap;
1658
1659 /* make DMA engine forget about the failed command */
1660 if (qc->flags & ATA_QCFLAG_FAILED)
1661 ahci_kick_engine(ap, 1);
1662 }
1663
1664 static void ahci_pmp_attach(struct ata_port *ap)
1665 {
1666 void __iomem *port_mmio = ahci_port_base(ap);
1667 struct ahci_port_priv *pp = ap->private_data;
1668 u32 cmd;
1669
1670 cmd = readl(port_mmio + PORT_CMD);
1671 cmd |= PORT_CMD_PMP;
1672 writel(cmd, port_mmio + PORT_CMD);
1673
1674 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1675 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1676 }
1677
1678 static void ahci_pmp_detach(struct ata_port *ap)
1679 {
1680 void __iomem *port_mmio = ahci_port_base(ap);
1681 struct ahci_port_priv *pp = ap->private_data;
1682 u32 cmd;
1683
1684 cmd = readl(port_mmio + PORT_CMD);
1685 cmd &= ~PORT_CMD_PMP;
1686 writel(cmd, port_mmio + PORT_CMD);
1687
1688 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1689 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1690 }
1691
1692 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
1693 {
1694 struct ata_port *ap = dev->link->ap;
1695 struct ata_taskfile tf;
1696 int rc;
1697
1698 ahci_kick_engine(ap, 0);
1699
1700 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
1701 rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1702 SATA_PMP_SCR_TIMEOUT);
1703 if (rc == 0) {
1704 ahci_tf_read(ap, &tf);
1705 *r_val = sata_pmp_read_val(&tf);
1706 }
1707 return rc;
1708 }
1709
1710 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
1711 {
1712 struct ata_port *ap = dev->link->ap;
1713 struct ata_taskfile tf;
1714
1715 ahci_kick_engine(ap, 0);
1716
1717 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
1718 return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1719 SATA_PMP_SCR_TIMEOUT);
1720 }
1721
1722 static int ahci_port_resume(struct ata_port *ap)
1723 {
1724 ahci_power_up(ap);
1725 ahci_start_port(ap);
1726
1727 if (ap->nr_pmp_links)
1728 ahci_pmp_attach(ap);
1729 else
1730 ahci_pmp_detach(ap);
1731
1732 return 0;
1733 }
1734
1735 #ifdef CONFIG_PM
1736 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1737 {
1738 const char *emsg = NULL;
1739 int rc;
1740
1741 rc = ahci_deinit_port(ap, &emsg);
1742 if (rc == 0)
1743 ahci_power_down(ap);
1744 else {
1745 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1746 ahci_start_port(ap);
1747 }
1748
1749 return rc;
1750 }
1751
1752 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1753 {
1754 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1755 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1756 u32 ctl;
1757
1758 if (mesg.event == PM_EVENT_SUSPEND) {
1759 /* AHCI spec rev1.1 section 8.3.3:
1760 * Software must disable interrupts prior to requesting a
1761 * transition of the HBA to D3 state.
1762 */
1763 ctl = readl(mmio + HOST_CTL);
1764 ctl &= ~HOST_IRQ_EN;
1765 writel(ctl, mmio + HOST_CTL);
1766 readl(mmio + HOST_CTL); /* flush */
1767 }
1768
1769 return ata_pci_device_suspend(pdev, mesg);
1770 }
1771
1772 static int ahci_pci_device_resume(struct pci_dev *pdev)
1773 {
1774 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1775 int rc;
1776
1777 rc = ata_pci_device_do_resume(pdev);
1778 if (rc)
1779 return rc;
1780
1781 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1782 rc = ahci_reset_controller(host);
1783 if (rc)
1784 return rc;
1785
1786 ahci_init_controller(host);
1787 }
1788
1789 ata_host_resume(host);
1790
1791 return 0;
1792 }
1793 #endif
1794
1795 static int ahci_port_start(struct ata_port *ap)
1796 {
1797 struct device *dev = ap->host->dev;
1798 struct ahci_port_priv *pp;
1799 void *mem;
1800 dma_addr_t mem_dma;
1801 int rc;
1802
1803 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1804 if (!pp)
1805 return -ENOMEM;
1806
1807 rc = ata_pad_alloc(ap, dev);
1808 if (rc)
1809 return rc;
1810
1811 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1812 GFP_KERNEL);
1813 if (!mem)
1814 return -ENOMEM;
1815 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1816
1817 /*
1818 * First item in chunk of DMA memory: 32-slot command table,
1819 * 32 bytes each in size
1820 */
1821 pp->cmd_slot = mem;
1822 pp->cmd_slot_dma = mem_dma;
1823
1824 mem += AHCI_CMD_SLOT_SZ;
1825 mem_dma += AHCI_CMD_SLOT_SZ;
1826
1827 /*
1828 * Second item: Received-FIS area
1829 */
1830 pp->rx_fis = mem;
1831 pp->rx_fis_dma = mem_dma;
1832
1833 mem += AHCI_RX_FIS_SZ;
1834 mem_dma += AHCI_RX_FIS_SZ;
1835
1836 /*
1837 * Third item: data area for storing a single command
1838 * and its scatter-gather table
1839 */
1840 pp->cmd_tbl = mem;
1841 pp->cmd_tbl_dma = mem_dma;
1842
1843 /*
1844 * Save off initial list of interrupts to be enabled.
1845 * This could be changed later
1846 */
1847 pp->intr_mask = DEF_PORT_IRQ;
1848
1849 ap->private_data = pp;
1850
1851 /* engage engines, captain */
1852 return ahci_port_resume(ap);
1853 }
1854
1855 static void ahci_port_stop(struct ata_port *ap)
1856 {
1857 const char *emsg = NULL;
1858 int rc;
1859
1860 /* de-initialize port */
1861 rc = ahci_deinit_port(ap, &emsg);
1862 if (rc)
1863 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1864 }
1865
1866 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1867 {
1868 int rc;
1869
1870 if (using_dac &&
1871 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1872 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1873 if (rc) {
1874 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1875 if (rc) {
1876 dev_printk(KERN_ERR, &pdev->dev,
1877 "64-bit DMA enable failed\n");
1878 return rc;
1879 }
1880 }
1881 } else {
1882 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1883 if (rc) {
1884 dev_printk(KERN_ERR, &pdev->dev,
1885 "32-bit DMA enable failed\n");
1886 return rc;
1887 }
1888 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1889 if (rc) {
1890 dev_printk(KERN_ERR, &pdev->dev,
1891 "32-bit consistent DMA enable failed\n");
1892 return rc;
1893 }
1894 }
1895 return 0;
1896 }
1897
1898 static void ahci_print_info(struct ata_host *host)
1899 {
1900 struct ahci_host_priv *hpriv = host->private_data;
1901 struct pci_dev *pdev = to_pci_dev(host->dev);
1902 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1903 u32 vers, cap, impl, speed;
1904 const char *speed_s;
1905 u16 cc;
1906 const char *scc_s;
1907
1908 vers = readl(mmio + HOST_VERSION);
1909 cap = hpriv->cap;
1910 impl = hpriv->port_map;
1911
1912 speed = (cap >> 20) & 0xf;
1913 if (speed == 1)
1914 speed_s = "1.5";
1915 else if (speed == 2)
1916 speed_s = "3";
1917 else
1918 speed_s = "?";
1919
1920 pci_read_config_word(pdev, 0x0a, &cc);
1921 if (cc == PCI_CLASS_STORAGE_IDE)
1922 scc_s = "IDE";
1923 else if (cc == PCI_CLASS_STORAGE_SATA)
1924 scc_s = "SATA";
1925 else if (cc == PCI_CLASS_STORAGE_RAID)
1926 scc_s = "RAID";
1927 else
1928 scc_s = "unknown";
1929
1930 dev_printk(KERN_INFO, &pdev->dev,
1931 "AHCI %02x%02x.%02x%02x "
1932 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1933 ,
1934
1935 (vers >> 24) & 0xff,
1936 (vers >> 16) & 0xff,
1937 (vers >> 8) & 0xff,
1938 vers & 0xff,
1939
1940 ((cap >> 8) & 0x1f) + 1,
1941 (cap & 0x1f) + 1,
1942 speed_s,
1943 impl,
1944 scc_s);
1945
1946 dev_printk(KERN_INFO, &pdev->dev,
1947 "flags: "
1948 "%s%s%s%s%s%s%s"
1949 "%s%s%s%s%s%s%s\n"
1950 ,
1951
1952 cap & (1 << 31) ? "64bit " : "",
1953 cap & (1 << 30) ? "ncq " : "",
1954 cap & (1 << 29) ? "sntf " : "",
1955 cap & (1 << 28) ? "ilck " : "",
1956 cap & (1 << 27) ? "stag " : "",
1957 cap & (1 << 26) ? "pm " : "",
1958 cap & (1 << 25) ? "led " : "",
1959
1960 cap & (1 << 24) ? "clo " : "",
1961 cap & (1 << 19) ? "nz " : "",
1962 cap & (1 << 18) ? "only " : "",
1963 cap & (1 << 17) ? "pmp " : "",
1964 cap & (1 << 15) ? "pio " : "",
1965 cap & (1 << 14) ? "slum " : "",
1966 cap & (1 << 13) ? "part " : ""
1967 );
1968 }
1969
1970 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1971 {
1972 static int printed_version;
1973 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1974 const struct ata_port_info *ppi[] = { &pi, NULL };
1975 struct device *dev = &pdev->dev;
1976 struct ahci_host_priv *hpriv;
1977 struct ata_host *host;
1978 int i, rc;
1979
1980 VPRINTK("ENTER\n");
1981
1982 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1983
1984 if (!printed_version++)
1985 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1986
1987 /* acquire resources */
1988 rc = pcim_enable_device(pdev);
1989 if (rc)
1990 return rc;
1991
1992 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1993 if (rc == -EBUSY)
1994 pcim_pin_device(pdev);
1995 if (rc)
1996 return rc;
1997
1998 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1999 if (!hpriv)
2000 return -ENOMEM;
2001 hpriv->flags |= (unsigned long)pi.private_data;
2002
2003 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2004 pci_intx(pdev, 1);
2005
2006 /* save initial config */
2007 ahci_save_initial_config(pdev, hpriv);
2008
2009 /* prepare host */
2010 if (hpriv->cap & HOST_CAP_NCQ)
2011 pi.flags |= ATA_FLAG_NCQ;
2012
2013 if (hpriv->cap & HOST_CAP_PMP)
2014 pi.flags |= ATA_FLAG_PMP;
2015
2016 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2017 if (!host)
2018 return -ENOMEM;
2019 host->iomap = pcim_iomap_table(pdev);
2020 host->private_data = hpriv;
2021
2022 for (i = 0; i < host->n_ports; i++) {
2023 struct ata_port *ap = host->ports[i];
2024 void __iomem *port_mmio = ahci_port_base(ap);
2025
2026 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2027 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2028 0x100 + ap->port_no * 0x80, "port");
2029
2030 /* standard SATA port setup */
2031 if (hpriv->port_map & (1 << i))
2032 ap->ioaddr.cmd_addr = port_mmio;
2033
2034 /* disabled/not-implemented port */
2035 else
2036 ap->ops = &ata_dummy_port_ops;
2037 }
2038
2039 /* initialize adapter */
2040 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2041 if (rc)
2042 return rc;
2043
2044 rc = ahci_reset_controller(host);
2045 if (rc)
2046 return rc;
2047
2048 ahci_init_controller(host);
2049 ahci_print_info(host);
2050
2051 pci_set_master(pdev);
2052 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2053 &ahci_sht);
2054 }
2055
2056 static int __init ahci_init(void)
2057 {
2058 return pci_register_driver(&ahci_pci_driver);
2059 }
2060
2061 static void __exit ahci_exit(void)
2062 {
2063 pci_unregister_driver(&ahci_pci_driver);
2064 }
2065
2066
2067 MODULE_AUTHOR("Jeff Garzik");
2068 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2069 MODULE_LICENSE("GPL");
2070 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2071 MODULE_VERSION(DRV_VERSION);
2072
2073 module_init(ahci_init);
2074 module_exit(ahci_exit);
linux kernel for loongson