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sparc64: Create and use psycho_pbm_init_common().
[linux-2.6/linux-loongson.git] / arch / sparc64 / kernel / pci_psycho.c
blob2de51fb34ee7ddf3d79d20de01968c3fd3de3fb9
1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
15
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18 #include <asm/starfire.h>
19 #include <asm/prom.h>
20
21 #include "pci_impl.h"
22 #include "iommu_common.h"
23 #include "psycho_common.h"
24
25 #define DRIVER_NAME "psycho"
26 #define PFX DRIVER_NAME ": "
27
28 /* All PSYCHO registers are 64-bits. The following accessor
29 * routines are how they are accessed. The REG parameter
30 * is a physical address.
31 */
32 #define psycho_read(__reg) \
33 ({ u64 __ret; \
34 __asm__ __volatile__("ldxa [%1] %2, %0" \
35 : "=r" (__ret) \
36 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 : "memory"); \
38 __ret; \
39 })
40 #define psycho_write(__reg, __val) \
41 __asm__ __volatile__("stxa %0, [%1] %2" \
42 : /* no outputs */ \
43 : "r" (__val), "r" (__reg), \
44 "i" (ASI_PHYS_BYPASS_EC_E) \
45 : "memory")
46
47 /* Misc. PSYCHO PCI controller register offsets and definitions. */
48 #define PSYCHO_CONTROL 0x0010UL
49 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
50 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
51 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
52 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
53 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
54 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
55 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
56 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
57 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
58 #define PSYCHO_PCIA_CTRL 0x2000UL
59 #define PSYCHO_PCIB_CTRL 0x4000UL
60 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
61 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
62 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
63 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
64 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
65 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
66 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
67 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
68 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
69 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
70 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
71 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
72
73 /* U2P Programmer's Manual, page 13-55, configuration space
74 * address format:
75 *
76 * 32 24 23 16 15 11 10 8 7 2 1 0
77 * ---------------------------------------------------------
78 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
79 * ---------------------------------------------------------
80 */
81 #define PSYCHO_CONFIG_BASE(PBM) \
82 ((PBM)->config_space | (1UL << 24))
83 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
84 (((unsigned long)(BUS) << 16) | \
85 ((unsigned long)(DEVFN) << 8) | \
86 ((unsigned long)(REG)))
87
88 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
89 unsigned char bus,
90 unsigned int devfn,
91 int where)
92 {
93 if (!pbm)
94 return NULL;
95 return (void *)
96 (PSYCHO_CONFIG_BASE(pbm) |
97 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
98 }
99
100 /* PSYCHO error handling support. */
101 enum psycho_error_type {
102 UE_ERR, CE_ERR, PCI_ERR
103 };
104
105 /* Helper function of IOMMU error checking, which checks out
106 * the state of the streaming buffers. The IOMMU lock is
107 * held when this is called.
108 *
109 * For the PCI error case we know which PBM (and thus which
110 * streaming buffer) caused the error, but for the uncorrectable
111 * error case we do not. So we always check both streaming caches.
112 */
113 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
114 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
115 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
116 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
117 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
118 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
119 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
120 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
121 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
122 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
123 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
124 #define PSYCHO_STC_DATA_A 0xb000UL
125 #define PSYCHO_STC_DATA_B 0xc000UL
126 #define PSYCHO_STC_ERR_A 0xb400UL
127 #define PSYCHO_STC_ERR_B 0xc400UL
128 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
129 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
130 #define PSYCHO_STC_TAG_A 0xb800UL
131 #define PSYCHO_STC_TAG_B 0xc800UL
132 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
133 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
134 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
135 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
136 #define PSYCHO_STC_LINE_A 0xb900UL
137 #define PSYCHO_STC_LINE_B 0xc900UL
138 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
139 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
140 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
141 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
142 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
143 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
144
145 static DEFINE_SPINLOCK(stc_buf_lock);
146 static unsigned long stc_error_buf[128];
147 static unsigned long stc_tag_buf[16];
148 static unsigned long stc_line_buf[16];
149
150 static void psycho_check_stc_error(struct pci_pbm_info *pbm)
151 {
152 struct strbuf *strbuf = &pbm->stc;
153 unsigned long err_base, tag_base, line_base;
154 u64 control;
155 int i;
156
157 err_base = strbuf->strbuf_err_stat;
158 tag_base = strbuf->strbuf_tag_diag;
159 line_base = strbuf->strbuf_line_diag;
160
161 spin_lock(&stc_buf_lock);
162
163 /* This is __REALLY__ dangerous. When we put the
164 * streaming buffer into diagnostic mode to probe
165 * it's tags and error status, we _must_ clear all
166 * of the line tag valid bits before re-enabling
167 * the streaming buffer. If any dirty data lives
168 * in the STC when we do this, we will end up
169 * invalidating it before it has a chance to reach
170 * main memory.
171 */
172 control = psycho_read(strbuf->strbuf_control);
173 psycho_write(strbuf->strbuf_control,
174 (control | PSYCHO_STRBUF_CTRL_DENAB));
175 for (i = 0; i < 128; i++) {
176 unsigned long val;
177
178 val = psycho_read(err_base + (i * 8UL));
179 psycho_write(err_base + (i * 8UL), 0UL);
180 stc_error_buf[i] = val;
181 }
182 for (i = 0; i < 16; i++) {
183 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
184 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
185 psycho_write(tag_base + (i * 8UL), 0UL);
186 psycho_write(line_base + (i * 8UL), 0UL);
187 }
188
189 /* OK, state is logged, exit diagnostic mode. */
190 psycho_write(strbuf->strbuf_control, control);
191
192 for (i = 0; i < 16; i++) {
193 int j, saw_error, first, last;
194
195 saw_error = 0;
196 first = i * 8;
197 last = first + 8;
198 for (j = first; j < last; j++) {
199 unsigned long errval = stc_error_buf[j];
200 if (errval != 0) {
201 saw_error++;
202 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
203 pbm->name,
204 j,
205 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
206 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
207 }
208 }
209 if (saw_error != 0) {
210 unsigned long tagval = stc_tag_buf[i];
211 unsigned long lineval = stc_line_buf[i];
212 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
213 pbm->name,
214 i,
215 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
216 (tagval & PSYCHO_STCTAG_VPN),
217 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
218 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
219 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
220 "V(%d)FOFN(%d)]\n",
221 pbm->name,
222 i,
223 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
224 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
225 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
226 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
227 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
228 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
229 }
230 }
231
232 spin_unlock(&stc_buf_lock);
233 }
234
235 /* When an Uncorrectable Error or a PCI Error happens, we
236 * interrogate the IOMMU state to see if it is the cause.
237 */
238 #define PSYCHO_IOMMU_CONTROL 0x0200UL
239 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
240 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
241 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
242 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
243 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
244 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
245 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
246 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
247 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
248 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
249 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
250 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
251 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
252 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
253 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
254 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
255 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
256 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
257 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
258 #define PSYCHO_IOMMU_FLUSH 0x0210UL
259 #define PSYCHO_IOMMU_TAG 0xa580UL
260 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
261 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
262 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
263 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
264 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
265 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
266 #define PSYCHO_IOMMU_DATA 0xa600UL
267 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
268 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
269 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
270 static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
271 unsigned long afsr,
272 unsigned long afar,
273 enum psycho_error_type type)
274 {
275 struct iommu *iommu = pbm->iommu;
276 unsigned long iommu_tag[16];
277 unsigned long iommu_data[16];
278 unsigned long flags;
279 u64 control;
280 int i;
281
282 spin_lock_irqsave(&iommu->lock, flags);
283 control = psycho_read(iommu->iommu_control);
284 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
285 char *type_string;
286
287 /* Clear the error encountered bit. */
288 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
289 psycho_write(iommu->iommu_control, control);
290
291 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
292 case 0:
293 type_string = "Protection Error";
294 break;
295 case 1:
296 type_string = "Invalid Error";
297 break;
298 case 2:
299 type_string = "TimeOut Error";
300 break;
301 case 3:
302 default:
303 type_string = "ECC Error";
304 break;
305 };
306 printk("%s: IOMMU Error, type[%s]\n",
307 pbm->name, type_string);
308
309 /* Put the IOMMU into diagnostic mode and probe
310 * it's TLB for entries with error status.
311 *
312 * It is very possible for another DVMA to occur
313 * while we do this probe, and corrupt the system
314 * further. But we are so screwed at this point
315 * that we are likely to crash hard anyways, so
316 * get as much diagnostic information to the
317 * console as we can.
318 */
319 psycho_write(iommu->iommu_control,
320 control | PSYCHO_IOMMU_CTRL_DENAB);
321 for (i = 0; i < 16; i++) {
322 unsigned long base = pbm->controller_regs;
323
324 iommu_tag[i] =
325 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
326 iommu_data[i] =
327 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
328
329 /* Now clear out the entry. */
330 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
331 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
332 }
333
334 /* Leave diagnostic mode. */
335 psycho_write(iommu->iommu_control, control);
336
337 for (i = 0; i < 16; i++) {
338 unsigned long tag, data;
339
340 tag = iommu_tag[i];
341 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
342 continue;
343
344 data = iommu_data[i];
345 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
346 case 0:
347 type_string = "Protection Error";
348 break;
349 case 1:
350 type_string = "Invalid Error";
351 break;
352 case 2:
353 type_string = "TimeOut Error";
354 break;
355 case 3:
356 default:
357 type_string = "ECC Error";
358 break;
359 };
360 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
361 pbm->name, i, type_string,
362 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
363 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
364 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
365 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
366 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
367 pbm->name, i,
368 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
369 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
370 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
371 }
372 }
373 psycho_check_stc_error(pbm);
374 spin_unlock_irqrestore(&iommu->lock, flags);
375 }
376
377 /* Uncorrectable Errors. Cause of the error and the address are
378 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
379 * relating to UPA interface transactions.
380 */
381 #define PSYCHO_UE_AFSR 0x0030UL
382 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
383 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
384 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
385 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
386 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
387 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
388 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
389 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
390 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
391 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
392 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
393 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
394 #define PSYCHO_UE_AFAR 0x0038UL
395
396 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
397 {
398 struct pci_pbm_info *pbm = dev_id;
399 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
400 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
401 unsigned long afsr, afar, error_bits;
402 int reported;
403
404 /* Latch uncorrectable error status. */
405 afar = psycho_read(afar_reg);
406 afsr = psycho_read(afsr_reg);
407
408 /* Clear the primary/secondary error status bits. */
409 error_bits = afsr &
410 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
411 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
412 if (!error_bits)
413 return IRQ_NONE;
414 psycho_write(afsr_reg, error_bits);
415
416 /* Log the error. */
417 printk("%s: Uncorrectable Error, primary error type[%s]\n",
418 pbm->name,
419 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
420 "PIO" :
421 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
422 "DMA Read" :
423 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
424 "DMA Write" : "???")))));
425 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
426 pbm->name,
427 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
428 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
429 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
430 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
431 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
432 printk("%s: UE Secondary errors [", pbm->name);
433 reported = 0;
434 if (afsr & PSYCHO_UEAFSR_SPIO) {
435 reported++;
436 printk("(PIO)");
437 }
438 if (afsr & PSYCHO_UEAFSR_SDRD) {
439 reported++;
440 printk("(DMA Read)");
441 }
442 if (afsr & PSYCHO_UEAFSR_SDWR) {
443 reported++;
444 printk("(DMA Write)");
445 }
446 if (!reported)
447 printk("(none)");
448 printk("]\n");
449
450 /* Interrogate both IOMMUs for error status. */
451 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
452 if (pbm->sibling)
453 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
454
455 return IRQ_HANDLED;
456 }
457
458 /* Correctable Errors. */
459 #define PSYCHO_CE_AFSR 0x0040UL
460 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
461 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
462 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
463 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
464 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
465 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
466 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
467 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
468 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
469 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
470 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
471 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
472 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
473 #define PSYCHO_CE_AFAR 0x0040UL
474
475 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
476 {
477 struct pci_pbm_info *pbm = dev_id;
478 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
479 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
480 unsigned long afsr, afar, error_bits;
481 int reported;
482
483 /* Latch error status. */
484 afar = psycho_read(afar_reg);
485 afsr = psycho_read(afsr_reg);
486
487 /* Clear primary/secondary error status bits. */
488 error_bits = afsr &
489 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
490 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
491 if (!error_bits)
492 return IRQ_NONE;
493 psycho_write(afsr_reg, error_bits);
494
495 /* Log the error. */
496 printk("%s: Correctable Error, primary error type[%s]\n",
497 pbm->name,
498 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
499 "PIO" :
500 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
501 "DMA Read" :
502 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
503 "DMA Write" : "???")))));
504
505 /* XXX Use syndrome and afar to print out module string just like
506 * XXX UDB CE trap handler does... -DaveM
507 */
508 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
509 "UPA_MID[%02lx] was_block(%d)\n",
510 pbm->name,
511 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
512 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
513 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
514 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
515 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
516 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
517 printk("%s: CE Secondary errors [", pbm->name);
518 reported = 0;
519 if (afsr & PSYCHO_CEAFSR_SPIO) {
520 reported++;
521 printk("(PIO)");
522 }
523 if (afsr & PSYCHO_CEAFSR_SDRD) {
524 reported++;
525 printk("(DMA Read)");
526 }
527 if (afsr & PSYCHO_CEAFSR_SDWR) {
528 reported++;
529 printk("(DMA Write)");
530 }
531 if (!reported)
532 printk("(none)");
533 printk("]\n");
534
535 return IRQ_HANDLED;
536 }
537
538 /* PCI Errors. They are signalled by the PCI bus module since they
539 * are associated with a specific bus segment.
540 */
541 #define PSYCHO_PCI_AFSR_A 0x2010UL
542 #define PSYCHO_PCI_AFSR_B 0x4010UL
543 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
544 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
545 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
546 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
547 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
548 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
549 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
550 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
551 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
552 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
553 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
554 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
555 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
556 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
557 #define PSYCHO_PCI_AFAR_A 0x2018UL
558 #define PSYCHO_PCI_AFAR_B 0x4018UL
559
560 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
561 {
562 unsigned long csr, csr_error_bits;
563 irqreturn_t ret = IRQ_NONE;
564 u16 stat;
565
566 csr = psycho_read(pbm->pci_csr);
567 csr_error_bits =
568 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
569 if (csr_error_bits) {
570 /* Clear the errors. */
571 psycho_write(pbm->pci_csr, csr);
572
573 /* Log 'em. */
574 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
575 printk("%s: PCI streaming byte hole error asserted.\n",
576 pbm->name);
577 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
578 printk("%s: PCI SERR signal asserted.\n", pbm->name);
579 ret = IRQ_HANDLED;
580 }
581 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
582 if (stat & (PCI_STATUS_PARITY |
583 PCI_STATUS_SIG_TARGET_ABORT |
584 PCI_STATUS_REC_TARGET_ABORT |
585 PCI_STATUS_REC_MASTER_ABORT |
586 PCI_STATUS_SIG_SYSTEM_ERROR)) {
587 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
588 pbm->name, stat);
589 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
590 ret = IRQ_HANDLED;
591 }
592 return ret;
593 }
594
595 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
596 {
597 struct pci_pbm_info *pbm = dev_id;
598 unsigned long afsr_reg, afar_reg;
599 unsigned long afsr, afar, error_bits;
600 int reported;
601
602 afsr_reg = pbm->pci_afsr;
603 afar_reg = pbm->pci_afar;
604
605 /* Latch error status. */
606 afar = psycho_read(afar_reg);
607 afsr = psycho_read(afsr_reg);
608
609 /* Clear primary/secondary error status bits. */
610 error_bits = afsr &
611 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
612 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
613 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
614 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
615 if (!error_bits)
616 return psycho_pcierr_intr_other(pbm);
617 psycho_write(afsr_reg, error_bits);
618
619 /* Log the error. */
620 printk("%s: PCI Error, primary error type[%s]\n",
621 pbm->name,
622 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
623 "Master Abort" :
624 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
625 "Target Abort" :
626 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
627 "Excessive Retries" :
628 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
629 "Parity Error" : "???"))))));
630 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
631 pbm->name,
632 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
633 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
634 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
635 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
636 printk("%s: PCI Secondary errors [", pbm->name);
637 reported = 0;
638 if (afsr & PSYCHO_PCIAFSR_SMA) {
639 reported++;
640 printk("(Master Abort)");
641 }
642 if (afsr & PSYCHO_PCIAFSR_STA) {
643 reported++;
644 printk("(Target Abort)");
645 }
646 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
647 reported++;
648 printk("(Excessive Retries)");
649 }
650 if (afsr & PSYCHO_PCIAFSR_SPERR) {
651 reported++;
652 printk("(Parity Error)");
653 }
654 if (!reported)
655 printk("(none)");
656 printk("]\n");
657
658 /* For the error types shown, scan PBM's PCI bus for devices
659 * which have logged that error type.
660 */
661
662 /* If we see a Target Abort, this could be the result of an
663 * IOMMU translation error of some sort. It is extremely
664 * useful to log this information as usually it indicates
665 * a bug in the IOMMU support code or a PCI device driver.
666 */
667 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
668 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
669 pci_scan_for_target_abort(pbm, pbm->pci_bus);
670 }
671 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
672 pci_scan_for_master_abort(pbm, pbm->pci_bus);
673
674 /* For excessive retries, PSYCHO/PBM will abort the device
675 * and there is no way to specifically check for excessive
676 * retries in the config space status registers. So what
677 * we hope is that we'll catch it via the master/target
678 * abort events.
679 */
680
681 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
682 pci_scan_for_parity_error(pbm, pbm->pci_bus);
683
684 return IRQ_HANDLED;
685 }
686
687 /* XXX What about PowerFail/PowerManagement??? -DaveM */
688 #define PSYCHO_ECC_CTRL 0x0020
689 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
690 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
691 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
692 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
693 {
694 struct of_device *op = of_find_device_by_node(pbm->op->node);
695 unsigned long base = pbm->controller_regs;
696 u64 tmp;
697 int err;
698
699 if (!op)
700 return;
701
702 /* Psycho interrupt property order is:
703 * 0: PCIERR INO for this PBM
704 * 1: UE ERR
705 * 2: CE ERR
706 * 3: POWER FAIL
707 * 4: SPARE HARDWARE
708 * 5: POWER MANAGEMENT
709 */
710
711 if (op->num_irqs < 6)
712 return;
713
714 /* We really mean to ignore the return result here. Two
715 * PCI controller share the same interrupt numbers and
716 * drive the same front-end hardware. Whichever of the
717 * two get in here first will register the IRQ handler
718 * the second will just error out since we do not pass in
719 * IRQF_SHARED.
720 */
721 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
722 "PSYCHO_UE", pbm);
723 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
724 "PSYCHO_CE", pbm);
725
726 /* This one, however, ought not to fail. We can just warn
727 * about it since the system can still operate properly even
728 * if this fails.
729 */
730 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
731 "PSYCHO_PCIERR", pbm);
732 if (err)
733 printk(KERN_WARNING "%s: Could not register PCIERR, "
734 "err=%d\n", pbm->name, err);
735
736 /* Enable UE and CE interrupts for controller. */
737 psycho_write(base + PSYCHO_ECC_CTRL,
738 (PSYCHO_ECCCTRL_EE |
739 PSYCHO_ECCCTRL_UE |
740 PSYCHO_ECCCTRL_CE));
741
742 /* Enable PCI Error interrupts and clear error
743 * bits for each PBM.
744 */
745 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
746 tmp |= (PSYCHO_PCICTRL_SERR |
747 PSYCHO_PCICTRL_SBH_ERR |
748 PSYCHO_PCICTRL_EEN);
749 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
750 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
751
752 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
753 tmp |= (PSYCHO_PCICTRL_SERR |
754 PSYCHO_PCICTRL_SBH_ERR |
755 PSYCHO_PCICTRL_EEN);
756 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
757 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
758 }
759
760 /* PSYCHO boot time probing and initialization. */
761 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
762 {
763 u8 *addr;
764
765 /* Set cache-line size to 64 bytes, this is actually
766 * a nop but I do it for completeness.
767 */
768 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
769 0, PCI_CACHE_LINE_SIZE);
770 pci_config_write8(addr, 64 / sizeof(u32));
771
772 /* Set PBM latency timer to 64 PCI clocks. */
773 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
774 0, PCI_LATENCY_TIMER);
775 pci_config_write8(addr, 64);
776 }
777
778 static void __init psycho_scan_bus(struct pci_pbm_info *pbm,
779 struct device *parent)
780 {
781 pbm_config_busmastering(pbm);
782 pbm->is_66mhz_capable = 0;
783 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
784
785 /* After the PCI bus scan is complete, we can register
786 * the error interrupt handlers.
787 */
788 psycho_register_error_handlers(pbm);
789 }
790
791 #define PSYCHO_IRQ_RETRY 0x1a00UL
792 #define PSYCHO_PCIA_DIAG 0x2020UL
793 #define PSYCHO_PCIB_DIAG 0x4020UL
794 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
795 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
796 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
797 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
798 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
799 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
800 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
801 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
802
803 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
804 {
805 u64 tmp;
806
807 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
808
809 /* Enable arbiter for all PCI slots. */
810 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
811 tmp |= PSYCHO_PCICTRL_AEN;
812 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
813
814 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
815 tmp |= PSYCHO_PCICTRL_AEN;
816 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
817
818 /* Disable DMA write / PIO read synchronization on
819 * both PCI bus segments.
820 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
821 */
822 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
823 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
824 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
825
826 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
827 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
828 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
829 }
830
831 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
832 int is_pbm_a)
833 {
834 unsigned long base = pbm->controller_regs;
835 u64 control;
836
837 if (is_pbm_a) {
838 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
839 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
840 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
841 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
842 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
843 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
844 } else {
845 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
846 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
847 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
848 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
849 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
850 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
851 }
852 /* PSYCHO's streaming buffer lacks ctx flushing. */
853 pbm->stc.strbuf_ctxflush = 0;
854 pbm->stc.strbuf_ctxmatch_base = 0;
855
856 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
857 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
858 + 63UL)
859 & ~63UL);
860 pbm->stc.strbuf_flushflag_pa = (unsigned long)
861 __pa(pbm->stc.strbuf_flushflag);
862
863 /* Enable the streaming buffer. We have to be careful
864 * just in case OBP left it with LRU locking enabled.
865 *
866 * It is possible to control if PBM will be rerun on
867 * line misses. Currently I just retain whatever setting
868 * OBP left us with. All checks so far show it having
869 * a value of zero.
870 */
871 #undef PSYCHO_STRBUF_RERUN_ENABLE
872 #undef PSYCHO_STRBUF_RERUN_DISABLE
873 control = psycho_read(pbm->stc.strbuf_control);
874 control |= PSYCHO_STRBUF_CTRL_ENAB;
875 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
876 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
877 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
878 #else
879 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
880 control |= PSYCHO_STRBUF_CTRL_RRDIS;
881 #endif
882 #endif
883 psycho_write(pbm->stc.strbuf_control, control);
884
885 pbm->stc.strbuf_enabled = 1;
886 }
887
888 #define PSYCHO_IOSPACE_A 0x002000000UL
889 #define PSYCHO_IOSPACE_B 0x002010000UL
890 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
891 #define PSYCHO_MEMSPACE_A 0x100000000UL
892 #define PSYCHO_MEMSPACE_B 0x180000000UL
893 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
894
895 static void __init psycho_pbm_init(struct pci_pbm_info *pbm,
896 struct of_device *op, int is_pbm_a)
897 {
898 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
899 psycho_pbm_strbuf_init(pbm, is_pbm_a);
900 psycho_scan_bus(pbm, &op->dev);
901 }
902
903 static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid)
904 {
905 struct pci_pbm_info *pbm;
906
907 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
908 if (pbm->portid == upa_portid)
909 return pbm;
910 }
911 return NULL;
912 }
913
914 #define PSYCHO_CONFIGSPACE 0x001000000UL
915
916 static int __devinit psycho_probe(struct of_device *op,
917 const struct of_device_id *match)
918 {
919 const struct linux_prom64_registers *pr_regs;
920 struct device_node *dp = op->node;
921 struct pci_pbm_info *pbm;
922 struct iommu *iommu;
923 int is_pbm_a, err;
924 u32 upa_portid;
925
926 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
927
928 err = -ENOMEM;
929 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
930 if (!pbm) {
931 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
932 goto out_err;
933 }
934
935 pbm->sibling = psycho_find_sibling(upa_portid);
936 if (pbm->sibling) {
937 iommu = pbm->sibling->iommu;
938 } else {
939 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
940 if (!iommu) {
941 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
942 goto out_free_controller;
943 }
944 }
945
946 pbm->iommu = iommu;
947 pbm->portid = upa_portid;
948
949 pr_regs = of_get_property(dp, "reg", NULL);
950 err = -ENODEV;
951 if (!pr_regs) {
952 printk(KERN_ERR PFX "No reg property.\n");
953 goto out_free_iommu;
954 }
955
956 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
957
958 pbm->controller_regs = pr_regs[2].phys_addr;
959 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
960
961 if (is_pbm_a) {
962 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
963 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
964 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
965 } else {
966 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
967 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
968 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
969 }
970
971 psycho_controller_hwinit(pbm);
972 if (!pbm->sibling) {
973 err = psycho_iommu_init(pbm, 128, 0xc0000000,
974 0xffffffff, PSYCHO_CONTROL);
975 if (err)
976 goto out_free_iommu;
977
978 /* If necessary, hook us up for starfire IRQ translations. */
979 if (this_is_starfire)
980 starfire_hookup(pbm->portid);
981 }
982
983 psycho_pbm_init(pbm, op, is_pbm_a);
984
985 pbm->next = pci_pbm_root;
986 pci_pbm_root = pbm;
987
988 if (pbm->sibling)
989 pbm->sibling->sibling = pbm;
990
991 dev_set_drvdata(&op->dev, pbm);
992
993 return 0;
994
995 out_free_iommu:
996 if (!pbm->sibling)
997 kfree(pbm->iommu);
998
999 out_free_controller:
1000 kfree(pbm);
1001
1002 out_err:
1003 return err;
1004 }
1005
1006 static struct of_device_id __initdata psycho_match[] = {
1007 {
1008 .name = "pci",
1009 .compatible = "pci108e,8000",
1010 },
1011 {},
1012 };
1013
1014 static struct of_platform_driver psycho_driver = {
1015 .name = DRIVER_NAME,
1016 .match_table = psycho_match,
1017 .probe = psycho_probe,
1018 };
1019
1020 static int __init psycho_init(void)
1021 {
1022 return of_register_driver(&psycho_driver, &of_bus_type);
1023 }
1024
1025 subsys_initcall(psycho_init);
linux kernel for loongson