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V4L/DVB (6927): tda18271: improve printk macros
[linux-2.6/linux-loongson.git] / drivers / media / dvb / frontends / tda18271-fe.c
blob8146c4e7ee7bce6a0a8226632707454fa961adc4
1 /*
2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/delay.h>
22 #include <linux/videodev2.h>
23 #include "tda18271-priv.h"
24
25 int tda18271_debug;
26 module_param_named(debug, tda18271_debug, int, 0644);
27 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
28
29 /*---------------------------------------------------------------------*/
30
31 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
32 {
33 struct tda18271_priv *priv = fe->tuner_priv;
34 enum tda18271_i2c_gate gate;
35 int ret = 0;
36
37 switch (priv->gate) {
38 case TDA18271_GATE_DIGITAL:
39 case TDA18271_GATE_ANALOG:
40 gate = priv->gate;
41 break;
42 case TDA18271_GATE_AUTO:
43 default:
44 switch (priv->mode) {
45 case TDA18271_DIGITAL:
46 gate = TDA18271_GATE_DIGITAL;
47 break;
48 case TDA18271_ANALOG:
49 default:
50 gate = TDA18271_GATE_ANALOG;
51 break;
52 }
53 }
54
55 switch (gate) {
56 case TDA18271_GATE_ANALOG:
57 if (fe->ops.analog_ops.i2c_gate_ctrl)
58 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
59 break;
60 case TDA18271_GATE_DIGITAL:
61 if (fe->ops.i2c_gate_ctrl)
62 ret = fe->ops.i2c_gate_ctrl(fe, enable);
63 break;
64 default:
65 ret = -EINVAL;
66 break;
67 }
68
69 return ret;
70 };
71
72 /*---------------------------------------------------------------------*/
73
74 static void tda18271_dump_regs(struct dvb_frontend *fe)
75 {
76 struct tda18271_priv *priv = fe->tuner_priv;
77 unsigned char *regs = priv->tda18271_regs;
78
79 tda_reg("=== TDA18271 REG DUMP ===\n");
80 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
81 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
82 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
83 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
84 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
85 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
86 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
87 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
88 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
89 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
90 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
91 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
92 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
93 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
94 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
95 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
96 }
97
98 static void tda18271_read_regs(struct dvb_frontend *fe)
99 {
100 struct tda18271_priv *priv = fe->tuner_priv;
101 unsigned char *regs = priv->tda18271_regs;
102 unsigned char buf = 0x00;
103 int ret;
104 struct i2c_msg msg[] = {
105 { .addr = priv->i2c_addr, .flags = 0,
106 .buf = &buf, .len = 1 },
107 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
108 .buf = regs, .len = 16 }
109 };
110
111 tda18271_i2c_gate_ctrl(fe, 1);
112
113 /* read all registers */
114 ret = i2c_transfer(priv->i2c_adap, msg, 2);
115
116 tda18271_i2c_gate_ctrl(fe, 0);
117
118 if (ret != 2)
119 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
120
121 if (tda18271_debug & DBG_REG)
122 tda18271_dump_regs(fe);
123 }
124
125 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
126 {
127 struct tda18271_priv *priv = fe->tuner_priv;
128 unsigned char *regs = priv->tda18271_regs;
129 unsigned char buf[TDA18271_NUM_REGS+1];
130 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
131 .buf = buf, .len = len+1 };
132 int i, ret;
133
134 BUG_ON((len == 0) || (idx+len > sizeof(buf)));
135
136 buf[0] = idx;
137 for (i = 1; i <= len; i++) {
138 buf[i] = regs[idx-1+i];
139 }
140
141 tda18271_i2c_gate_ctrl(fe, 1);
142
143 /* write registers */
144 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
145
146 tda18271_i2c_gate_ctrl(fe, 0);
147
148 if (ret != 1)
149 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
150 }
151
152 /*---------------------------------------------------------------------*/
153
154 static int tda18271_init_regs(struct dvb_frontend *fe)
155 {
156 struct tda18271_priv *priv = fe->tuner_priv;
157 unsigned char *regs = priv->tda18271_regs;
158
159 tda_dbg("initializing registers for device @ %d-%04x\n",
160 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
161
162 /* initialize registers */
163 regs[R_ID] = 0x83;
164 regs[R_TM] = 0x08;
165 regs[R_PL] = 0x80;
166 regs[R_EP1] = 0xc6;
167 regs[R_EP2] = 0xdf;
168 regs[R_EP3] = 0x16;
169 regs[R_EP4] = 0x60;
170 regs[R_EP5] = 0x80;
171 regs[R_CPD] = 0x80;
172 regs[R_CD1] = 0x00;
173 regs[R_CD2] = 0x00;
174 regs[R_CD3] = 0x00;
175 regs[R_MPD] = 0x00;
176 regs[R_MD1] = 0x00;
177 regs[R_MD2] = 0x00;
178 regs[R_MD3] = 0x00;
179 regs[R_EB1] = 0xff;
180 regs[R_EB2] = 0x01;
181 regs[R_EB3] = 0x84;
182 regs[R_EB4] = 0x41;
183 regs[R_EB5] = 0x01;
184 regs[R_EB6] = 0x84;
185 regs[R_EB7] = 0x40;
186 regs[R_EB8] = 0x07;
187 regs[R_EB9] = 0x00;
188 regs[R_EB10] = 0x00;
189 regs[R_EB11] = 0x96;
190 regs[R_EB12] = 0x0f;
191 regs[R_EB13] = 0xc1;
192 regs[R_EB14] = 0x00;
193 regs[R_EB15] = 0x8f;
194 regs[R_EB16] = 0x00;
195 regs[R_EB17] = 0x00;
196 regs[R_EB18] = 0x00;
197 regs[R_EB19] = 0x00;
198 regs[R_EB20] = 0x20;
199 regs[R_EB21] = 0x33;
200 regs[R_EB22] = 0x48;
201 regs[R_EB23] = 0xb0;
202
203 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
204 /* setup AGC1 & AGC2 */
205 regs[R_EB17] = 0x00;
206 tda18271_write_regs(fe, R_EB17, 1);
207 regs[R_EB17] = 0x03;
208 tda18271_write_regs(fe, R_EB17, 1);
209 regs[R_EB17] = 0x43;
210 tda18271_write_regs(fe, R_EB17, 1);
211 regs[R_EB17] = 0x4c;
212 tda18271_write_regs(fe, R_EB17, 1);
213
214 regs[R_EB20] = 0xa0;
215 tda18271_write_regs(fe, R_EB20, 1);
216 regs[R_EB20] = 0xa7;
217 tda18271_write_regs(fe, R_EB20, 1);
218 regs[R_EB20] = 0xe7;
219 tda18271_write_regs(fe, R_EB20, 1);
220 regs[R_EB20] = 0xec;
221 tda18271_write_regs(fe, R_EB20, 1);
222
223 /* image rejection calibration */
224
225 /* low-band */
226 regs[R_EP3] = 0x1f;
227 regs[R_EP4] = 0x66;
228 regs[R_EP5] = 0x81;
229 regs[R_CPD] = 0xcc;
230 regs[R_CD1] = 0x6c;
231 regs[R_CD2] = 0x00;
232 regs[R_CD3] = 0x00;
233 regs[R_MPD] = 0xcd;
234 regs[R_MD1] = 0x77;
235 regs[R_MD2] = 0x08;
236 regs[R_MD3] = 0x00;
237
238 tda18271_write_regs(fe, R_EP3, 11);
239 msleep(5); /* pll locking */
240
241 regs[R_EP1] = 0xc6;
242 tda18271_write_regs(fe, R_EP1, 1);
243 msleep(5); /* wanted low measurement */
244
245 regs[R_EP3] = 0x1f;
246 regs[R_EP4] = 0x66;
247 regs[R_EP5] = 0x85;
248 regs[R_CPD] = 0xcb;
249 regs[R_CD1] = 0x66;
250 regs[R_CD2] = 0x70;
251 regs[R_CD3] = 0x00;
252
253 tda18271_write_regs(fe, R_EP3, 7);
254 msleep(5); /* pll locking */
255
256 regs[R_EP2] = 0xdf;
257 tda18271_write_regs(fe, R_EP2, 1);
258 msleep(30); /* image low optimization completion */
259
260 /* mid-band */
261 regs[R_EP3] = 0x1f;
262 regs[R_EP4] = 0x66;
263 regs[R_EP5] = 0x82;
264 regs[R_CPD] = 0xa8;
265 regs[R_CD1] = 0x66;
266 regs[R_CD2] = 0x00;
267 regs[R_CD3] = 0x00;
268 regs[R_MPD] = 0xa9;
269 regs[R_MD1] = 0x73;
270 regs[R_MD2] = 0x1a;
271 regs[R_MD3] = 0x00;
272
273 tda18271_write_regs(fe, R_EP3, 11);
274 msleep(5); /* pll locking */
275
276 regs[R_EP1] = 0xc6;
277 tda18271_write_regs(fe, R_EP1, 1);
278 msleep(5); /* wanted mid measurement */
279
280 regs[R_EP3] = 0x1f;
281 regs[R_EP4] = 0x66;
282 regs[R_EP5] = 0x86;
283 regs[R_CPD] = 0xa8;
284 regs[R_CD1] = 0x66;
285 regs[R_CD2] = 0xa0;
286 regs[R_CD3] = 0x00;
287
288 tda18271_write_regs(fe, R_EP3, 7);
289 msleep(5); /* pll locking */
290
291 regs[R_EP2] = 0xdf;
292 tda18271_write_regs(fe, R_EP2, 1);
293 msleep(30); /* image mid optimization completion */
294
295 /* high-band */
296 regs[R_EP3] = 0x1f;
297 regs[R_EP4] = 0x66;
298 regs[R_EP5] = 0x83;
299 regs[R_CPD] = 0x98;
300 regs[R_CD1] = 0x65;
301 regs[R_CD2] = 0x00;
302 regs[R_CD3] = 0x00;
303 regs[R_MPD] = 0x99;
304 regs[R_MD1] = 0x71;
305 regs[R_MD2] = 0xcd;
306 regs[R_MD3] = 0x00;
307
308 tda18271_write_regs(fe, R_EP3, 11);
309 msleep(5); /* pll locking */
310
311 regs[R_EP1] = 0xc6;
312 tda18271_write_regs(fe, R_EP1, 1);
313 msleep(5); /* wanted high measurement */
314
315 regs[R_EP3] = 0x1f;
316 regs[R_EP4] = 0x66;
317 regs[R_EP5] = 0x87;
318 regs[R_CPD] = 0x98;
319 regs[R_CD1] = 0x65;
320 regs[R_CD2] = 0x50;
321 regs[R_CD3] = 0x00;
322
323 tda18271_write_regs(fe, R_EP3, 7);
324 msleep(5); /* pll locking */
325
326 regs[R_EP2] = 0xdf;
327
328 tda18271_write_regs(fe, R_EP2, 1);
329 msleep(30); /* image high optimization completion */
330
331 regs[R_EP4] = 0x64;
332 tda18271_write_regs(fe, R_EP4, 1);
333
334 regs[R_EP1] = 0xc6;
335 tda18271_write_regs(fe, R_EP1, 1);
336
337 return 0;
338 }
339
340 static int tda18271_init(struct dvb_frontend *fe)
341 {
342 struct tda18271_priv *priv = fe->tuner_priv;
343 unsigned char *regs = priv->tda18271_regs;
344
345 tda18271_read_regs(fe);
346
347 /* test IR_CAL_OK to see if we need init */
348 if ((regs[R_EP1] & 0x08) == 0)
349 tda18271_init_regs(fe);
350
351 return 0;
352 }
353
354 static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
355 {
356 /* Sets Main Post-Divider & Divider bytes, but does not write them */
357 struct tda18271_priv *priv = fe->tuner_priv;
358 unsigned char *regs = priv->tda18271_regs;
359 u8 d, pd;
360 u32 div;
361
362 int ret = tda18271_lookup_pll_map(MAIN_PLL, &freq, &pd, &d);
363 if (ret < 0)
364 goto fail;
365
366 regs[R_MPD] = (0x77 & pd);
367
368 switch (priv->mode) {
369 case TDA18271_ANALOG:
370 regs[R_MPD] &= ~0x08;
371 break;
372 case TDA18271_DIGITAL:
373 regs[R_MPD] |= 0x08;
374 break;
375 }
376
377 div = ((d * (freq / 1000)) << 7) / 125;
378
379 regs[R_MD1] = 0x7f & (div >> 16);
380 regs[R_MD2] = 0xff & (div >> 8);
381 regs[R_MD3] = 0xff & div;
382 fail:
383 return ret;
384 }
385
386 static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
387 {
388 /* Sets Cal Post-Divider & Divider bytes, but does not write them */
389 struct tda18271_priv *priv = fe->tuner_priv;
390 unsigned char *regs = priv->tda18271_regs;
391 u8 d, pd;
392 u32 div;
393
394 int ret = tda18271_lookup_pll_map(CAL_PLL, &freq, &pd, &d);
395 if (ret < 0)
396 goto fail;
397
398 regs[R_CPD] = pd;
399
400 div = ((d * (freq / 1000)) << 7) / 125;
401
402 regs[R_CD1] = 0x7f & (div >> 16);
403 regs[R_CD2] = 0xff & (div >> 8);
404 regs[R_CD3] = 0xff & div;
405 fail:
406 return ret;
407 }
408
409 static int tda18271_tune(struct dvb_frontend *fe,
410 u32 ifc, u32 freq, u32 bw, u8 std)
411 {
412 struct tda18271_priv *priv = fe->tuner_priv;
413 unsigned char *regs = priv->tda18271_regs;
414 u32 N = 0;
415 u8 val;
416
417 tda18271_init(fe);
418
419 tda_dbg("freq = %d, ifc = %d\n", freq, ifc);
420
421 /* RF tracking filter calibration */
422
423 /* calculate BP_Filter */
424 tda18271_lookup_map(BP_FILTER, &freq, &val);
425
426 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
427 regs[R_EP1] |= val;
428 tda18271_write_regs(fe, R_EP1, 1);
429
430 regs[R_EB4] &= 0x07;
431 regs[R_EB4] |= 0x60;
432 tda18271_write_regs(fe, R_EB4, 1);
433
434 regs[R_EB7] = 0x60;
435 tda18271_write_regs(fe, R_EB7, 1);
436
437 regs[R_EB14] = 0x00;
438 tda18271_write_regs(fe, R_EB14, 1);
439
440 regs[R_EB20] = 0xcc;
441 tda18271_write_regs(fe, R_EB20, 1);
442
443 /* set CAL mode to RF tracking filter calibration */
444 regs[R_EP4] |= 0x03;
445
446 /* calculate CAL PLL */
447
448 switch (priv->mode) {
449 case TDA18271_ANALOG:
450 N = freq - 1250000;
451 break;
452 case TDA18271_DIGITAL:
453 N = freq + bw / 2;
454 break;
455 }
456
457 tda18271_calc_cal_pll(fe, N);
458
459 /* calculate MAIN PLL */
460
461 switch (priv->mode) {
462 case TDA18271_ANALOG:
463 N = freq - 250000;
464 break;
465 case TDA18271_DIGITAL:
466 N = freq + bw / 2 + 1000000;
467 break;
468 }
469
470 tda18271_calc_main_pll(fe, N);
471
472 tda18271_write_regs(fe, R_EP3, 11);
473 msleep(5); /* RF tracking filter calibration initialization */
474
475 /* search for K,M,CO for RF Calibration */
476 tda18271_lookup_map(RF_CAL_KMCO, &freq, &val);
477
478 regs[R_EB13] &= 0x83;
479 regs[R_EB13] |= val;
480 tda18271_write_regs(fe, R_EB13, 1);
481
482 /* search for RF_BAND */
483 tda18271_lookup_map(RF_BAND, &freq, &val);
484
485 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
486 regs[R_EP2] |= (val << 5);
487
488 /* search for Gain_Taper */
489 tda18271_lookup_map(GAIN_TAPER, &freq, &val);
490
491 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
492 regs[R_EP2] |= val;
493
494 tda18271_write_regs(fe, R_EP2, 1);
495 tda18271_write_regs(fe, R_EP1, 1);
496 tda18271_write_regs(fe, R_EP2, 1);
497 tda18271_write_regs(fe, R_EP1, 1);
498
499 regs[R_EB4] &= 0x07;
500 regs[R_EB4] |= 0x40;
501 tda18271_write_regs(fe, R_EB4, 1);
502
503 regs[R_EB7] = 0x40;
504 tda18271_write_regs(fe, R_EB7, 1);
505 msleep(10);
506
507 regs[R_EB20] = 0xec;
508 tda18271_write_regs(fe, R_EB20, 1);
509 msleep(60); /* RF tracking filter calibration completion */
510
511 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
512 tda18271_write_regs(fe, R_EP4, 1);
513
514 tda18271_write_regs(fe, R_EP1, 1);
515
516 /* RF tracking filer correction for VHF_Low band */
517 tda18271_lookup_map(RF_CAL, &freq, &val);
518
519 /* VHF_Low band only */
520 if (val != 0) {
521 regs[R_EB14] = val;
522 tda18271_write_regs(fe, R_EB14, 1);
523 }
524
525 /* Channel Configuration */
526
527 switch (priv->mode) {
528 case TDA18271_ANALOG:
529 regs[R_EB22] = 0x2c;
530 break;
531 case TDA18271_DIGITAL:
532 regs[R_EB22] = 0x37;
533 break;
534 }
535 tda18271_write_regs(fe, R_EB22, 1);
536
537 regs[R_EP1] |= 0x40; /* set dis power level on */
538
539 /* set standard */
540 regs[R_EP3] &= ~0x1f; /* clear std bits */
541
542 /* see table 22 */
543 regs[R_EP3] |= std;
544
545 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
546
547 regs[R_EP4] &= ~0x1c; /* clear if level bits */
548 switch (priv->mode) {
549 case TDA18271_ANALOG:
550 regs[R_MPD] &= ~0x80; /* IF notch = 0 */
551 break;
552 case TDA18271_DIGITAL:
553 regs[R_EP4] |= 0x04;
554 regs[R_MPD] |= 0x80;
555 break;
556 }
557
558 regs[R_EP4] &= ~0x80; /* turn this bit on only for fm */
559
560 /* image rejection validity EP5[2:0] */
561 tda18271_lookup_map(IR_MEASURE, &freq, &val);
562
563 regs[R_EP5] &= ~0x07;
564 regs[R_EP5] |= val;
565
566 /* calculate MAIN PLL */
567 N = freq + ifc;
568
569 tda18271_calc_main_pll(fe, N);
570
571 tda18271_write_regs(fe, R_TM, 15);
572 msleep(5);
573
574 return 0;
575 }
576
577 /* ------------------------------------------------------------------ */
578
579 static int tda18271_set_params(struct dvb_frontend *fe,
580 struct dvb_frontend_parameters *params)
581 {
582 struct tda18271_priv *priv = fe->tuner_priv;
583 u8 std;
584 u32 bw, sgIF = 0;
585
586 u32 freq = params->frequency;
587
588 priv->mode = TDA18271_DIGITAL;
589
590 /* see table 22 */
591 if (fe->ops.info.type == FE_ATSC) {
592 switch (params->u.vsb.modulation) {
593 case VSB_8:
594 case VSB_16:
595 std = 0x1b; /* device-specific (spec says 0x1c) */
596 sgIF = 5380000;
597 break;
598 case QAM_64:
599 case QAM_256:
600 std = 0x18; /* device-specific (spec says 0x1d) */
601 sgIF = 4000000;
602 break;
603 default:
604 tda_warn("modulation not set!\n");
605 return -EINVAL;
606 }
607 #if 0
608 /* userspace request is already center adjusted */
609 freq += 1750000; /* Adjust to center (+1.75MHZ) */
610 #endif
611 bw = 6000000;
612 } else if (fe->ops.info.type == FE_OFDM) {
613 switch (params->u.ofdm.bandwidth) {
614 case BANDWIDTH_6_MHZ:
615 std = 0x1b; /* device-specific (spec says 0x1c) */
616 bw = 6000000;
617 sgIF = 3300000;
618 break;
619 case BANDWIDTH_7_MHZ:
620 std = 0x19; /* device-specific (spec says 0x1d) */
621 bw = 7000000;
622 sgIF = 3800000;
623 break;
624 case BANDWIDTH_8_MHZ:
625 std = 0x1a; /* device-specific (spec says 0x1e) */
626 bw = 8000000;
627 sgIF = 4300000;
628 break;
629 default:
630 tda_warn("bandwidth not set!\n");
631 return -EINVAL;
632 }
633 } else {
634 tda_warn("modulation type not supported!\n");
635 return -EINVAL;
636 }
637
638 return tda18271_tune(fe, sgIF, freq, bw, std);
639 }
640
641 static int tda18271_set_analog_params(struct dvb_frontend *fe,
642 struct analog_parameters *params)
643 {
644 struct tda18271_priv *priv = fe->tuner_priv;
645 u8 std;
646 unsigned int sgIF;
647 char *mode;
648
649 priv->mode = TDA18271_ANALOG;
650
651 /* see table 22 */
652 if (params->std & V4L2_STD_MN) {
653 std = 0x0d;
654 sgIF = 92;
655 mode = "MN";
656 } else if (params->std & V4L2_STD_B) {
657 std = 0x0e;
658 sgIF = 108;
659 mode = "B";
660 } else if (params->std & V4L2_STD_GH) {
661 std = 0x0f;
662 sgIF = 124;
663 mode = "GH";
664 } else if (params->std & V4L2_STD_PAL_I) {
665 std = 0x0f;
666 sgIF = 124;
667 mode = "I";
668 } else if (params->std & V4L2_STD_DK) {
669 std = 0x0f;
670 sgIF = 124;
671 mode = "DK";
672 } else if (params->std & V4L2_STD_SECAM_L) {
673 std = 0x0f;
674 sgIF = 124;
675 mode = "L";
676 } else if (params->std & V4L2_STD_SECAM_LC) {
677 std = 0x0f;
678 sgIF = 20;
679 mode = "LC";
680 } else {
681 std = 0x0f;
682 sgIF = 124;
683 mode = "xx";
684 }
685
686 if (params->mode == V4L2_TUNER_RADIO)
687 sgIF = 88; /* if frequency is 5.5 MHz */
688
689 tda_dbg("setting tda18271 to system %s\n", mode);
690
691 return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
692 0, std);
693 }
694
695 static int tda18271_release(struct dvb_frontend *fe)
696 {
697 kfree(fe->tuner_priv);
698 fe->tuner_priv = NULL;
699 return 0;
700 }
701
702 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
703 {
704 struct tda18271_priv *priv = fe->tuner_priv;
705 *frequency = priv->frequency;
706 return 0;
707 }
708
709 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
710 {
711 struct tda18271_priv *priv = fe->tuner_priv;
712 *bandwidth = priv->bandwidth;
713 return 0;
714 }
715
716 static int tda18271_get_id(struct dvb_frontend *fe)
717 {
718 struct tda18271_priv *priv = fe->tuner_priv;
719 unsigned char *regs = priv->tda18271_regs;
720 char *name;
721 int ret = 0;
722
723 tda18271_read_regs(fe);
724
725 switch (regs[R_ID] & 0x7f) {
726 case 3:
727 name = "TDA18271HD/C1";
728 break;
729 case 4:
730 name = "TDA18271HD/C2";
731 ret = -EPROTONOSUPPORT;
732 break;
733 default:
734 name = "Unknown device";
735 ret = -EINVAL;
736 break;
737 }
738
739 tda_info("%s detected @ %d-%04x%s\n", name,
740 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr,
741 (0 == ret) ? "" : ", device not supported.");
742
743 return ret;
744 }
745
746 static struct dvb_tuner_ops tda18271_tuner_ops = {
747 .info = {
748 .name = "NXP TDA18271HD",
749 .frequency_min = 45000000,
750 .frequency_max = 864000000,
751 .frequency_step = 62500
752 },
753 .init = tda18271_init,
754 .set_params = tda18271_set_params,
755 .set_analog_params = tda18271_set_analog_params,
756 .release = tda18271_release,
757 .get_frequency = tda18271_get_frequency,
758 .get_bandwidth = tda18271_get_bandwidth,
759 };
760
761 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
762 struct i2c_adapter *i2c,
763 enum tda18271_i2c_gate gate)
764 {
765 struct tda18271_priv *priv = NULL;
766
767 priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
768 if (priv == NULL)
769 return NULL;
770
771 priv->i2c_addr = addr;
772 priv->i2c_adap = i2c;
773 priv->gate = gate;
774
775 fe->tuner_priv = priv;
776
777 if (tda18271_get_id(fe) < 0)
778 goto fail;
779
780 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
781 sizeof(struct dvb_tuner_ops));
782
783 tda18271_init_regs(fe);
784
785 return fe;
786 fail:
787 tda18271_release(fe);
788 return NULL;
789 }
790 EXPORT_SYMBOL_GPL(tda18271_attach);
791 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
792 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
793 MODULE_LICENSE("GPL");
794
795 /*
796 * Overrides for Emacs so that we follow Linus's tabbing style.
797 * ---------------------------------------------------------------------------
798 * Local variables:
799 * c-basic-offset: 8
800 * End:
801 */
linux kernel for loongson