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ide: remove ->mmio flag from ide_hwif_t
[linux-2.6/linux-loongson.git] / drivers / ide / pci / scc_pata.c
blob133053c7a480b55a58a1cef4dad67876cd5f04bb
1 /*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
32
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35 #define SCC_PATA_NAME "scc IDE"
36
37 #define TDVHSEL_MASTER 0x00000001
38 #define TDVHSEL_SLAVE 0x00000004
39
40 #define MODE_JCUSFEN 0x00000080
41
42 #define CCKCTRL_ATARESET 0x00040000
43 #define CCKCTRL_BUFCNT 0x00020000
44 #define CCKCTRL_CRST 0x00010000
45 #define CCKCTRL_OCLKEN 0x00000100
46 #define CCKCTRL_ATACLKOEN 0x00000002
47 #define CCKCTRL_LCLKEN 0x00000001
48
49 #define QCHCD_IOS_SS 0x00000001
50
51 #define QCHSD_STPDIAG 0x00020000
52
53 #define INTMASK_MSK 0xD1000012
54 #define INTSTS_SERROR 0x80000000
55 #define INTSTS_PRERR 0x40000000
56 #define INTSTS_RERR 0x10000000
57 #define INTSTS_ICERR 0x01000000
58 #define INTSTS_BMSINT 0x00000010
59 #define INTSTS_BMHE 0x00000008
60 #define INTSTS_IOIRQS 0x00000004
61 #define INTSTS_INTRQ 0x00000002
62 #define INTSTS_ACTEINT 0x00000001
63
64 #define ECMODE_VALUE 0x01
65
66 static struct scc_ports {
67 unsigned long ctl, dma;
68 ide_hwif_t *hwif; /* for removing port from system */
69 } scc_ports[MAX_HWIFS];
70
71 /* PIO transfer mode table */
72 /* JCHST */
73 static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76 };
77
78 /* JCHHT */
79 static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82 };
83
84 /* JCHCT */
85 static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88 };
89
90
91 /* DMA transfer mode table */
92 /* JCHDCTM/JCHDCTS */
93 static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96 };
97
98 /* JCSTWTM/JCSTWTS */
99 static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102 };
103
104 /* JCTSS */
105 static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108 };
109
110 /* JCENVT */
111 static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114 };
115
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120 };
121
122
123 static u8 scc_ide_inb(unsigned long port)
124 {
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127 }
128
129 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
130 {
131 u16 *ptr = (u16 *)addr;
132 while (count--) {
133 *ptr++ = le16_to_cpu(in_be32((void*)port));
134 }
135 }
136
137 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
138 {
139 u16 *ptr = (u16 *)addr;
140 while (count--) {
141 *ptr++ = le16_to_cpu(in_be32((void*)port));
142 *ptr++ = le16_to_cpu(in_be32((void*)port));
143 }
144 }
145
146 static void scc_ide_outb(u8 addr, unsigned long port)
147 {
148 out_be32((void*)port, addr);
149 }
150
151 static void
152 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
153 {
154 ide_hwif_t *hwif = HWIF(drive);
155
156 out_be32((void*)port, addr);
157 eieio();
158 in_be32((void*)(hwif->dma_base + 0x01c));
159 eieio();
160 }
161
162 static void
163 scc_ide_outsw(unsigned long port, void *addr, u32 count)
164 {
165 u16 *ptr = (u16 *)addr;
166 while (count--) {
167 out_be32((void*)port, cpu_to_le16(*ptr++));
168 }
169 }
170
171 static void
172 scc_ide_outsl(unsigned long port, void *addr, u32 count)
173 {
174 u16 *ptr = (u16 *)addr;
175 while (count--) {
176 out_be32((void*)port, cpu_to_le16(*ptr++));
177 out_be32((void*)port, cpu_to_le16(*ptr++));
178 }
179 }
180
181 /**
182 * scc_set_pio_mode - set host controller for PIO mode
183 * @drive: drive
184 * @pio: PIO mode number
185 *
186 * Load the timing settings for this device mode into the
187 * controller.
188 */
189
190 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
191 {
192 ide_hwif_t *hwif = HWIF(drive);
193 struct scc_ports *ports = ide_get_hwifdata(hwif);
194 unsigned long ctl_base = ports->ctl;
195 unsigned long cckctrl_port = ctl_base + 0xff0;
196 unsigned long piosht_port = ctl_base + 0x000;
197 unsigned long pioct_port = ctl_base + 0x004;
198 unsigned long reg;
199 int offset;
200
201 reg = in_be32((void __iomem *)cckctrl_port);
202 if (reg & CCKCTRL_ATACLKOEN) {
203 offset = 1; /* 133MHz */
204 } else {
205 offset = 0; /* 100MHz */
206 }
207 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
208 out_be32((void __iomem *)piosht_port, reg);
209 reg = JCHCTtbl[offset][pio];
210 out_be32((void __iomem *)pioct_port, reg);
211 }
212
213 /**
214 * scc_set_dma_mode - set host controller for DMA mode
215 * @drive: drive
216 * @speed: DMA mode
217 *
218 * Load the timing settings for this device mode into the
219 * controller.
220 */
221
222 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
223 {
224 ide_hwif_t *hwif = HWIF(drive);
225 struct scc_ports *ports = ide_get_hwifdata(hwif);
226 unsigned long ctl_base = ports->ctl;
227 unsigned long cckctrl_port = ctl_base + 0xff0;
228 unsigned long mdmact_port = ctl_base + 0x008;
229 unsigned long mcrcst_port = ctl_base + 0x00c;
230 unsigned long sdmact_port = ctl_base + 0x010;
231 unsigned long scrcst_port = ctl_base + 0x014;
232 unsigned long udenvt_port = ctl_base + 0x018;
233 unsigned long tdvhsel_port = ctl_base + 0x020;
234 int is_slave = (&hwif->drives[1] == drive);
235 int offset, idx;
236 unsigned long reg;
237 unsigned long jcactsel;
238
239 reg = in_be32((void __iomem *)cckctrl_port);
240 if (reg & CCKCTRL_ATACLKOEN) {
241 offset = 1; /* 133MHz */
242 } else {
243 offset = 0; /* 100MHz */
244 }
245
246 idx = speed - XFER_UDMA_0;
247
248 jcactsel = JCACTSELtbl[offset][idx];
249 if (is_slave) {
250 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
251 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
252 jcactsel = jcactsel << 2;
253 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
254 } else {
255 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
256 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
257 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
258 }
259 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
260 out_be32((void __iomem *)udenvt_port, reg);
261 }
262
263 static void scc_dma_host_set(ide_drive_t *drive, int on)
264 {
265 ide_hwif_t *hwif = drive->hwif;
266 u8 unit = (drive->select.b.unit & 0x01);
267 u8 dma_stat = scc_ide_inb(hwif->dma_status);
268
269 if (on)
270 dma_stat |= (1 << (5 + unit));
271 else
272 dma_stat &= ~(1 << (5 + unit));
273
274 scc_ide_outb(dma_stat, hwif->dma_status);
275 }
276
277 /**
278 * scc_ide_dma_setup - begin a DMA phase
279 * @drive: target device
280 *
281 * Build an IDE DMA PRD (IDE speak for scatter gather table)
282 * and then set up the DMA transfer registers.
283 *
284 * Returns 0 on success. If a PIO fallback is required then 1
285 * is returned.
286 */
287
288 static int scc_dma_setup(ide_drive_t *drive)
289 {
290 ide_hwif_t *hwif = drive->hwif;
291 struct request *rq = HWGROUP(drive)->rq;
292 unsigned int reading;
293 u8 dma_stat;
294
295 if (rq_data_dir(rq))
296 reading = 0;
297 else
298 reading = 1 << 3;
299
300 /* fall back to pio! */
301 if (!ide_build_dmatable(drive, rq)) {
302 ide_map_sg(drive, rq);
303 return 1;
304 }
305
306 /* PRD table */
307 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
308
309 /* specify r/w */
310 out_be32((void __iomem *)hwif->dma_command, reading);
311
312 /* read dma_status for INTR & ERROR flags */
313 dma_stat = in_be32((void __iomem *)hwif->dma_status);
314
315 /* clear INTR & ERROR flags */
316 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
317 drive->waiting_for_dma = 1;
318 return 0;
319 }
320
321 static void scc_dma_start(ide_drive_t *drive)
322 {
323 ide_hwif_t *hwif = drive->hwif;
324 u8 dma_cmd = scc_ide_inb(hwif->dma_command);
325
326 /* start DMA */
327 scc_ide_outb(dma_cmd | 1, hwif->dma_command);
328 hwif->dma = 1;
329 wmb();
330 }
331
332 static int __scc_dma_end(ide_drive_t *drive)
333 {
334 ide_hwif_t *hwif = drive->hwif;
335 u8 dma_stat, dma_cmd;
336
337 drive->waiting_for_dma = 0;
338 /* get DMA command mode */
339 dma_cmd = scc_ide_inb(hwif->dma_command);
340 /* stop DMA */
341 scc_ide_outb(dma_cmd & ~1, hwif->dma_command);
342 /* get DMA status */
343 dma_stat = scc_ide_inb(hwif->dma_status);
344 /* clear the INTR & ERROR bits */
345 scc_ide_outb(dma_stat | 6, hwif->dma_status);
346 /* purge DMA mappings */
347 ide_destroy_dmatable(drive);
348 /* verify good DMA status */
349 hwif->dma = 0;
350 wmb();
351 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
352 }
353
354 /**
355 * scc_dma_end - Stop DMA
356 * @drive: IDE drive
357 *
358 * Check and clear INT Status register.
359 * Then call __scc_dma_end().
360 */
361
362 static int scc_dma_end(ide_drive_t *drive)
363 {
364 ide_hwif_t *hwif = HWIF(drive);
365 unsigned long intsts_port = hwif->dma_base + 0x014;
366 u32 reg;
367 int dma_stat, data_loss = 0;
368 static int retry = 0;
369
370 /* errata A308 workaround: Step5 (check data loss) */
371 /* We don't check non ide_disk because it is limited to UDMA4 */
372 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
373 & ERR_STAT) &&
374 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
375 reg = in_be32((void __iomem *)intsts_port);
376 if (!(reg & INTSTS_ACTEINT)) {
377 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
378 drive->name);
379 data_loss = 1;
380 if (retry++) {
381 struct request *rq = HWGROUP(drive)->rq;
382 int unit;
383 /* ERROR_RESET and drive->crc_count are needed
384 * to reduce DMA transfer mode in retry process.
385 */
386 if (rq)
387 rq->errors |= ERROR_RESET;
388 for (unit = 0; unit < MAX_DRIVES; unit++) {
389 ide_drive_t *drive = &hwif->drives[unit];
390 drive->crc_count++;
391 }
392 }
393 }
394 }
395
396 while (1) {
397 reg = in_be32((void __iomem *)intsts_port);
398
399 if (reg & INTSTS_SERROR) {
400 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
401 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
402
403 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
404 continue;
405 }
406
407 if (reg & INTSTS_PRERR) {
408 u32 maea0, maec0;
409 unsigned long ctl_base = hwif->config_data;
410
411 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
412 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
413
414 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
415
416 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
417
418 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
419 continue;
420 }
421
422 if (reg & INTSTS_RERR) {
423 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
424 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
425
426 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
427 continue;
428 }
429
430 if (reg & INTSTS_ICERR) {
431 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
432
433 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
434 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
435 continue;
436 }
437
438 if (reg & INTSTS_BMSINT) {
439 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
440 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
441
442 ide_do_reset(drive);
443 continue;
444 }
445
446 if (reg & INTSTS_BMHE) {
447 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
448 continue;
449 }
450
451 if (reg & INTSTS_ACTEINT) {
452 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
453 continue;
454 }
455
456 if (reg & INTSTS_IOIRQS) {
457 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
458 continue;
459 }
460 break;
461 }
462
463 dma_stat = __scc_dma_end(drive);
464 if (data_loss)
465 dma_stat |= 2; /* emulate DMA error (to retry command) */
466 return dma_stat;
467 }
468
469 /* returns 1 if dma irq issued, 0 otherwise */
470 static int scc_dma_test_irq(ide_drive_t *drive)
471 {
472 ide_hwif_t *hwif = HWIF(drive);
473 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
474
475 /* SCC errata A252,A308 workaround: Step4 */
476 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
477 & ERR_STAT) &&
478 (int_stat & INTSTS_INTRQ))
479 return 1;
480
481 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
482 if (int_stat & INTSTS_IOIRQS)
483 return 1;
484
485 if (!drive->waiting_for_dma)
486 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
487 drive->name, __func__);
488 return 0;
489 }
490
491 static u8 scc_udma_filter(ide_drive_t *drive)
492 {
493 ide_hwif_t *hwif = drive->hwif;
494 u8 mask = hwif->ultra_mask;
495
496 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
497 if ((drive->media != ide_disk) && (mask & 0xE0)) {
498 printk(KERN_INFO "%s: limit %s to UDMA4\n",
499 SCC_PATA_NAME, drive->name);
500 mask = ATA_UDMA4;
501 }
502
503 return mask;
504 }
505
506 /**
507 * setup_mmio_scc - map CTRL/BMID region
508 * @dev: PCI device we are configuring
509 * @name: device name
510 *
511 */
512
513 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
514 {
515 unsigned long ctl_base = pci_resource_start(dev, 0);
516 unsigned long dma_base = pci_resource_start(dev, 1);
517 unsigned long ctl_size = pci_resource_len(dev, 0);
518 unsigned long dma_size = pci_resource_len(dev, 1);
519 void __iomem *ctl_addr;
520 void __iomem *dma_addr;
521 int i, ret;
522
523 for (i = 0; i < MAX_HWIFS; i++) {
524 if (scc_ports[i].ctl == 0)
525 break;
526 }
527 if (i >= MAX_HWIFS)
528 return -ENOMEM;
529
530 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
531 if (ret < 0) {
532 printk(KERN_ERR "%s: can't reserve resources\n", name);
533 return ret;
534 }
535
536 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
537 goto fail_0;
538
539 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
540 goto fail_1;
541
542 pci_set_master(dev);
543 scc_ports[i].ctl = (unsigned long)ctl_addr;
544 scc_ports[i].dma = (unsigned long)dma_addr;
545 pci_set_drvdata(dev, (void *) &scc_ports[i]);
546
547 return 1;
548
549 fail_1:
550 iounmap(ctl_addr);
551 fail_0:
552 return -ENOMEM;
553 }
554
555 static int scc_ide_setup_pci_device(struct pci_dev *dev,
556 const struct ide_port_info *d)
557 {
558 struct scc_ports *ports = pci_get_drvdata(dev);
559 ide_hwif_t *hwif = NULL;
560 hw_regs_t hw;
561 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
562 int i;
563
564 hwif = ide_find_port();
565 if (hwif == NULL) {
566 printk(KERN_ERR "%s: too many IDE interfaces, "
567 "no room in table\n", SCC_PATA_NAME);
568 return -ENOMEM;
569 }
570
571 memset(&hw, 0, sizeof(hw));
572 for (i = 0; i <= 8; i++)
573 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
574 hw.irq = dev->irq;
575 hw.dev = &dev->dev;
576 hw.chipset = ide_pci;
577 ide_init_port_hw(hwif, &hw);
578 hwif->dev = &dev->dev;
579
580 idx[0] = hwif->index;
581
582 ide_device_add(idx, d);
583
584 return 0;
585 }
586
587 /**
588 * init_setup_scc - set up an SCC PATA Controller
589 * @dev: PCI device
590 * @d: IDE port info
591 *
592 * Perform the initial set up for this device.
593 */
594
595 static int __devinit init_setup_scc(struct pci_dev *dev,
596 const struct ide_port_info *d)
597 {
598 unsigned long ctl_base;
599 unsigned long dma_base;
600 unsigned long cckctrl_port;
601 unsigned long intmask_port;
602 unsigned long mode_port;
603 unsigned long ecmode_port;
604 unsigned long dma_status_port;
605 u32 reg = 0;
606 struct scc_ports *ports;
607 int rc;
608
609 rc = pci_enable_device(dev);
610 if (rc)
611 goto end;
612
613 rc = setup_mmio_scc(dev, d->name);
614 if (rc < 0)
615 goto end;
616
617 ports = pci_get_drvdata(dev);
618 ctl_base = ports->ctl;
619 dma_base = ports->dma;
620 cckctrl_port = ctl_base + 0xff0;
621 intmask_port = dma_base + 0x010;
622 mode_port = ctl_base + 0x024;
623 ecmode_port = ctl_base + 0xf00;
624 dma_status_port = dma_base + 0x004;
625
626 /* controller initialization */
627 reg = 0;
628 out_be32((void*)cckctrl_port, reg);
629 reg |= CCKCTRL_ATACLKOEN;
630 out_be32((void*)cckctrl_port, reg);
631 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
632 out_be32((void*)cckctrl_port, reg);
633 reg |= CCKCTRL_CRST;
634 out_be32((void*)cckctrl_port, reg);
635
636 for (;;) {
637 reg = in_be32((void*)cckctrl_port);
638 if (reg & CCKCTRL_CRST)
639 break;
640 udelay(5000);
641 }
642
643 reg |= CCKCTRL_ATARESET;
644 out_be32((void*)cckctrl_port, reg);
645
646 out_be32((void*)ecmode_port, ECMODE_VALUE);
647 out_be32((void*)mode_port, MODE_JCUSFEN);
648 out_be32((void*)intmask_port, INTMASK_MSK);
649
650 rc = scc_ide_setup_pci_device(dev, d);
651
652 end:
653 return rc;
654 }
655
656 static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
657 {
658 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
659 struct ide_taskfile *tf = &task->tf;
660 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
661
662 if (task->tf_flags & IDE_TFLAG_FLAGGED)
663 HIHI = 0xFF;
664
665 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
666 out_be32((void *)io_ports->data_addr,
667 (tf->hob_data << 8) | tf->data);
668
669 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
670 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
671 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
672 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
673 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
674 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
675 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
676 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
677 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
678 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
679
680 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
681 scc_ide_outb(tf->feature, io_ports->feature_addr);
682 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
683 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
684 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
685 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
686 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
687 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
688 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
689 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
690
691 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
692 scc_ide_outb((tf->device & HIHI) | drive->select.all,
693 io_ports->device_addr);
694 }
695
696 static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
697 {
698 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
699 struct ide_taskfile *tf = &task->tf;
700
701 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
702 u16 data = (u16)in_be32((void *)io_ports->data_addr);
703
704 tf->data = data & 0xff;
705 tf->hob_data = (data >> 8) & 0xff;
706 }
707
708 /* be sure we're looking at the low order bits */
709 scc_ide_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
710
711 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
712 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
713 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
714 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
715 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
716 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
717 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
718 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
719 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
720 tf->device = scc_ide_inb(io_ports->device_addr);
721
722 if (task->tf_flags & IDE_TFLAG_LBA48) {
723 scc_ide_outb(drive->ctl | 0x80, io_ports->ctl_addr);
724
725 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
726 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
727 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
728 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
729 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
730 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
731 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
732 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
733 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
734 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
735 }
736 }
737
738 static void scc_input_data(ide_drive_t *drive, struct request *rq,
739 void *buf, unsigned int len)
740 {
741 unsigned long data_addr = drive->hwif->io_ports.data_addr;
742
743 len++;
744
745 if (drive->io_32bit) {
746 scc_ide_insl(data_addr, buf, len / 4);
747
748 if ((len & 3) >= 2)
749 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
750 } else
751 scc_ide_insw(data_addr, buf, len / 2);
752 }
753
754 static void scc_output_data(ide_drive_t *drive, struct request *rq,
755 void *buf, unsigned int len)
756 {
757 unsigned long data_addr = drive->hwif->io_ports.data_addr;
758
759 len++;
760
761 if (drive->io_32bit) {
762 scc_ide_outsl(data_addr, buf, len / 4);
763
764 if ((len & 3) >= 2)
765 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
766 } else
767 scc_ide_outsw(data_addr, buf, len / 2);
768 }
769
770 /**
771 * init_mmio_iops_scc - set up the iops for MMIO
772 * @hwif: interface to set up
773 *
774 */
775
776 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
777 {
778 struct pci_dev *dev = to_pci_dev(hwif->dev);
779 struct scc_ports *ports = pci_get_drvdata(dev);
780 unsigned long dma_base = ports->dma;
781
782 ide_set_hwifdata(hwif, ports);
783
784 hwif->tf_load = scc_tf_load;
785 hwif->tf_read = scc_tf_read;
786
787 hwif->input_data = scc_input_data;
788 hwif->output_data = scc_output_data;
789
790 hwif->INB = scc_ide_inb;
791 hwif->OUTB = scc_ide_outb;
792 hwif->OUTBSYNC = scc_ide_outbsync;
793
794 hwif->dma_base = dma_base;
795 hwif->config_data = ports->ctl;
796 }
797
798 /**
799 * init_iops_scc - set up iops
800 * @hwif: interface to set up
801 *
802 * Do the basic setup for the SCC hardware interface
803 * and then do the MMIO setup.
804 */
805
806 static void __devinit init_iops_scc(ide_hwif_t *hwif)
807 {
808 struct pci_dev *dev = to_pci_dev(hwif->dev);
809
810 hwif->hwif_data = NULL;
811 if (pci_get_drvdata(dev) == NULL)
812 return;
813 init_mmio_iops_scc(hwif);
814 }
815
816 static u8 __devinit scc_cable_detect(ide_hwif_t *hwif)
817 {
818 return ATA_CBL_PATA80;
819 }
820
821 /**
822 * init_hwif_scc - set up hwif
823 * @hwif: interface to set up
824 *
825 * We do the basic set up of the interface structure. The SCC
826 * requires several custom handlers so we override the default
827 * ide DMA handlers appropriately.
828 */
829
830 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
831 {
832 struct scc_ports *ports = ide_get_hwifdata(hwif);
833
834 ports->hwif = hwif;
835
836 hwif->dma_command = hwif->dma_base;
837 hwif->dma_status = hwif->dma_base + 0x04;
838
839 /* PTERADD */
840 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
841
842 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
843 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
844 else
845 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
846 }
847
848 static const struct ide_port_ops scc_port_ops = {
849 .set_pio_mode = scc_set_pio_mode,
850 .set_dma_mode = scc_set_dma_mode,
851 .udma_filter = scc_udma_filter,
852 .cable_detect = scc_cable_detect,
853 };
854
855 static const struct ide_dma_ops scc_dma_ops = {
856 .dma_host_set = scc_dma_host_set,
857 .dma_setup = scc_dma_setup,
858 .dma_exec_cmd = ide_dma_exec_cmd,
859 .dma_start = scc_dma_start,
860 .dma_end = scc_dma_end,
861 .dma_test_irq = scc_dma_test_irq,
862 .dma_lost_irq = ide_dma_lost_irq,
863 .dma_timeout = ide_dma_timeout,
864 };
865
866 #define DECLARE_SCC_DEV(name_str) \
867 { \
868 .name = name_str, \
869 .init_iops = init_iops_scc, \
870 .init_hwif = init_hwif_scc, \
871 .port_ops = &scc_port_ops, \
872 .dma_ops = &scc_dma_ops, \
873 .host_flags = IDE_HFLAG_SINGLE, \
874 .pio_mask = ATA_PIO4, \
875 }
876
877 static const struct ide_port_info scc_chipsets[] __devinitdata = {
878 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
879 };
880
881 /**
882 * scc_init_one - pci layer discovery entry
883 * @dev: PCI device
884 * @id: ident table entry
885 *
886 * Called by the PCI code when it finds an SCC PATA controller.
887 * We then use the IDE PCI generic helper to do most of the work.
888 */
889
890 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
891 {
892 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
893 }
894
895 /**
896 * scc_remove - pci layer remove entry
897 * @dev: PCI device
898 *
899 * Called by the PCI code when it removes an SCC PATA controller.
900 */
901
902 static void __devexit scc_remove(struct pci_dev *dev)
903 {
904 struct scc_ports *ports = pci_get_drvdata(dev);
905 ide_hwif_t *hwif = ports->hwif;
906
907 if (hwif->dmatable_cpu) {
908 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
909 hwif->dmatable_cpu, hwif->dmatable_dma);
910 hwif->dmatable_cpu = NULL;
911 }
912
913 ide_unregister(hwif);
914
915 iounmap((void*)ports->dma);
916 iounmap((void*)ports->ctl);
917 pci_release_selected_regions(dev, (1 << 2) - 1);
918 memset(ports, 0, sizeof(*ports));
919 }
920
921 static const struct pci_device_id scc_pci_tbl[] = {
922 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
923 { 0, },
924 };
925 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
926
927 static struct pci_driver driver = {
928 .name = "SCC IDE",
929 .id_table = scc_pci_tbl,
930 .probe = scc_init_one,
931 .remove = scc_remove,
932 };
933
934 static int scc_ide_init(void)
935 {
936 return ide_pci_register_driver(&driver);
937 }
938
939 module_init(scc_ide_init);
940 /* -- No exit code?
941 static void scc_ide_exit(void)
942 {
943 ide_pci_unregister_driver(&driver);
944 }
945 module_exit(scc_ide_exit);
946 */
947
948
949 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
950 MODULE_LICENSE("GPL");
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