arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <asm/hardware.h>
  21 #include <asm/irq.h>
  22 #include <asm/arch/irqs.h>
  23 #include <asm/arch/pxa-regs.h>
  24 #include <asm/arch/pxa2xx-regs.h>
  25 #include <asm/arch/ohci.h>
  26 #include <asm/arch/pm.h>
  27 #include <asm/arch/dma.h>
  28 #include <asm/arch/i2c.h>
  29
  30 #include "generic.h"
  31 #include "devices.h"
  32 #include "clock.h"
  33
  34 /* Crystal clock: 13MHz */
  35 #define BASE_CLK        13000000
  36
  37 /*
  38  * Get the clock frequency as reflected by CCSR and the turbo flag.
  39  * We assume these values have been applied via a fcs.
  40  * If info is not 0 we also display the current settings.
  41  */
  42 unsigned int pxa27x_get_clk_frequency_khz(int info)
  43 {
  44         unsigned long ccsr, clkcfg;
  45         unsigned int l, L, m, M, n2, N, S;
  46         int cccr_a, t, ht, b;
  47
  48         ccsr = CCSR;
  49         cccr_a = CCCR & (1 << 25);
  50
  51         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  52         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  53         t  = clkcfg & (1 << 0);
  54         ht = clkcfg & (1 << 2);
  55         b  = clkcfg & (1 << 3);
  56
  57         l  = ccsr & 0x1f;
  58         n2 = (ccsr>>7) & 0xf;
  59         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  60
  61         L  = l * BASE_CLK;
  62         N  = (L * n2) / 2;
  63         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  64         S  = (b) ? L : (L/2);
  65
  66         if (info) {
  67                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  68                         L / 1000000, (L % 1000000) / 10000, l );
  69                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  70                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
  71                         (t) ? "" : "in" );
  72                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
  73                         M / 1000000, (M % 1000000) / 10000, m );
  74                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
  75                         S / 1000000, (S % 1000000) / 10000 );
  76         }
  77
  78         return (t) ? (N/1000) : (L/1000);
  79 }
  80
  81 /*
  82  * Return the current mem clock frequency in units of 10kHz as
  83  * reflected by CCCR[A], B, and L
  84  */
  85 unsigned int pxa27x_get_memclk_frequency_10khz(void)
  86 {
  87         unsigned long ccsr, clkcfg;
  88         unsigned int l, L, m, M;
  89         int cccr_a, b;
  90
  91         ccsr = CCSR;
  92         cccr_a = CCCR & (1 << 25);
  93
  94         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  95         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  96         b = clkcfg & (1 << 3);
  97
  98         l = ccsr & 0x1f;
  99         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 100
 101         L = l * BASE_CLK;
 102         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 103
 104         return (M / 10000);
 105 }
 106
 107 /*
 108  * Return the current LCD clock frequency in units of 10kHz as
 109  */
 110 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 111 {
 112         unsigned long ccsr;
 113         unsigned int l, L, k, K;
 114
 115         ccsr = CCSR;
 116
 117         l = ccsr & 0x1f;
 118         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 119
 120         L = l * BASE_CLK;
 121         K = L / k;
 122
 123         return (K / 10000);
 124 }
 125
 126 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 127 {
 128         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 129 }
 130
 131 static const struct clkops clk_pxa27x_lcd_ops = {
 132         .enable         = clk_cken_enable,
 133         .disable        = clk_cken_disable,
 134         .getrate        = clk_pxa27x_lcd_getrate,
 135 };
 136
 137 static struct clk pxa27x_clks[] = {
 138         INIT_CK("LCDCLK", LCD,    &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
 139         INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
 140
 141         INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 142         INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
 143         INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 144
 145         INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
 146         INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
 147         INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa_device_udc.dev),
 148         INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
 149         INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
 150
 151         INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
 152         INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
 153         INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
 154
 155         INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
 156         INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
 157         INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 158
 159         /*
 160         INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
 161         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
 162         INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
 163         INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
 164         INIT_CKEN("IMCLK",   IM,   0, 0, NULL),
 165         INIT_CKEN("MEMCLK",  MEMC, 0, 0, NULL),
 166         */
 167 };
 168
 169 #ifdef CONFIG_PM
 170
 171 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 172 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 173
 174 #define RESTORE_GPLEVEL(n) do { \
 175         GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
 176         GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
 177 } while (0)
 178
 179 /*
 180  * List of global PXA peripheral registers to preserve.
 181  * More ones like CP and general purpose register values are preserved
 182  * with the stack pointer in sleep.S.
 183  */
 184 enum {  SLEEP_SAVE_START = 0,
 185
 186         SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
 187         SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
 188         SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
 189         SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
 190         SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
 191
 192         SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
 193         SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
 194         SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
 195         SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
 196
 197         SLEEP_SAVE_PSTR,
 198
 199         SLEEP_SAVE_ICMR,
 200         SLEEP_SAVE_CKEN,
 201
 202         SLEEP_SAVE_MDREFR,
 203         SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
 204         SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
 205
 206         SLEEP_SAVE_SIZE
 207 };
 208
 209 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 210 {
 211         SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
 212         SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
 213         SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
 214         SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
 215         SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
 216
 217         SAVE(GAFR0_L); SAVE(GAFR0_U);
 218         SAVE(GAFR1_L); SAVE(GAFR1_U);
 219         SAVE(GAFR2_L); SAVE(GAFR2_U);
 220         SAVE(GAFR3_L); SAVE(GAFR3_U);
 221
 222         SAVE(MDREFR);
 223         SAVE(PWER); SAVE(PCFR); SAVE(PRER);
 224         SAVE(PFER); SAVE(PKWR);
 225
 226         SAVE(ICMR); ICMR = 0;
 227         SAVE(CKEN);
 228         SAVE(PSTR);
 229
 230         /* Clear GPIO transition detect bits */
 231         GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
 232 }
 233
 234 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 235 {
 236         /* ensure not to come back here if it wasn't intended */
 237         PSPR = 0;
 238
 239         /* restore registers */
 240         RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
 241         RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
 242         RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
 243         RESTORE(GAFR0_L); RESTORE(GAFR0_U);
 244         RESTORE(GAFR1_L); RESTORE(GAFR1_U);
 245         RESTORE(GAFR2_L); RESTORE(GAFR2_U);
 246         RESTORE(GAFR3_L); RESTORE(GAFR3_U);
 247         RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
 248         RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
 249         RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
 250
 251         RESTORE(MDREFR);
 252         RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
 253         RESTORE(PFER); RESTORE(PKWR);
 254
 255         PSSR = PSSR_RDH | PSSR_PH;
 256
 257         RESTORE(CKEN);
 258
 259         ICLR = 0;
 260         ICCR = 1;
 261         RESTORE(ICMR);
 262         RESTORE(PSTR);
 263 }
 264
 265 void pxa27x_cpu_pm_enter(suspend_state_t state)
 266 {
 267         extern void pxa_cpu_standby(void);
 268
 269         /* ensure voltage-change sequencer not initiated, which hangs */
 270         PCFR &= ~PCFR_FVC;
 271
 272         /* Clear edge-detect status register. */
 273         PEDR = 0xDF12FE1B;
 274
 275         switch (state) {
 276         case PM_SUSPEND_STANDBY:
 277                 pxa_cpu_standby();
 278                 break;
 279         case PM_SUSPEND_MEM:
 280                 /* set resume return address */
 281                 PSPR = virt_to_phys(pxa_cpu_resume);
 282                 pxa27x_cpu_suspend(PWRMODE_SLEEP);
 283                 break;
 284         }
 285 }
 286
 287 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 288 {
 289         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 290 }
 291
 292 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 293         .save_size      = SLEEP_SAVE_SIZE,
 294         .save           = pxa27x_cpu_pm_save,
 295         .restore        = pxa27x_cpu_pm_restore,
 296         .valid          = pxa27x_cpu_pm_valid,
 297         .enter          = pxa27x_cpu_pm_enter,
 298 };
 299
 300 static void __init pxa27x_init_pm(void)
 301 {
 302         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 303 }
 304 #else
 305 static inline void pxa27x_init_pm(void) {}
 306 #endif
 307
 308 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 309  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 310  */
 311 #define PXA27x_GPIO_NOWAKE_MASK \
 312         ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
 313 #define WAKEMASK(gpio) \
 314         (((gpio) <= 15) \
 315                  ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
 316                  : ((gpio == 35) ? (1 << 24) : 0))
 317
 318 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 319 {
 320         int gpio = IRQ_TO_GPIO(irq);
 321         uint32_t mask;
 322
 323         if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
 324                 if (WAKEMASK(gpio) == 0)
 325                         return -EINVAL;
 326
 327                 mask = WAKEMASK(gpio);
 328
 329                 if (on) {
 330                         if (GRER(gpio) | GPIO_bit(gpio))
 331                                 PRER |= mask;
 332                         else
 333                                 PRER &= ~mask;
 334
 335                         if (GFER(gpio) | GPIO_bit(gpio))
 336                                 PFER |= mask;
 337                         else
 338                                 PFER &= ~mask;
 339                 }
 340                 goto set_pwer;
 341         }
 342
 343         switch (irq) {
 344         case IRQ_RTCAlrm:
 345                 mask = PWER_RTC;
 346                 break;
 347         case IRQ_USB:
 348                 mask = 1u << 26;
 349                 break;
 350         default:
 351                 return -EINVAL;
 352         }
 353
 354 set_pwer:
 355         if (on)
 356                 PWER |= mask;
 357         else
 358                 PWER &=~mask;
 359
 360         return 0;
 361 }
 362
 363 void __init pxa27x_init_irq(void)
 364 {
 365         pxa_init_irq_low();
 366         pxa_init_irq_high();
 367         pxa_init_irq_gpio(128);
 368         pxa_init_irq_set_wake(pxa27x_set_wake);
 369 }
 370
 371 /*
 372  * device registration specific to PXA27x.
 373  */
 374
 375 static struct resource i2c_power_resources[] = {
 376         {
 377                 .start  = 0x40f00180,
 378                 .end    = 0x40f001a3,
 379                 .flags  = IORESOURCE_MEM,
 380         }, {
 381                 .start  = IRQ_PWRI2C,
 382                 .end    = IRQ_PWRI2C,
 383                 .flags  = IORESOURCE_IRQ,
 384         },
 385 };
 386
 387 struct platform_device pxa27x_device_i2c_power = {
 388         .name           = "pxa2xx-i2c",
 389         .id             = 1,
 390         .resource       = i2c_power_resources,
 391         .num_resources  = ARRAY_SIZE(i2c_power_resources),
 392 };
 393
 394 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 395 {
 396         pxa27x_device_i2c_power.dev.platform_data = info;
 397 }
 398
 399 static struct platform_device *devices[] __initdata = {
 400         &pxa_device_udc,
 401         &pxa_device_ffuart,
 402         &pxa_device_btuart,
 403         &pxa_device_stuart,
 404         &pxa_device_i2s,
 405         &pxa_device_rtc,
 406         &pxa27x_device_i2c_power,
 407         &pxa27x_device_ssp1,
 408         &pxa27x_device_ssp2,
 409         &pxa27x_device_ssp3,
 410 };
 411
 412 static int __init pxa27x_init(void)
 413 {
 414         int ret = 0;
 415         if (cpu_is_pxa27x()) {
 416                 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
 417
 418                 if ((ret = pxa_init_dma(32)))
 419                         return ret;
 420
 421                 pxa27x_init_pm();
 422
 423                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 424         }
 425         return ret;
 426 }
 427
 428 subsys_initcall(pxa27x_init);