arch/x86_64/kernel/genapic_cluster.c

   1 /*
   2  * Copyright 2004 James Cleverdon, IBM.
   3  * Subject to the GNU Public License, v.2
   4  *
   5  * Clustered APIC subarch code.  Up to 255 CPUs, physical delivery.
   6  * (A more realistic maximum is around 230 CPUs.)
   7  *
   8  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
   9  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
  10  * James Cleverdon.
  11  */
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <asm/smp.h>
  19 #include <asm/ipi.h>
  20
  21
  22 /*
  23  * Set up the logical destination ID.
  24  *
  25  * Intel recommends to set DFR, LDR and TPR before enabling
  26  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  27  * document number 292116).  So here it goes...
  28  */
  29 static void cluster_init_apic_ldr(void)
  30 {
  31         unsigned long val, id;
  32         long i, count;
  33         u8 lid;
  34         u8 my_id = hard_smp_processor_id();
  35         u8 my_cluster = APIC_CLUSTER(my_id);
  36
  37         /* Create logical APIC IDs by counting CPUs already in cluster. */
  38         for (count = 0, i = NR_CPUS; --i >= 0; ) {
  39                 lid = x86_cpu_to_log_apicid[i];
  40                 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
  41                         ++count;
  42         }
  43         /*
  44          * We only have a 4 wide bitmap in cluster mode.  There's no way
  45          * to get above 60 CPUs and still give each one it's own bit.
  46          * But, we're using physical IRQ delivery, so we don't care.
  47          * Use bit 3 for the 4th through Nth CPU in each cluster.
  48          */
  49         if (count >= XAPIC_DEST_CPUS_SHIFT)
  50                 count = 3;
  51         id = my_cluster | (1UL << count);
  52         x86_cpu_to_log_apicid[smp_processor_id()] = id;
  53         apic_write(APIC_DFR, APIC_DFR_CLUSTER);
  54         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  55         val |= SET_APIC_LOGICAL_ID(id);
  56         apic_write(APIC_LDR, val);
  57 }
  58
  59 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  60
  61 static cpumask_t cluster_target_cpus(void)
  62 {
  63         return cpumask_of_cpu(0);
  64 }
  65
  66 static cpumask_t cluster_vector_allocation_domain(int cpu)
  67 {
  68         cpumask_t domain = CPU_MASK_NONE;
  69         cpu_set(cpu, domain);
  70         return domain;
  71 }
  72
  73 static void cluster_send_IPI_mask(cpumask_t mask, int vector)
  74 {
  75         send_IPI_mask_sequence(mask, vector);
  76 }
  77
  78 static void cluster_send_IPI_allbutself(int vector)
  79 {
  80         cpumask_t mask = cpu_online_map;
  81
  82         cpu_clear(smp_processor_id(), mask);
  83
  84         if (!cpus_empty(mask))
  85                 cluster_send_IPI_mask(mask, vector);
  86 }
  87
  88 static void cluster_send_IPI_all(int vector)
  89 {
  90         cluster_send_IPI_mask(cpu_online_map, vector);
  91 }
  92
  93 static int cluster_apic_id_registered(void)
  94 {
  95         return 1;
  96 }
  97
  98 static unsigned int cluster_cpu_mask_to_apicid(cpumask_t cpumask)
  99 {
 100         int cpu;
 101
 102         /*
 103          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 104          * May as well be the first.
 105          */
 106         cpu = first_cpu(cpumask);
 107         if ((unsigned)cpu < NR_CPUS)
 108                 return x86_cpu_to_apicid[cpu];
 109         else
 110                 return BAD_APICID;
 111 }
 112
 113 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 114  * register's value.  For any box whose BIOS changes APIC IDs, like
 115  * clustered APIC systems, we must use hard_smp_processor_id.
 116  *
 117  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 118  */
 119 static unsigned int phys_pkg_id(int index_msb)
 120 {
 121         return hard_smp_processor_id() >> index_msb;
 122 }
 123
 124 struct genapic apic_cluster = {
 125         .name = "clustered",
 126         .int_delivery_mode = dest_Fixed,
 127         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 128         .target_cpus = cluster_target_cpus,
 129         .vector_allocation_domain = cluster_vector_allocation_domain,
 130         .apic_id_registered = cluster_apic_id_registered,
 131         .init_apic_ldr = cluster_init_apic_ldr,
 132         .send_IPI_all = cluster_send_IPI_all,
 133         .send_IPI_allbutself = cluster_send_IPI_allbutself,
 134         .send_IPI_mask = cluster_send_IPI_mask,
 135         .cpu_mask_to_apicid = cluster_cpu_mask_to_apicid,
 136         .phys_pkg_id = phys_pkg_id,
 137 };